CN102681274B - Liquid crystal display array substrate and manufacturing method thereof - Google Patents
Liquid crystal display array substrate and manufacturing method thereof Download PDFInfo
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- CN102681274B CN102681274B CN201110294949.3A CN201110294949A CN102681274B CN 102681274 B CN102681274 B CN 102681274B CN 201110294949 A CN201110294949 A CN 201110294949A CN 102681274 B CN102681274 B CN 102681274B
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- data line
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- scan line
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Abstract
The invention discloses a liquid crystal display array substrate and a manufacturing method thereof. The liquid crystal display array substrate is designed to reduce parasitic capacitance generated between a data wire and a grid scanning wire of the existing array substrate. The array substrate comprises a substrate, and a data wire and a grid scanning wire which are arranged on the substrate in stagger; one of the date wire and the grid scanning wire is disconnected at a stagger area of the date wire and the grid scanning wire, so that two ends are positioned at two sides of the grid scanning wire or the data wire; a lead bridging the data wire or the grid scanning wire is arranged above the disconnecting part of the data wire or the grid scanning wire; an isolation layer and a protection layer are arranged between the lead and the data wire or the grid scanning wire; and the lead is connected with the disconnected data wire or the grid scanning wire through penetrating through a through hole of the protection layer. By adopting the structure, the parasitic capacitance between the data wire and the grid scanning wire on the substrate is reduced; and the delay of the grid scanning wire and the date wire and a kickback voltage instantly generated when a thin film transistor is turned off are reduced.
Description
Technical field
The present invention relates to technical field of liquid crystal display, particularly relate to a kind of LCD (Liquid Crystal Display) array substrate and manufacture method thereof.
Background technology
TFT-LCD (Thin Film Transistor-LCD) because of its volume little, low in energy consumption, the feature such as radiationless, occupies the leading position in current flat panel display market.TFT-LCD device is become box-like with color film glass substrate by array glass substrate.In array base palte, be provided with controlling grid scan line 3 and the data line 1 of definition pixel region as shown in Figure 1 staggered relative, pixel electrode 2 and thin film transistor (TFT) are set in each pixel region.Drive singal is applied on controlling grid scan line 3, and viewdata signal is applied on pixel electrode by data line 1.Color membrane substrates configures black matrix, light through the region except pixel electrode, can not be arranged color rete at each pixel region, arrange public electrode more on this basis.In array base palte and color membrane substrates, be filled with liquid crystal, controlled the deflection of liquid crystal by above-mentioned drive singal and pixel electrode voltage, thus control the power of light, match with color membrane substrates, displays image information on substrate.
At present, the controlling grid scan line 3 of the array glass substrate of the TFT-LCD of main flow and data line 1 are mutual juxtaposition (as shown in Figure 1), the two is separated by insulation course, namely in traditional TFT-LCD manufacturing process, directly be formed with active layer on insulation course, then data line 1 is formed at active layer, the various piece of pixel electrode 2.Controlling grid scan line 3 and data line 1 also exist juxtaposition, and mutual close together, therefore easily produce capacity effect between them.When data line creates stray capacitance C with between controlling grid scan line
gd, just can increase the delay of controlling grid scan line and data line, and in the moment that thin film transistor (TFT) cuts out, controlling grid scan line can produce a kick-back voltage Δ V by stray capacitance to pixel electrode
p, because of the inconsistent formation film flicker of positive and negative pressure when this kick-back voltage can make pixel electrode do reversal.
Summary of the invention
For the problems referred to above, the object of the present invention is to provide a kind of LCD (Liquid Crystal Display) array substrate and the manufacture method thereof that effectively can reduce the stray capacitance of available data line and the generation of controlling grid scan line staggered place.
For achieving the above object, LCD (Liquid Crystal Display) array substrate of the present invention, comprises substrate, is formed at the data line be crisscross arranged on substrate and controlling grid scan line,
At described data line and controlling grid scan line interlaced area place; one of them of described data line and controlling grid scan line disconnects and makes two broken ends be in the both sides of respective gates sweep trace or data line; the wire of data line or controlling grid scan line described in a cross-over connection is provided with above described data line or controlling grid scan line gap; and being provided with an insulation course and a protective seam between described wire and controlling grid scan line or data line, described wire is by connecting the data line or controlling grid scan line that disconnect through the via hole of protective seam.
Further, described LCD (Liquid Crystal Display) array substrate also comprises pixel electrode, and described wire is identical with pixel electrode material.
Preferably, described wire and pixel electrode material are tin indium oxide, IZO layer or indium oxide gallium zinc layers.
Further, described data line and described controlling grid scan line are in same metal level.
Further, described data line place metal level is on the metal level of described controlling grid scan line place.
Further, described controlling grid scan line place metal level is on the metal level of described data line place.
The manufacture method of LCD (Liquid Crystal Display) array substrate of the present invention, comprises the steps:
Step 1, on substrate, form metallic film, form controlling grid scan line or data line by photoetching process and etching technics;
Step 2, on the substrate of completing steps 1, form insulation course;
Step 3, on the substrate of completing steps 2, form metal level, then form data line or controlling grid scan line by the region beyond photoetching process and etching technics are directly over described controlling grid scan line or data line;
Step 4, on the substrate of completing steps 3, form protects material layer, then above data line or controlling grid scan line, form the protective seam with via hole by photoetching process, expose data line or controlling grid scan line;
Step 5, on the substrate of completing steps 4, form conductive layer, this conductive layer connects by the two place's via holes formed in step 4 controlling grid scan line or the data line that are in described data line or controlling grid scan line both sides, and recycling photoetching process makes conductive layer form wire.
Further, the described photoetching process that utilizes makes conductive layer be formed while wire, forms pixel electrode.
Preferably, described conductive layer is tin indium oxide, indium zinc oxide or indium oxide gallium zinc layers.
The invention has the beneficial effects as follows: the present invention is connected by recycling wire after one of them disconnects with controlling grid scan line staggered place by data line; layer protective layer can be increased between wire and data line or controlling grid scan line, effectively can reduce data line like this with the stray capacitance C between controlling grid scan line
gdand then decrease the delay of controlling grid scan line and data line, reduce the kick-back voltage to pixel electrode that thin film transistor (TFT) produced in the moment of cutting out, improve pixel electrode under same GTG when doing reversal of poles, the pressure reduction because of positive-negative polarity is inconsistent and form the phenomenon of film flicker.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of data line and controlling grid scan line juxtaposition on available liquid crystal display array substrate;
Fig. 2 is the partial top view of LCD (Liquid Crystal Display) array substrate of the present invention;
Fig. 3 be in Fig. 2 A-A to cut-open view;
Fig. 4 is the partial top view of another embodiment of LCD (Liquid Crystal Display) array substrate of the present invention;
Fig. 5 a is the schematic cross-section form metallic film on substrate after;
Fig. 5 b forms the schematic cross-section after controlling grid scan line by photoetching process and etching technics;
Fig. 6 is the schematic cross-section form insulation course on the substrate forming controlling grid scan line after;
Fig. 7 a is the schematic cross-section form metal level again on the substrate having formed insulation course after;
Fig. 7 b forms the schematic cross-section after data line by the region beyond photoetching process and etching technics are directly over described controlling grid scan line;
Fig. 8 a is the schematic cross-section form protective seam on the substrate forming data line after;
Fig. 8 b be by photoetching process and etching technics formed above the data line being in described controlling grid scan line both sides via hole expose the data line of controlling grid scan line both sides after schematic cross-section;
Fig. 9 is the schematic cross-section form oxide semiconductor layer on the substrate defining protective seam after.
Embodiment
Below in conjunction with Figure of description, the specific embodiment of the present invention is described in detail.
Embodiment 1
As shown in Figures 2 and 3, LCD (Liquid Crystal Display) array substrate of the present invention, comprise substrate 7, be formed at the data line 1 be crisscross arranged on substrate 7 and controlling grid scan line 3, controlling grid scan line 3 and data line 1 enclose the pixel region 2 of formation, and described data line 1 place metal level is on the metal level of described controlling grid scan line 3 place or belongs to layer of metal layer together; When described data line 1 place metal level is on the metal level of described controlling grid scan line 3 place, separated by insulation course 8 between described controlling grid scan line 3 and data line 1.In described data line 1 and controlling grid scan line 3 interlaced area, described data line 1 disconnects, and two ends is in the both sides of controlling grid scan line 3 respectively, and is provided with the wire 6 of data line 1 described in a cross-over connection above described data line 1 gap; This wire 6 is identical with pixel electrode 2 material, and described wire 6 is tin indium oxide, IZO layer or indium oxide gallium zinc layers with pixel electrode 2 material.
A protective seam 9 is provided with between described wire 6 and the data line 1 of described disconnection; this protective seam 9 is provided with via hole 51 and 52 respectively above the data line 1 being in controlling grid scan line 3 both sides, and described wire 6 is connected the data line 1 being in controlling grid scan line 3 both sides with 52 by this via hole 51.
Embodiment 2
As shown in Figure 4, LCD (Liquid Crystal Display) array substrate of the present invention, comprise substrate, be formed at the data line 1 be crisscross arranged on substrate and controlling grid scan line 3, controlling grid scan line 3 and data line 1 enclose the pixel region 2 of formation, and described data line 1 place metal level is under the metal level of controlling grid scan line 3 place or is in and belongs to layer of metal layer together; When described data line 1 place metal level is under the metal level of controlling grid scan line 3 place, separated by insulation course between described data line 1 and controlling grid scan line 3.In described data line 1 and controlling grid scan line 3 interlaced area, described controlling grid scan line 3 disconnects, and it disconnects the both sides that termination is in data line 1 respectively, and above described controlling grid scan line 3 gap, be provided with the wire 6 of controlling grid scan line 3 described in a cross-over connection; Wire 6 described in the present embodiment connects the mode of the controlling grid scan line 3 disconnected with embodiment 1; namely by the via hole on the protective seam between described wire 6 and described controlling grid scan line 3 realize connect; in addition, described wire 6 also connects described data line or the controlling grid scan line of disconnection by other modes.Preferably, wire 6 described in the present embodiment is identical with pixel electrode 2 material, and described wire 6 is tin indium oxide, IZO layer or indium oxide gallium zinc layers with pixel electrode 2 material.
As can be seen from the above embodiments, controlling grid scan line described in the present invention can be various arrangement order with the positional structure of data line, namely controlling grid scan line is same metal level with data line, or described data line place metal level is on the metal level of described controlling grid scan line place, or described controlling grid scan line place metal level is on the metal level of described data line place.If controlling grid scan line is same metal level with data line, now the data line of controlling grid scan line interlaced area or all available tin indium oxide (ITO) of controlling grid scan line, indium zinc oxide (IZO) or indium oxide gallium zinc layers (IGZO) is followed to replace at data line.If data line is at the bottom near glass substrate, controlling grid scan line is on data line, now can replace the gate metal of interlaced area at data line by tin indium oxide (ITO), indium zinc oxide (IZO) or indium oxide gallium zinc layers (IGZO) with controlling grid scan line interlaced area, and utilize via hole that the controlling grid scan line of data line both sides is coupled together.If data line place metal level is on the metal level of described controlling grid scan line place (as shown in Figure 3), now, the data line of interlaced area can be replaced at data line by tin indium oxide (ITO), indium zinc oxide (IZO) or indium oxide gallium zinc layers (IGZO) with controlling grid scan line interlaced area, and utilize via hole that the data line of controlling grid scan line both sides is coupled together.
The present invention revises data line in the place staggered with controlling grid scan line, utilize tin indium oxide or indium zinc oxide or indium oxide gallium zinc layers oxide semiconductor layer to replace data line or the controlling grid scan line of intervening portion, and utilize via hole to be connected to data line or the controlling grid scan line of the disconnection of intervening portion place.The present invention owing to adding data line with the distance between grid metal lines, so data line can be reduced with the stray capacitance C between controlling grid scan line
gd, thus decrease the delay of controlling grid scan line and data line, and make kick-back voltage Δ V further
preduce, so just can improve pixel electrode under same GTG when doing reversal of poles, because the pressure reduction of positive-negative polarity is inconsistent, and form the phenomenon of film flicker.
LCD (Liquid Crystal Display) array substrate of the present invention is by method manufacture below:
Embodiment 3
1, as shown in Figure 5 a, substrate 7 forms metallic film, this metallic film material can use the metals such as molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper, also can use the combination of above-mentioned material film; Then as shown in Figure 5 b, controlling grid scan line 3 is formed by photoetching process and etching technics;
2, on the substrate 7 forming controlling grid scan line, insulation course 8 is formed, as shown in Figure 6;
3, as shown in Figure 7a, the substrate 7 having deposited insulation course forms metal level again, then form data line 1 by the region beyond photoetching process and etching technics are directly over described controlling grid scan line 3, as shown in Figure 7b;
4, as shown in Figure 8 a, the substrate 7 forming data line forms protects material layer, then above data line 1, forms the protective seam 9 with via hole 51 and 52 by photoetching process, expose data line 1; As shown in Figure 8 b;
5, as shown in Figure 9, the substrate 7 of completing steps 4 forms conductive layer, this conductive layer is connected by the two place's via holes 51 formed in step 4 data line 1 being in described controlling grid scan line 3 both sides with 52, and recycling photoetching process makes conductive layer form wire 6.
Embodiment 4
1, on substrate, form metallic film, form data line by photoetching process and etching technics;
2, on the substrate forming data line, insulation course is formed;
3, on the substrate forming insulation course, form gate metal layer again, then form controlling grid scan line by the region beyond photoetching process and etching technics are directly over described data line;
4, on the substrate forming controlling grid scan line, form protects material layer, and then above the controlling grid scan line being in described data line both sides, form the protective seam with via hole by photoetching process or etching technics, expose the controlling grid scan line of data line both sides;
5, conductive layer on the substrate defining protective seam, described conductive layer connects by the two place's via holes formed in step 4 controlling grid scan line being in described data line both sides, and recycling photoetching process makes conductive layer form wire.
The described conductive layer that in above-described embodiment 3 and embodiment 4, final step is formed is preferably tin indium oxide or indium zinc oxide or indium oxide gallium zinc layers.
Above; be only preferred embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.Therefore, the protection domain that protection scope of the present invention should define with claim is as the criterion.
Claims (6)
1. a LCD (Liquid Crystal Display) array substrate, comprises substrate, is formed at the data line be crisscross arranged on substrate and controlling grid scan line, it is characterized in that,
Described data line place metal level is on the metal level of described controlling grid scan line place; Or described controlling grid scan line place metal level is on the metal level of described data line place; Separated by insulation course between described controlling grid scan line and described data line;
At described data line and controlling grid scan line interlaced area place; one of them being positioned at the described data line of top and controlling grid scan line disconnects and two broken ends is in be correspondingly positioned at the controlling grid scan line of below or the both sides of data line; the wire of data line or controlling grid scan line described in a cross-over connection is provided with above described data line or controlling grid scan line gap; and being provided with a protective seam between described wire and data line or controlling grid scan line, described wire is by connecting the data line or controlling grid scan line that disconnect through the via hole of protective seam.
2. LCD (Liquid Crystal Display) array substrate according to claim 1, it is characterized in that, described LCD (Liquid Crystal Display) array substrate also comprises pixel electrode, and described wire is identical with pixel electrode material.
3. LCD (Liquid Crystal Display) array substrate according to claim 2, it is characterized in that, described wire and pixel electrode material are tin indium oxide, IZO layer or indium oxide gallium zinc layers.
4. a manufacture method for LCD (Liquid Crystal Display) array substrate according to claim 1, is characterized in that, comprises the steps:
Step 1, on substrate, form metallic film, form controlling grid scan line or data line by photoetching process and etching technics;
Step 2, on the substrate of completing steps 1, form insulation course;
Step 3, on the substrate of completing steps 2, form metal level, then form data line or controlling grid scan line by the region beyond photoetching process and etching technics are directly over described controlling grid scan line or data line;
Step 4, on the substrate of completing steps 3, form protects material layer, then above data line or controlling grid scan line, form the protective seam with via hole by photoetching process, expose data line or controlling grid scan line;
Step 5, on the substrate of completing steps 4, form conductive layer, this conductive layer connects by the two place's via holes formed in step 4 controlling grid scan line or the data line that are in described data line or controlling grid scan line both sides, and recycling photoetching process makes conductive layer form wire.
5. the manufacture method of LCD (Liquid Crystal Display) array substrate according to claim 4, is characterized in that, the described photoetching process that utilizes makes conductive layer be formed while wire, forms pixel electrode.
6. the manufacture method of LCD (Liquid Crystal Display) array substrate according to claim 4, is characterized in that, described conductive layer is tin indium oxide, indium zinc oxide or indium oxide gallium zinc layers.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110294949.3A CN102681274B (en) | 2011-09-29 | 2011-09-29 | Liquid crystal display array substrate and manufacturing method thereof |
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| CN201110294949.3A CN102681274B (en) | 2011-09-29 | 2011-09-29 | Liquid crystal display array substrate and manufacturing method thereof |
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| CN102681274B true CN102681274B (en) | 2015-04-01 |
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| CN104076566B (en) * | 2014-07-21 | 2017-09-22 | 深圳市华星光电技术有限公司 | Display panel, array base palte and preparation method thereof |
| CN108803170B (en) * | 2018-06-22 | 2021-10-08 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| WO2020065962A1 (en) * | 2018-09-28 | 2020-04-02 | シャープ株式会社 | Display device |
| CN109254461A (en) * | 2018-10-22 | 2019-01-22 | 惠科股份有限公司 | display panel and display |
| CN109272882B (en) * | 2018-12-10 | 2024-03-29 | 云赛智联股份有限公司 | Transparent small-spacing LED display screen |
| JP6952819B2 (en) * | 2019-12-13 | 2021-10-27 | ラピスセミコンダクタ株式会社 | Source driver and display device |
| WO2023245355A1 (en) * | 2022-06-20 | 2023-12-28 | 京东方科技集团股份有限公司 | Array substrate, display panel, and display device |
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| CN1794074A (en) * | 2005-12-29 | 2006-06-28 | 友达光电股份有限公司 | Manufacturing method of film transistor matrix substrate |
| CN101051645A (en) * | 2007-04-29 | 2007-10-10 | 友达光电股份有限公司 | Pixel array substrate |
| CN101840121A (en) * | 2009-03-20 | 2010-09-22 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof |
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| KR100789090B1 (en) * | 2002-12-30 | 2007-12-26 | 엘지.필립스 엘시디 주식회사 | Method for manufacturing lcd |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1794074A (en) * | 2005-12-29 | 2006-06-28 | 友达光电股份有限公司 | Manufacturing method of film transistor matrix substrate |
| CN101051645A (en) * | 2007-04-29 | 2007-10-10 | 友达光电股份有限公司 | Pixel array substrate |
| CN101840121A (en) * | 2009-03-20 | 2010-09-22 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof |
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