CN1794074A - Manufacturing method of film transistor matrix substrate - Google Patents
Manufacturing method of film transistor matrix substrate Download PDFInfo
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- CN1794074A CN1794074A CN 200510137514 CN200510137514A CN1794074A CN 1794074 A CN1794074 A CN 1794074A CN 200510137514 CN200510137514 CN 200510137514 CN 200510137514 A CN200510137514 A CN 200510137514A CN 1794074 A CN1794074 A CN 1794074A
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Abstract
A method for preparing base board with film transistor array includes forming island semiconductor above grid dielectric layer above grid electrode with grid width being greater than width of island semiconductor; forming lap hole on insulation layer covered above island semiconductor to expose partial island semiconductor; forming ohm contact by injecting ion on exposed island semiconductor surface and forming transparent conductive layer to clad above all structures; carrying out micro image etching process to define out source/ drain electrode, pixel electrode, grid electrode pad and signal electrode pad.
Description
Technical field
The invention relates to a kind of manufacture method of display panels, and especially in regard to a kind of manufacture method of film transistor matrix substrate.
Background technology
The photoelectricity correlation technique is constantly weeded out the old and bring forth the new in recent years, adds the arrival of digital times, and then has promoted the flourish of LCD market.LCD has that high image quality, volume are little, in light weight, low driving voltage, with advantage such as low consumpting power, therefore be widely used in PDA(Personal Digital Assistant), mobile phone, shoot with video-corder projector, mobile computer, desktop display, automobile-used display, and consumer communication or electronic product such as projection TV, and replace cathode-ray tube (CRT) gradually and become the main flow of display.
LCD (Liquid Crystal Display, LCD) be a kind of display device of utilizing liquid crystal characteristic to reach display effect, because its traditional cathode-ray tube display commonly used has better elasticity aspect dimension and weight, therefore, LCD often is used on the various pss at present, little display screen on mobile phone, personal digital assistant and digital camera arrives televisor and advertisement plate greatly, can see the shadow of LCD everywhere.
So LCD can be more traditional cathode-ray tube display more flexible in size and weight, be because most assembly of LCD all is flat, therefore visual application demand cuts into moderate size with these assemblies, also has the cathode-ray tube (CRT) of huge three-dimensional profile to come lightly manyly on weight.
The expensive price of well known mask, the mask number is many more to mean that promptly the cost of required payment is high more, in addition, manufacturing time also can be long more, so reduce the mask number, except can reducing cost, can also quicken the speed of response, increases competitiveness of product.Therefore, the present invention reaches at known shortcoming, reduces the employed mask number of amorphous silicon LCD Panel technology, promptly reduces the cost of making, and makes product have more competitive power.
In the technology of general film transistor matrix substrate, employed mask count can be tapered to five roads or four road mask process.Fig. 1 illustrates the formed film transistor matrix substrate diagrammatic cross-section of traditional four road mask process.As shown in Figure 1; on glass substrate 100, has grid 102; dielectric layer 104 cover gate 102; semiconductor layer 106 covers dielectric layer 104; ohmic contact layer 108; 110 of electrode layers are positioned on the ohmic contact layer 108, and the opening disjunction is positioned at the ohmic contact layer 108 and the electrode layer 110 of grid 102 tops, and insulating protective layer 114 is covered on the structure of glass substrate 100.When film transistor matrix substrate is subjected to 116 whens irradiation backlight, semiconductor layer 106 can produce photocurrents and change thin film transistor (TFT) electrically.
Be example with general four road mask process again, Fig. 2 illustrates the diagrammatic cross-section of the committed step of reduction use mask count in the processes well known.On glass substrate 100, have grid 102, form dielectric layer 104, semiconductor layer 106, ohmic contact layer 108, electrode layer 110 in regular turn on glass substrate 100.Behind coating photoresist layer (not being illustrated on the figure), expose with half mode (half-tone) mask again and carry out follow-up development step, and formation patterning photoresist layer 112, patterning photoresist layer 112 desire above grid 102 forms the zone of source/drain and channel region and becomes the concave character type shape, utilizes different etching modes to form transistor again.Photoresist layer 112 becomes the position of channel region to have less thickness h 1 in preboarding, and the thickness of photoresist layer 112 other parts is h2.The thickness of photoresist layer 112 has two kinds of different thickness in the zone that desire forms source/drain and channel region, and this is whole technology key.Because two kinds of different photoresistance height must be arranged at the same area, photoresistance thickness h 1 all can influence the result of subsequent etch on photoresistance angle (taper angle) and the channel region island shape semiconductor, so both control is very important, but very wayward on actual process.
Therefore, how to continue to reduce the number that mask uses and keep the yield of technology and reduce the problem that becomes a difficulty of photocurrent.
Summary of the invention
In view of this, purpose of the present invention is providing a kind of manufacture method of film transistor matrix substrate, can use four road masks can finish the technology of pixel electrode and driving transistors.
Another object of the present invention is providing a kind of manufacture method of film transistor matrix substrate, can significantly reduce the cost of manufacturing, makes product have more competitive power.
Another purpose of the present invention is providing a kind of manufacture method of film transistor matrix substrate, can effectively avoid the generation of island shape semiconductor photocurrent.
A further object of the present invention is providing a kind of manufacture method of film transistor matrix substrate, can use the ion injection and form ohmic contact layer on the island shape semiconductor surface.
Another again purpose of the present invention is providing a kind of manufacture method of film transistor matrix substrate, can use half mode mask reducing employed mask number, and avoids the difficulty controlled on known photoresist layer thickness and the angle.
According to above-mentioned purpose of the present invention, the preferred embodiments of the present invention propose a kind of manufacture method of film transistor matrix substrate, use four road mask process, can finish the manufacturing of pixel electrode and driving transistors.Four road mask process comprise respectively: at the first road mask process definition grid, follow, in regular turn dielectric layer, semiconductor layer and conductor layer; Then, define island shape semiconductor and signal electrode with the second road mask process.The second road mask process utilization, half mode mask carries out, photoresist layer is carried out exposure imaging and go out different photoresist layer thickness at island shape semiconductor and desire formation signal electrode zone definitions respectively by the distribution of a shadow tone GTG (Halftone Gray Level) exposure dose, wherein, form in desire that the photoresist layer thickness in signal electrode zone is the thickest, the photoresist layer thickness of island shape semiconductor secondly and other zone is photoresistance standard-sized sheet zone.Utilizing after different etching (dry ecthing or wet etching process) finishes the definition of island shape semiconductor and signal electrode, removing the photoresist layer of island shape semiconductor top and expose conductor layer.Because the photoresist layer above signal electrode is thicker, still has the top that certain thickness photoresist layer is positioned at signal electrode.Then, remove conductor layer on the island shape semiconductor with etch process.Wherein, the material of dielectric layer can for example be silicon nitride or silicon oxynitride, and the material of semiconductor layer can for example be polysilicon or amorphous silicon.
Then, deposit insulating protective layer again on all component structure, and on island shape semiconductor, define source/drain electrode contact hole, signal electrode contact hole to expose the surface of island shape semiconductor and signal electrode respectively with the 3rd road mask process.Then, implementing ion injects to form Ohmic contact on the island shape semiconductor surface that exposes.Follow the deposit transparent conductor layer, and define source/drain electrode, pixel electrode, signal electrode (data line) contact mat with the 4th road mask process.
Another preferred embodiment of the present invention proposes a kind of manufacture method of film transistor matrix substrate, uses four road mask process, can finish the manufacturing of pixel electrode and driving transistors.Four road mask process comprise respectively: define grid and signal electrode at the first road mask process, follow, in regular turn dielectric layer and semiconductor layer; Then, define island shape semiconductor with the second road mask process.Wherein, the material of dielectric layer can for example be silicon nitride or silicon oxynitride, and the material of semiconductor layer can for example be polysilicon or amorphous silicon.
Then, deposit insulating protective layer again on all component structure, and on island shape semiconductor, define source/drain electrode contact hole, signal electrode contact hole to expose the surface of island shape semiconductor and signal electrode respectively with the 3rd road mask process.Then, implementing ion injects to form Ohmic contact on the island shape semiconductor surface that exposes.Follow the deposit transparent conductor layer, and define source/drain electrode, pixel electrode, signal electrode (data line) contact mat with the 4th road mask process.
Therefore, the manufacture method of the disclosed film transistor matrix substrate of utilization the present invention has following advantage: (1) can only use four road masks; (2) adopt ion to inject, need not use metal level or metal silicide layer forms ohmic contact layer to form Ohmic contact on the island shape semiconductor surface; (3) though have and use half mode (half-tone) mask to expose and carry out follow-up development step, but can avoid being known in same zonule and form two kinds of different photoresistance height, therefore there is no the known difficulty that needs strict control photoresistance angle and photoresistance sunk area (photoresistance thinner thickness place) photoresistance thickness; (4) the island shape semiconductor island structure of formation transistor array, the assembly island shape semiconductor does not have the destruction of etching process, makes assembly possess good characteristic, also can reduce at halfbody layer film forming thickness, not only can reduce photocurrent and produce the destruction of plasma in the time of also can reducing film forming, lifting subassembly characteristic; (5) utilize nesa coating bridge joint pixel electrode and signal electrode, can be recessed in island shape semiconductor in the gate electrode, make the border of island shape semiconductor not exceed the border of this grid structure, utilize the gate blocks backlight, the photocurrent that reduces behind the irradiation produces.(6) can reduce manufacturing cost.
Description of drawings
For above and other objects of the present invention, feature, advantage and embodiment can be become apparent, being described in detail as follows of accompanying drawing:
Fig. 1 illustrates the formed film transistor matrix substrate diagrammatic cross-section of traditional four road mask process;
Fig. 2 illustrates the diagrammatic cross-section of the committed step of reduction use mask count in the processes well known;
Fig. 3 illustrates transistor array substrate part (pixel cell structure) schematic top plan view that forms with four road mask process according to one embodiment of the present invention;
Fig. 4 A to Fig. 4 D is along shown in the I-I ' profile line of Fig. 3, the diagrammatic cross-section of the transistor array substrate manufacturing process that forms with four road mask process;
Fig. 5 illustrates transistor array substrate part (pixel cell structure) schematic top plan view that forms with four road mask process according to one embodiment of the present invention; And
Fig. 6 A to Fig. 6 C is along shown in the II-II ' profile line of Fig. 5, the diagrammatic cross-section of the transistor array substrate manufacturing process that forms with four road mask process.
[primary clustering symbol description]
10: gate line (sweep trace); 20: signal wire or signal electrode (data line);
30: gate electrode; 40: pixel electrode; 50: island shape semiconductor;
60,70: source/drain electrode; 100: glass substrate;
104,204,304: dielectric layer; 106,206,206a, 206b: semiconductor layer;
108: ohmic contact layer; 110: electrode layer;
112,210,210a: photoresist layer; 114,212,310: insulating protective layer;
116: backlight; 200,300: transparency carrier; 208,208a, 208b: conductor layer;
214,314: ion injects; 216,312: the Ohmic contact zone;
218,316: transparent conductor layer;
Embodiment
Please refer to Fig. 3, Fig. 3 illustrates transistor array substrate part (pixel cell structure) schematic top plan view that forms with four road mask process according to the preferred embodiment of the present invention.Transistor array substrate comprises gate line (sweep trace) 10, signal wire or signal electrode (data line) 20, gate electrode 30, pixel electrode 40, island shape semiconductor 50 and source/ drain electrode 60 and 70.
Please refer to Fig. 4 A to Fig. 4 D, Fig. 4 A to Fig. 4 D is along shown in the I-I ' profile line of Fig. 3, the diagrammatic cross-section of the transistor array substrate manufacturing process that forms with four road mask process.Please refer to Fig. 4 A, on transparency carrier 200, form gate electrode 30 and gate line (sweep trace) (not illustrating) with one mask process definition conductor layer.Transparency carrier 200 can for example be a glass substrate; The material of conductor layer can for example be the group that aluminium, molybdenum, copper, chromium and the formed alloy of combination in any thereof and metal nitride are formed.Conductor layer can be the formed single or multiple lift structure of previous materials.Then, deposit gate dielectric 204, semiconductor layer 206 and conductor layer 208 in regular turn above transparency carrier 200 and gate electrode 30, wherein the material of gate dielectric 208 can for example be silicon nitride, silicon oxynitride or monox; The material of semiconductor layer 206 can for example be amorphous silicon or polysilicon.And the group that the material that forms conductor layer 208 can for example be formed for aluminium, molybdenum, copper, chromium and the formed alloy of combination in any, metal nitride and metal silicide.
Please continue A, above conductor layer 208, form the photoresist layer 210 that develops with half mode mask exposure referring to Fig. 4.Be positioned at the thinner thickness of the photoresist layer above the gate electrode 30 210 desire form signal electrode above the thickness of photoresist layer 210 thicker.
Please follow B with reference to Fig. 4, utilization dry ecthing or wet etching process remove among Fig. 4 A not the conductor layer 208 that covered for photoresist layer 210 and semiconductor layer 206 and stay semiconductor layer 206a, 206b shown in Fig. 4 B and conductor layer 208a, 208b to finish the definition of island shape semiconductor and signal electrode (data line) and pixel region (pixel area) (not illustrating).Whole etch process can change the composition of etchant according to the variation of required etching material, for example, can be earlier that etchant removes the conductor layer that comes out among Fig. 4 A 208 and is that etchant removes semiconductor layer 206 with SF6/O2 in the present embodiment with SF6/Cl2.
Please continue the B referring to Fig. 4, for example O2 is that etchant removes the part photoresist layer 210 among Fig. 4 A.Since photoresist layer 210 thinner thicknesses of the top of gate electrode 30, and photoresist layer 210 thickness of the top of conductor layer 208b are thicker, therefore, the photoresist layer 210 of the top of gate electrode 30 is removed fully, and the top of conductor layer 208b still can have photoresist layer 210a.Then, serve as cover curtain with light resistance structure 210a, be etchant removes conductor layer 208a among Fig. 4 B and forms island shape semiconductor 50 among Fig. 3 with SF6/Cl2.Then, remove photoresist layer 210a.Signal wire in semiconductor layer 206b and the conductor layer 208b pie graph 3 or signal electrode (data line) 20.
Shown in Fig. 4 C, form insulating protective layer 212 cover gate dielectric layers 204, island shape semiconductor 50 and signal wire or signal electrode (data line) 20. Form contact hole 220 and 222 with the 3rd road mask process lithography insulating protective layer 212 at the insulating protective layer on the island shape semiconductor 50 and on the signal electrode (data line) 20 212. Contact hole 220 and 222 exposes the part upper surface of island shape semiconductor 50 and signal electrode (data line) 20 respectively.The upper surface of the island shape semiconductor 50 that carries out ion implantation technology 214 afterwards and exposed at contact hole 220 forms Ohmic contact zone 216.
Shown in Fig. 4 D, form conformal transparent conductor layer 218 on the structure of transparency carrier 200 tops, and insert contact hole 220 and 222.The material of transparent conductor layer 218 can for example be indium tin oxide, indium-zinc oxide, aluminium zinc oxide, indium oxide or tin oxide.With the 4th road mask process transparent conductor layer 218 is carried out little shadow and etch process defining source/drain electrode shown in Figure 3 60 and 70 and pixel electrode 40, and finish pixel cell structure shown in Figure 3.
Please refer to Fig. 5, Fig. 5 illustrates transistor array substrate part (pixel cell structure) schematic top plan view that forms with four road mask process according to another preferred embodiment of the present invention.Transistor array substrate comprises gate line (sweep trace) 10, signal wire or signal electrode (data line) 20, gate electrode 30, pixel electrode 40, island shape semiconductor 50 and source/drain electrode 60 and 70.Signal wire or signal electrode (data line) 20 is 10 disjunctions of gate line (sweep trace), by being electrically connected in twos by the signal wire of 10 disjunctions of gate line (sweep trace) or signal electrode (data line) 20 through contact hole 308 from the lead 80 that source/drain electrode 70 extended out.
Please refer to Fig. 6 A to Fig. 6 C, Fig. 6 A to Fig. 6 C is along shown in the II-II ' profile line of Fig. 5, the diagrammatic cross-section of the transistor array substrate manufacturing process that forms with four road mask process.Please refer to Fig. 6 A, on transparency carrier 200, form with the first road mask process definition conductor layer gate electrode 30 with gate line (sweep trace) (not illustrating).Transparency carrier 300 can for example be a glass substrate; The material of conductor layer can for example be the group that aluminium, molybdenum, copper, chromium and the formed alloy of combination in any thereof and metal nitride are formed.Conductor layer can be the formed single or multiple lift structure of previous materials.Then, deposit gate dielectric 304 and semiconductor layer (not illustrating) in regular turn in transparency carrier 300, gate electrode 30 and signal electrode (data line) 20 tops, wherein the material of gate dielectric 304 can for example be silicon nitride, silicon oxynitride or monox; The material of semiconductor layer can for example be amorphous silicon or polysilicon.Please continue A, form island shape semiconductor 50 with the second road mask process definition semiconductor layer referring to Fig. 6.
B be please follow, insulating protective layer 310 cover gate dielectric layers 304, island shape semiconductor 50 formed with reference to Fig. 6.Form contact holes 306 and formation contact hole 308 in the insulating protective layer 310 of signal electrode (data line) 20 tops and gate dielectric 304 with the insulating protective layer 310 of the insulating protective layer 310 of mask process lithography island shape semiconductor 50 tops, the 3rd road and signal electrode (data line) 20 tops and gate dielectric 304 at the insulating protective layer on the island shape semiconductor 50 310.Contact hole overlap joint hole 306 and 308 exposes the upper surface of island shape semiconductor 50 and signal electrode (data line) 20 respectively.
Then, carry out ion implantation technology 314 and the upper surface of the island shape semiconductor 50 that exposed at contact hole 306 forms Ohmic contact zone 312.
Shown in Fig. 6 C, form conformal transparent conductor layer 316 on the structure of transparency carrier 200 tops and insert contact hole 306 and 308.The material of transparent conductor layer 316 can for example be indium tin oxide, indium-zinc oxide, aluminium zinc oxide, indium oxide or tin oxide.With the 4th road mask process transparent conductor layer 316 is carried out little shadow and etch process to define source/drain electrode shown in Figure 5 60 and 70 and pixel electrode 40 and finish pixel cell structure shown in Figure 5.
By the invention described above preferred embodiment as can be known, using the disclosed manufacture method of the present invention uses four road masks can finish the technology of pixel electrode and driving transistors.Compared to processes well known, and make in utilization half mode mask according to embodiment, still can avoid the difficulty controlled on known photoresist layer thickness and the angle, thereby can make island shape semiconductor can be entirely gate electrode to cover, and avoid under backlight illumination, producing photocurrent.The island shape semiconductor surface forms Ohmic contact and adopts the mode of ion injection to implement.Therefore, use the manufacture method of the disclosed film transistor matrix substrate of the present invention, can reach the purpose that subtracts mask number, lifting subassembly characteristic and reduce manufacturing cost of the technology that contracts really.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those of ordinary skill in the art, without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (13)
1. method for fabricating thin film transistor is applicable to that on the technology of display panels, this method comprises:
Transparent base is provided;
Form first conductor layer on this transparent base;
This first conductor layer of patterning is to form conductor layer No.1 and grid structure, and wherein this grid structure is electrically connected with this conductor layer No.1;
Deposit first dielectric layer, semiconductor layer and second conductor layer in regular turn and cover this transparent base and this conductor layer No.1 and this grid structure;
This semiconductor layer of etching and this second conductor layer are to form island shape semiconductor and forming semiconductor/conductor second conductor layer of layer again on first dielectric layer above this grid structure;
Forming second dielectric layer covers on this transparent base;
This second dielectric layer of patterning exposes this island shape semiconductor of part and this second conductor layer of part respectively to form contact hole at formation source/drain electrode contact hole on this island shape semiconductor and on this second conductor layer;
Forming transparency conducting layer covers this second dielectric layer and inserts this source/drain electrode contact hole and this contact hole; And
This transparency conducting layer of patterning is with the source of defining/drain electrode and pixel electrode, and wherein one of this source/drain electrode is electrically connected with this pixel electrode and another of this source/drain electrode is electrically connected with this second conductor layer.
2. method for fabricating thin film transistor as claimed in claim 1, wherein this first conductor layer and this second conductor layer can be the single or multiple lift structure.
3. method for fabricating thin film transistor as claimed in claim 1, wherein this etch process comprises:
Form photoresist layer on this second conductor layer;
By the distribution of shadow tone GTG exposure dose this photoresist layer is carried out exposure imaging, to form the patterning photoresist layer on this grid structure and on this second conductor layer zone of predetermined formation.
4. method for fabricating thin film transistor as claimed in claim 3, the predetermined thickness that forms this photoresist layer on this second conductor layer zone of this photoresist layer thickness that wherein is positioned on this grid structure is thin.
5. method for fabricating thin film transistor as claimed in claim 4, wherein this etch process comprises:
First etch process removes this second conductor layer and this semiconductor layer that come out;
Remove this photoresist layer that is positioned on this grid structure; And
Second etch process removes this second conductor layer on this grid structure.
6. method for fabricating thin film transistor as claimed in claim 1, wherein island shape semiconductor is recessed in the grid structure.
7. method for fabricating thin film transistor as claimed in claim 1 wherein after the step of this second dielectric layer of patterning, comprises that also this island shape semiconductor to exposing carries out plasma doping technology.
8. method for fabricating thin film transistor is applicable to that on the technology of display panels, this method comprises:
Transparent base is provided;
Form first conductor layer on this transparent base;
This first conductor layer of patterning is to form conductor layer No.1, second conductor layer and at least one grid structure, and wherein this grid structure is electrically connected with this conductor layer No.1;
Deposit first dielectric layer and semiconductor layer in regular turn and cover this transparent base and this conductor layer No.1, this second conductor layer and this grid structure;
This semiconductor layer of etching is to form island shape semiconductor above this grid structure;
Form second dielectric layer and cover this first dielectric layer and this island shape semiconductor;
This second dielectric layer of patterning and this first dielectric layer expose this island shape semiconductor of part and this second conductor layer of part respectively to form contact hole at formation source/drain electrode contact hole on this island shape semiconductor and on this second conductor layer;
Forming transparency conducting layer covers this second dielectric layer and inserts this source/drain electrode contact hole and this contact hole; And
This transparency conducting layer of patterning is with the source of defining/drain electrode and pixel electrode, and wherein one of this source/drain electrode is electrically connected with this pixel electrode and another of this source/drain electrode is electrically connected with this second conductor layer.
9. method for fabricating thin film transistor as claimed in claim 8, wherein this first conductor layer of patterning also optionally forms capacitor lower electrode.
10. method for fabricating thin film transistor as claimed in claim 9, wherein this pixel electrode of part and this capacitor lower electrode are overlapping to form storage capacitors.
11. method for fabricating thin film transistor as claimed in claim 8, wherein this first conductor layer can be the single or multiple lift structure.
12. method for fabricating thin film transistor as claimed in claim 8, wherein form the step of transparency conducting layer before, comprise that also this island shape semiconductor to exposing carries out plasma doping technology.
13. method for fabricating thin film transistor as claimed in claim 8, wherein island shape semiconductor is recessed in the grid structure.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101375142A CN100444007C (en) | 2005-12-29 | 2005-12-29 | Manufacturing method of film transistor matrix substrate |
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| CNB2005101375142A CN100444007C (en) | 2005-12-29 | 2005-12-29 | Manufacturing method of film transistor matrix substrate |
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| CN1794074A true CN1794074A (en) | 2006-06-28 |
| CN100444007C CN100444007C (en) | 2008-12-17 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102074504A (en) * | 2010-11-27 | 2011-05-25 | 上海大学 | Method for manufacturing self-alignment thin film transistor (TFT) active matrix |
| CN102681274A (en) * | 2011-09-29 | 2012-09-19 | 京东方科技集团股份有限公司 | Liquid crystal display array substrate and manufacturing method thereof |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW413949B (en) * | 1998-12-12 | 2000-12-01 | Samsung Electronics Co Ltd | Thin film transistor array panels for liquid crystal displays and methods of manufacturing the same |
| CN1225719C (en) * | 1999-09-08 | 2005-11-02 | 松下电器产业株式会社 | Electric circuit board, TFT array substrate using same, and liquid crystal display |
| CN1151406C (en) * | 2000-11-03 | 2004-05-26 | 友达光电股份有限公司 | Thin-film transistor LCD and its making method |
| KR100789090B1 (en) * | 2002-12-30 | 2007-12-26 | 엘지.필립스 엘시디 주식회사 | Method for manufacturing lcd |
| CN1304896C (en) * | 2003-04-29 | 2007-03-14 | 友达光电股份有限公司 | Fabrication method of thin film transistor liquid crystal display panel |
| JP2005108912A (en) * | 2003-09-29 | 2005-04-21 | Quanta Display Japan Inc | Liquid crystal display and its manufacturing method |
| US7391483B2 (en) * | 2003-11-27 | 2008-06-24 | Quanta Display Japan Inc. | Liquid crystal display device and manufacturing method |
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2005
- 2005-12-29 CN CNB2005101375142A patent/CN100444007C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102074504A (en) * | 2010-11-27 | 2011-05-25 | 上海大学 | Method for manufacturing self-alignment thin film transistor (TFT) active matrix |
| CN102074504B (en) * | 2010-11-27 | 2013-03-06 | 上海大学 | Method for manufacturing self-alignment thin film transistor (TFT) active matrix |
| CN102681274A (en) * | 2011-09-29 | 2012-09-19 | 京东方科技集团股份有限公司 | Liquid crystal display array substrate and manufacturing method thereof |
| CN102681274B (en) * | 2011-09-29 | 2015-04-01 | 京东方科技集团股份有限公司 | Liquid crystal display array substrate and manufacturing method thereof |
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| CN100444007C (en) | 2008-12-17 |
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