CN101840121A - Array substrate and manufacturing method thereof - Google Patents
Array substrate and manufacturing method thereof Download PDFInfo
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- CN101840121A CN101840121A CN200910080542A CN200910080542A CN101840121A CN 101840121 A CN101840121 A CN 101840121A CN 200910080542 A CN200910080542 A CN 200910080542A CN 200910080542 A CN200910080542 A CN 200910080542A CN 101840121 A CN101840121 A CN 101840121A
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Abstract
The invention discloses an array substrate and a manufacturing method thereof, relates to the technical field of liquid crystal displays, and solves the problem of overlarge parasitic capacitance between a data scanning line and a grid scanning line in the prior art and prevention of electrostatic breakdown. In the array substrate of the embodiment of the invention, a gas layer is arranged between a grid electrode and a source/drain electrode of a thin film transistor, and a gas layer positioned between the grid scanning line and the data scanning line is arranged at the intersection of the grid scanning line and the data scanning line. The embodiment of the invention is mainly used for the field of the liquid crystal displays, particularly for the array substrates needing small parasitic capacitance between the data scanning line and the grid scanning line.
Description
Technical field
The present invention relates to the LCD Technology field, relate in particular to array base palte and manufacture method thereof.
Background technology
As depicted in figs. 1 and 2, tft array substrate comprises and is arranged on controlling grid scan line intersected with each other on the infrabasal plate 1 and data scanning line 2, is provided with TFT7, pixel electrode 9 and public electrode wire 16 in each zone that controlling grid scan line 1 and data scanning line 2 intersect to form.The concrete structure of TFT7 is seen the TFT sectional view shown in Fig. 2, this TFT7 comprises the grid 3 that links to each other with controlling grid scan line 1, the source electrode 4 that links to each other with data scanning line 2, the drain electrode 5 that links to each other with pixel electrode 9, wherein draining 5 links to each other with pixel electrode 9 by contact hole 8, and source electrode 4 and drain and be provided with raceway groove 6 between 5.This TFT7 also comprises the semiconductor layer 13 overlapping with grid 3, also is formed with to be used for forming the doping semiconductor layer 14 that electrically contacts with source electrode 4 and drain electrode 5 semiconductor layer 13 and the doping semiconductor layer 14 common semiconductors that form on semiconductor layer 13.On controlling grid scan line 1, apply voltage, make the grid 3 of TFT7 have voltage and make TFT source electrode 4 and drain electrode 5 conductings, the pixel voltage that is applied to like this on the data scanning line 2 just can charge into also maintenance of pixel electrode 8, thereby makes that forming electric field between pixel electrode 9 and the other public electrode simultaneously of liquid crystal controls the transmittance of liquid crystal with display image.
As shown in Figure 2, be formed with grid insulating film 11 on the grid 3 of controlling grid scan line 1, TFT7 and the public electrode wire 16.Preparing source electrode and drain electrode back formation passivation layer 12, contact hole 8 wherein passes this passivation layer 12 and touches drain electrode 5.Tft array substrate and color film glass substrate to box after, in order further to reduce the light leak in the pixel, the both sides that can also be parallel to the data scanning line in each pixel are provided with shading strip, the grid of general shading strip and controlling grid scan line and TFT forms on one deck, only need to change the used mask plate of photoetching, make to have shading strip on the grid layer.
Realizing using in the process of above-mentioned array base palte, the inventor finds that there are the following problems at least: because tft array substrate is provided with a lot of data scanning lines and controlling grid scan line, and data scanning line and controlling grid scan line intersect, in data scanning line and controlling grid scan line infall and film crystal tube grid and source/bigger stray capacitance of drain electrode meeting formation, the signal that causes being input on the data scanning line postpones.
Summary of the invention
Embodiments of the invention provide a kind of array base palte and manufacture method thereof, to reduce to be input to the delay duration of the signal on the data scanning line.
For achieving the above object, embodiments of the invention adopt following technical scheme:
A kind of array base palte, comprise substrate, and the controlling grid scan line that on substrate, forms, data scanning line, pixel electrode and thin film transistor (TFT), the grid of this thin film transistor (TFT) links to each other with controlling grid scan line, source electrode links to each other with the data scanning line, drain electrode links to each other with pixel electrode; Be provided with gas blanket between the grid of described thin film transistor (TFT) and the source/drain electrode; Described controlling grid scan line and data scanning line infall are provided with the gas blanket between controlling grid scan line and data scanning line.
A kind of method of manufacturing array substrate comprises:
(1) form gate pattern on substrate, this gate pattern comprises controlling grid scan line and the grid that links to each other with controlling grid scan line;
(2) deposit grid insulating film having on the substrate of gate pattern;
(3) on grid insulating film, form with the dissolving layer of the gate overlap of thin film transistor (TFT) and with controlling grid scan line and the overlapping dissolving layer of data scanning line infall;
(4) formation source/leakage metallic film on described substrate with dissolving layer;
(5) on described source/leakage metallic film the source of etching/leakage pattern, and will etch away described dissolving layer, this source/leakage pattern comprises the data scanning line that intersects with controlling grid scan line, the source electrode and the drain electrode of thin film transistor (TFT);
(6) formation is connected to the pixel electrode of the drain electrode of thin film transistor (TFT);
(7) form active Thinfilm pattern corresponding to described source/drain electrode, this active Thinfilm pattern comprises the doping semiconductor layer with raceway groove, the semiconductor layer that forms successively.
A kind of method of manufacturing array substrate comprises:
(1) form gate pattern on substrate, this gate pattern comprises controlling grid scan line and the grid that links to each other with controlling grid scan line;
(2) deposit grid insulating film having on the substrate of gate pattern;
(3) the active Thinfilm pattern of the gate overlap of formation and thin film transistor (TFT) on grid insulating film;
(4) form with the overlapping dissolving layer of described active Thinfilm pattern and with controlling grid scan line and the overlapping dissolving layer of data scanning line infall;
(5) formation source/leakage metallic film on described substrate with dissolving layer;
(6) on described source/leakage metallic film the source of etching/leakage pattern, and will etch away described dissolving layer, this source/leakage pattern comprises the data scanning line that intersects with controlling grid scan line, the source electrode and the drain electrode of thin film transistor (TFT);
(7) form the passivation film with contact hole on the substrate of formation source/leakage pattern, this contact hole exposes the drain electrode of thin film transistor (TFT);
(8) form the pixel electrode that is connected to the drain electrode of thin film transistor (TFT) through described contact hole.
Array base palte that the embodiment of the invention provides and manufacture method thereof, owing between the grid of thin film transistor (TFT) and source/drain electrode, be provided with gas blanket, and be provided with gas blanket between controlling grid scan line and data scanning line at controlling grid scan line and data scanning line infall; For the gate insulation layer between the gate insulation layer between grid in the prior art and the source/drain electrode and semiconductor and controlling grid scan line and the data scanning line, the specific inductive capacity of gas blanket is relatively low in the embodiment of the invention, makes that the stray capacitance of grid and source/drain electrode formation of stray capacitance that controlling grid scan line and data scanning line form at infall and thin film transistor (TFT) all can be littler than stray capacitance of the prior art.Because the time of the signal delay on the data scanning line is directly proportional with stray capacitance, so under the situation that stray capacitance reduces, the duration of the signal delay on the data scanning line also will reduce.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the synoptic diagram of array base palte in the prior art;
Fig. 2 is the sectional view of I-I ' among Fig. 1;
Fig. 3 is the synoptic diagram of array base palte in the embodiment of the invention 1;
Fig. 4 is the sectional view of II-II ' among Fig. 3;
Fig. 5 is first process that array base palte is made in the embodiment of the invention 2;
Fig. 6 is second process that array base palte is made in the embodiment of the invention 2;
Fig. 7 is the 3rd process that array base palte is made in the embodiment of the invention 2;
Fig. 8 is the 4th process that array base palte is made in the embodiment of the invention 2;
Fig. 9 is the 5th process that array base palte is made in the embodiment of the invention 2;
Figure 10 is the 6th process that array base palte is made in the embodiment of the invention 2;
Figure 11 is the synoptic diagram of array base palte in the embodiment of the invention 3;
Figure 12 is the sectional view of III-III ' among Figure 11;
Figure 13 is first process that array base palte is made in the embodiment of the invention 4;
Figure 14 is second process that array base palte is made in the embodiment of the invention 4;
Figure 15 is the 3rd process that array base palte is made in the embodiment of the invention 4;
Figure 16 is the 4th process that array base palte is made in the embodiment of the invention 4;
Figure 17 is the 5th process that array base palte is made in the embodiment of the invention 4;
Figure 18 is the 6th process that array base palte is made in the embodiment of the invention 4.
Embodiment
Array base palte in the embodiment of the invention, comprise substrate, and the controlling grid scan line that on substrate, forms, data scanning line, pixel electrode and thin film transistor (TFT), the grid of this thin film transistor (TFT) links to each other with controlling grid scan line, source electrode links to each other with the data scanning line, drain electrode links to each other with pixel electrode.In order to reduce stray capacitance, between the grid of described thin film transistor (TFT) and source/drain electrode, be provided with gas blanket in the embodiment of the invention, and described controlling grid scan line and data scanning line infall are provided with the gas blanket between controlling grid scan line and data scanning line.
Owing to there is above-mentioned gas blanket, make that the grid of stray capacitance that controlling grid scan line and data scanning line in the embodiment of the invention form at infall and thin film transistor (TFT) is all relative less with the stray capacitance of source/drain electrode formation, under the less situation of stray capacitance, the duration of the signal delay on the controlling grid scan line is also shorter, thereby reduces to be input to the delay duration of the signal on the controlling grid scan line.
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that is obtained under the creative work prerequisite.
Embodiment 1:
The embodiment of the invention provides a kind of array base palte, as shown in Figure 3 and Figure 4, this array base palte comprises substrate 270, and the controlling grid scan line 220 of setting intersected with each other on substrate 270 and data scanning line 210, the pixel electrode 230 and the thin film transistor (TFT) 250 that are provided with at each infall of controlling grid scan line 220 and data scanning line 210.The sectional view of this thin film transistor (TFT) 250 and the sectional view of controlling grid scan line 220 and data scanning line 210 infalls have been expressed among Fig. 4.Thin film transistor (TFT) 250 shown in Fig. 4 comprise the grid 251 that links to each other with controlling grid scan line 220, the source electrode 252 that links to each other with data scanning line 210, the drain electrode 253 that links to each other with pixel electrode 230 and and controlling grid scan line 220 overlapping and limit source electrode 252 and the semiconductor layer 257a of the raceway groove 254 between 253 of draining; Also be formed with on semiconductor layer 257a and be used for forming the doping semiconductor layer 257b electrically contact with the data scanning line, semiconductor layer 257a and doping semiconductor layer 257b form semiconductor jointly.
In order to reduce to be input to the delay duration of the signal on the controlling grid scan line 220, array base palte in the embodiment of the invention is provided with gas blanket 256 between the grid 251 of thin film transistor (TFT) 250 and source/ drain electrode 252 and 253, and is provided with gas blanket 260 between controlling grid scan line 220 and data scanning line 210 at controlling grid scan line 220 and data scanning line 210 infalls.
As shown in Figure 4, the hierarchy of above-mentioned controlling grid scan line 220 and data scanning line 210 infalls: controlling grid scan line 220 is formed on the substrate 270, one deck is a gate insulation layer 280 on controlling grid scan line 220, above the gate insulation layer 280 is gas blanket 260, is exactly data scanning line 210 on the gas blanket 260.Generally speaking, at least also need to be provided with passivation layer 290, so that the tft array substrate of making is at last protected at data scanning line 210.
As shown in Figure 4, the hierarchy at above-mentioned thin film transistor (TFT) 250 places is: the grid 251 of thin film transistor (TFT) 250 is formed on the substrate 270, one deck is a gate insulation layer 280 on grid 251, above the gate insulation layer 280 is the active Thinfilm pattern that is formed by semiconductor layer 257a and doping semiconductor layer 257b, and is etched with raceway groove 254 on the doping semiconductor layer 257b; Being exactly gas blanket 256 on active Thinfilm pattern, is exactly source/ drain electrode 252 and 253 on gas blanket 256, and source electrode 252 253 can directly not contact with drain electrode, and source electrode 252 also connects together with above-mentioned data scanning line 210 simultaneously.
In order to protect above-mentioned thin film transistor (TFT) 250, data scanning line 210 and controlling grid scan line 220, the embodiment of the invention also need form the passivation layer 290 with contact hole 255 on the substrate of formation source/drain electrode, this contact hole 255 exposes the drain electrode 253 of above-mentioned thin film transistor (TFT) 250, specifically as shown in Figure 4; Also be formed with pixel electrode 230 in the embodiment of the invention on passivation layer 290, this pixel electrode 230 is connected to the drain electrode 253 of thin film transistor (TFT) 250 by contact hole 255.
Owing between the grid of thin film transistor (TFT) 250 and source/drain electrode, be provided with gas blanket 256, and be provided with gas blanket 260 between controlling grid scan line 220 and data scanning line 210 at controlling grid scan line 220 and data scanning line 210 infalls; For the gate insulation layer between the gate insulation layer between grid in the prior art and the source/drain electrode and semiconductor and controlling grid scan line and the data scanning line, gas blanket 256 and 260 specific inductive capacity are relatively low in the embodiment of the invention, make that the stray capacitance of grid and source/drain electrode formation of stray capacitance that controlling grid scan line and data scanning line form at infall and thin film transistor (TFT) all can be littler than stray capacitance of the prior art.Because the time of the signal delay on the data scanning line is directly proportional with stray capacitance, so under the situation that stray capacitance reduces, the duration of the signal delay on the data scanning line also will reduce.
And since data scanning line and controlling grid scan line at infall across gas blanket 256 and 260, can reduce data scanning line 210 and controlling grid scan line 220 probability so relatively at the infall short circuit.
The gas that is comprised in the gas blanket in the embodiment of the invention can adopt but not be defined as air.
Embodiment 2:
The embodiment of the invention also provides a kind of method of manufacturing array substrate, describes this manufacture method below with reference to Fig. 5 to Figure 10.
At first, as shown in Figure 5, deposition grid metal level on substrate 270.Subsequently, by mask composition technology described grid metal level etching is formed gate pattern, this gate pattern comprises controlling grid scan line 220 and grid 251, wherein, the controlling grid scan line 220 that grid 251 is adjacent be one and connect together.
Utilize deposition technique on substrate 270, to deposit grid insulating film 280 (see figure 6)s with gate pattern.And on grid insulating film 280, form semiconductor layer (material is an amorphous silicon) and doping semiconductor layer (material is the n+ amorphous silicon) successively; Semiconductor layer is wherein seen the 257a among the figure, and doping semiconductor layer is seen the 257b among the figure.
Then, as shown in Figure 6, semiconductor layer 257a and the doping semiconductor layer 257b that is formed on the grid insulating film carried out etching, to form the active Thinfilm pattern overlapping with grid 251 by mask composition technology.
Subsequently, as shown in Figure 7, the soluble material layer of deposition on substrate 270 with active Thinfilm pattern, by mask composition technology this soluble material layer is etched into the dissolving layer 258 overlapping with described active Thinfilm pattern then, and with controlling grid scan line 220 and the overlapping dissolving layer 261 of data scanning line 210 infalls.Dissolving layer 258 and 261 materials that adopted can be A-ITO (noncrystalline tin indium oxide in the present embodiment, Amorphous-Indium Tin Oxide), when practice, can also adopt other than source/fireballing material of leakage metal etch as the dissolving layer material, for example: indium zinc oxide (IZO, Indium Zincum Oxide) or zinc paste are as the material of dissolving layer.
Again subsequently, as shown in Figure 8, formation source/leakage metallic film on the substrate 270 that comprises active Thinfilm pattern and dissolving layer.Afterwards, by the mask composition technology source of etching/leakage pattern and etch away described dissolving layer, this source/leakage pattern comprises the source electrode 252 of the data scanning line 210 that intersects with controlling grid scan line 220, thin film transistor (TFT) 250 and drains 253; And the source electrode 252 of thin film transistor (TFT) 250 links to each other with data scanning line 210.
In general, when carrying out source/leakage pattern etch, because the rate of dissolution of the materials A-ITO of dissolving layer 258 and 261 is very fast, like this can be when carrying out source/leakage pattern etch, the A-ITO of all dissolving layers is etched away, so between the grid of thin film transistor (TFT) 250 and source/drain electrode, have gas blanket 256.Simultaneously, because controlling grid scan line 220 and data scanning line 210 infalls also have dissolving layer 261, in etching source/leakage pattern, also can between controlling grid scan line 220 and data scanning line 210, form gas blanket 260 so.And can be in the gas blanket 256 and 261 in the embodiment of the invention including but not limited to air.
Then, as shown in Figure 9, utilize deposition technique deposit passivation layer 290 on substrate shown in Figure 8, and utilize mask composition technology to etch a plurality of contact holes 255 on passivation layer 290, these contact holes 255 can expose the drain electrode 253 of thin film transistor (TFT) 250.
Again then, as shown in figure 10, deposition layer of transparent electrode material on passivation layer 290 with contact hole 255, and utilize mask composition technology to etch transparent electrode pattern, this transparent electrode pattern comprises the pixel electrode 230 that is connected to the drain electrode 253 of thin film transistor (TFT) 250 through contact hole 255.The material that forms pixel electrode 230 in the present embodiment can be A-ITO, also can be P-ITO (polycrystalline tin indium oxide, Polycrystal-Indium Tin Oxide).
The array base palte that the embodiment of the invention produces, between the grid of thin film transistor (TFT) 250 and source/drain electrode, have gas blanket 256, have gas blanket 260 between controlling grid scan line 220 and data scanning line 210 at controlling grid scan line 220 and data scanning line 210 infalls.Because gas blanket 256 and 260 specific inductive capacity are relatively low, make that the stray capacitance of grid and source/drain electrode formation of stray capacitance that controlling grid scan line and data scanning line form at infall and thin film transistor (TFT) all can be littler than stray capacitance of the prior art.Under the situation that stray capacitance reduces, the duration of the signal delay on the data scanning line also will reduce.
And since data scanning line 210 and controlling grid scan line 220 at infall across gas blanket 260, can reduce data scanning line 210 and controlling grid scan line 220 probability so relatively at the infall short circuit.And when preparation data scanning line 210, gas blanket 260 is still substituted by dissolving layer 261, even there is static in a small amount on the data scanning line 210, also can separate by dissolved layer 261, reduce electrostatic breakdown data scanning line 210 and controlling grid scan line 220 and the probability of short circuit.
Embodiment 3:
The embodiment of the invention provides a kind of array base palte, as Figure 11 and shown in Figure 12, this array base palte comprises substrate 370, and the controlling grid scan line 320 of setting intersected with each other on substrate 370 and data scanning line 310, the pixel electrode 330 and the thin film transistor (TFT) 350 that are provided with at each infall of controlling grid scan line 320 and data scanning line 310.Expression is except the sectional view of this thin film transistor (TFT) 350 and the sectional view of controlling grid scan line 320 and data scanning line 310 infalls among Figure 12.Thin film transistor (TFT) 350 shown in Figure 12 comprise the grid 351 that links to each other with controlling grid scan line 320, the source electrode 352 that links to each other with data scanning line 310, the drain electrode 353 that links to each other with pixel electrode 330 and and controlling grid scan line 320 overlapping and limit source electrode 352 and the semiconductor layer 356a of the raceway groove 354 between 353 of draining; On semiconductor layer 356a, also be formed with and be used for forming the doping semiconductor layer 356b that electrically contacts, semiconductor layer 356a and mix and partly lead 356b body layer and form semiconductor jointly with data scanning line 310.
In order to reduce to be input to the delay duration of the signal on the controlling grid scan line 320, array base palte in the embodiment of the invention is provided with gas blanket 357 between the grid of film crystal 350 pipes and source/drain electrode, and is provided with gas blanket 340 between controlling grid scan line 320 and data scanning line 310 at controlling grid scan line 320 and data scanning line 310 infalls.
As shown in figure 12, the hierarchy of above-mentioned controlling grid scan line 320 and data scanning line 310 infalls: controlling grid scan line 320 is formed on the substrate 370, one deck is a gate insulation layer 380 on controlling grid scan line 320, above the gate insulation layer 380 is gas blanket 340, is exactly data scanning line 310 on the gas blanket 340.Generally speaking, at least also need to be provided with passivation layer 390, so that the tft array substrate of making is at last protected at data scanning line 310.
As shown in figure 12, the hierarchy at above-mentioned thin film transistor (TFT) 350 places is: the grid 351 of thin film transistor (TFT) 350 is formed on the substrate 370, and one deck is a gate insulation layer 380 on grid 351, is exactly gas blanket 357 on gate insulation layer 380; Form active/ drain electrode 352 and 353 on gas blanket 357, and source electrode 352 and drain electrode 353 can not contact directly, while source electrode 352 also connects together with above-mentioned data scanning line 310.For other parts that do not form source/drain electrode, on gate insulation layer 380, be formed with the pixel electrode 330 of the drain electrode 353 that is connected to thin film transistor (TFT) 350; And the part of/drain electrode active for forming then is formed with doping semiconductor layer 356b and semiconductor layer 356a successively, and has raceway groove 354 on the doping semiconductor layer 356b.
As shown in figure 12, in order to protect above-mentioned thin film transistor (TFT) 350, data scanning line 310, controlling grid scan line 320 and pixel electrode 330, the embodiment of the invention also need form passivation layer 390 on substrate 370.
Owing between the grid of thin film transistor (TFT) and source/drain electrode, be provided with gas blanket 357, and be provided with gas blanket 340 between controlling grid scan line 320 and data scanning line 310 at controlling grid scan line 320 and data scanning line 310 infalls; For the gate insulation layer between the gate insulation layer between grid in the prior art and the source/drain electrode and semiconductor and controlling grid scan line and the data scanning line, the specific inductive capacity of gas blanket is relatively low in the embodiment of the invention, makes that the stray capacitance of grid and source/drain electrode formation of stray capacitance that controlling grid scan line and data scanning line form at infall and thin film transistor (TFT) all can be littler than stray capacitance of the prior art.Because the time of the signal delay on the data scanning line is directly proportional with stray capacitance, so under the situation that stray capacitance reduces, the duration of the signal delay on the data scanning line also will reduce.
And since data scanning line 310 and controlling grid scan line 320 at infall across gas blanket 340, can reduce data scanning line 310 and controlling grid scan line 320 probability so relatively at the infall short circuit.
Simultaneously, because the pixel electrode 330 in the embodiment of the invention is made below passivation layer 390, and directly be connected with the drain electrode 353 of thin film transistor (TFT) 350, the process of the making contact hole that saves, and not having can increase the useful area of pixel electricity 330 utmost points as memory capacitance behind the contact hole, can increase the capacity of memory capacitance.
The gas that is comprised in the gas blanket in the embodiment of the invention can adopt but not be defined as air.
Embodiment 4:
The embodiment of the invention also provides a kind of method of manufacturing array substrate, describes this manufacture method below with reference to Figure 13 to Figure 18.
At first, as shown in figure 13, deposition grid metal level on substrate 370.Subsequently, by mask composition technology described grid metal level etching is formed gate pattern, this gate pattern comprises controlling grid scan line 320 and grid 351, wherein, the controlling grid scan line 320 that grid 351 is adjacent be one and connect together.
Utilize deposition technique on substrate 370, to deposit grid insulating film 380 (seeing Figure 14) with gate pattern.Then, as shown in figure 14, the soluble material layer of deposition on substrate 370 with grid insulating film 380, will this soluble material layer be etched into the dissolving layer 358 overlapping by mask composition technology then with the grid 351 of described thin film transistor (TFT) 350, and with controlling grid scan line 320 and the overlapping dissolving layer 341 of data scanning line 310 infalls.In the present embodiment dissolving layer 358 and 341 materials that adopted can but be not defined as A-ITO or silicon dioxide.
Again subsequently, as shown in figure 15, formation source/leakage metallic film on the substrate that comprises dissolving layer 358 and 341.Afterwards, by the mask composition technology source of etching/leakage pattern, and will etch away described dissolving layer, this source/leakage pattern comprises the source electrode 352 of the data scanning line 310 that intersects with controlling grid scan line 320, thin film transistor (TFT) 350 and drains 353; And the source electrode 352 of thin film transistor (TFT) 350 links to each other with data scanning line 310.
In general, when carrying out source/leakage pattern etch, because the rate of dissolution of the materials A-ITO of dissolving layer 358 and 341 is very fast, like this can be when carrying out source/leakage pattern etch, the A-ITO of all dissolving layers is etched away, so between the grid of thin film transistor (TFT) 250 and source/drain electrode, have gas blanket 257.Simultaneously, because controlling grid scan line 320 and data scanning line 310 infalls also have dissolving layer 341, in etching source/leakage pattern, also can between controlling grid scan line 320 and data scanning line 310, form gas blanket 340 so.And can be in the gas blanket 357 and 340 in the embodiment of the invention including but not limited to air.
Certainly,, then can dissolving layer be etched away, so that form above-mentioned gas blanket by akaline liquid if the material of dissolving layer 358 and 341 is a silicon dioxide.When practice, can also leak the material of the fast other materials of metal than source/leakage metal than the source by other etching speeds, for example: silicon nitride, IZO or zinc paste etc. as dissolving layer.
Then, as shown in figure 16, have source/leakage pattern and etching away deposition layer of transparent electrode material on the substrate 370 of dissolving layer, and utilize mask composition technology to etch transparency electrode 330 patterns, this transparent electrode pattern comprises directly and thin film transistor (TFT) 350 drain electrodes 353 pixel electrodes that directly link to each other 330, the material that forms pixel electrode 330 in the present embodiment can be A-ITO, also can be P-ITO.
Again then, as shown in figure 17, form active Thinfilm pattern by mask composition technology in described source/drain electrode, this active Thinfilm pattern comprises doping semiconductor layer with raceway groove (material is the n+ amorphous silicon) and the semiconductor layer (material is an amorphous silicon) that forms successively; Semiconductor layer is wherein seen the 356a among the figure, and doping semiconductor layer is seen the 356b among the figure.
In order to protect above-mentioned thin film transistor (TFT) 350, data scanning line 310, controlling grid scan line 320 and pixel electrode 330, as shown in figure 18, the embodiment of the invention forms passivation layer 390 on the substrate 370 with active Thinfilm pattern and pixel electrode 330.
The array base palte that the embodiment of the invention produces, between the grid of thin film transistor (TFT) 350 and source/drain electrode, have gas blanket 357, have gas blanket 340 between controlling grid scan line 320 and data scanning line 310 at controlling grid scan line 320 and data scanning line 310 infalls.Because gas blanket 357 and 340 specific inductive capacity are relatively low, make that the stray capacitance of grid and source/drain electrode formation of stray capacitance that controlling grid scan line and data scanning line form at infall and thin film transistor (TFT) all can be littler than stray capacitance of the prior art.Under the situation that stray capacitance reduces, the duration of the signal delay on the data scanning line also will reduce.
And since data scanning line 310 and controlling grid scan line 320 at infall across gas blanket 340, can reduce data scanning line 310 and controlling grid scan line 320 probability so relatively at the infall short circuit.And when preparation data scanning line 310, gas blanket 340 is still substituted by dissolving layer 341, even there is static in a small amount on the data scanning line 310, also can separate by dissolved layer 341, reduce electrostatic breakdown data scanning line 310 and controlling grid scan line 320 and the probability of short circuit.
Simultaneously, because the pixel electrode 330 in the embodiment of the invention is made below passivation layer 390, and directly be connected with the drain electrode 353 of thin film transistor (TFT) 350, the process of the making contact hole that saves, and not having can increase the useful area of pixel electrode 330 as memory capacitance behind the contact hole, can increase the capacity of memory capacitance.
The embodiment of the invention mainly is used in field of liquid crystal, is used in especially on the array base palte that needs stray capacitance between less data scanning line and the controlling grid scan line.
The above; only be the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion by described protection domain with claim.
Claims (9)
1. array base palte, comprise substrate, and the controlling grid scan line that on substrate, forms, data scanning line, pixel electrode and thin film transistor (TFT), the grid of this thin film transistor (TFT) links to each other with controlling grid scan line, source electrode links to each other with the data scanning line, drain electrode links to each other with pixel electrode; It is characterized in that, be provided with gas blanket between the grid of described thin film transistor (TFT) and the source/drain electrode; Described controlling grid scan line and data scanning line infall are provided with the gas blanket between controlling grid scan line and data scanning line.
2. array base palte according to claim 1 is characterized in that, described controlling grid scan line and data scanning line infall comprise to the data scanning line successively from controlling grid scan line: gate insulation layer and gas blanket.
3. array base palte according to claim 1 and 2 is characterized in that, described thin film transistor (TFT) from the grid to the source/drain electrode between comprise successively: gate insulation layer, semiconductor layer, doping semiconductor layer and gas blanket.
4. array base palte according to claim 1 and 2 is characterized in that, described thin film transistor (TFT) from the grid to the source/drain electrode between comprise successively: gate insulation layer and gas blanket; Be formed with the pixel electrode of the drain electrode that is connected to thin film transistor (TFT) on the described gate insulation layer; Comprise successively in the source/drain electrode of described thin film transistor (TFT): doping semiconductor layer, semiconductor layer with raceway groove.
5. the method for a manufacturing array substrate is characterized in that, comprising:
(1) form gate pattern on substrate, this gate pattern comprises controlling grid scan line and the grid that links to each other with controlling grid scan line;
(2) deposit grid insulating film having on the substrate of gate pattern;
(3) the active Thinfilm pattern of the gate overlap of formation and thin film transistor (TFT) on grid insulating film;
(4) form with the overlapping dissolving layer of described active Thinfilm pattern and with controlling grid scan line and the overlapping dissolving layer of data scanning line infall;
(5) formation source/leakage metallic film on described substrate with dissolving layer;
(6) source of etching/leakage pattern and etch away described dissolving layer on described source/leakage metallic film, this source/leakage pattern comprises the data scanning line that intersects with controlling grid scan line, the source electrode and the drain electrode of thin film transistor (TFT);
(7) form the passivation film with contact hole on the substrate of formation source/leakage pattern, this contact hole exposes the drain electrode of thin film transistor (TFT);
(8) form the pixel electrode that is connected to the drain electrode of thin film transistor (TFT) through described contact hole.
6. the method for manufacturing array substrate according to claim 5 is characterized in that, described dissolving layer material therefor is noncrystalline tin indium oxide, indium zinc oxide or zinc paste.
7. the method for a manufacturing array substrate is characterized in that, comprising:
(1) form gate pattern on substrate, this gate pattern comprises controlling grid scan line and the grid that links to each other with controlling grid scan line;
(2) deposit grid insulating film having on the substrate of gate pattern;
(3) on grid insulating film, form with the dissolving layer of the gate overlap of thin film transistor (TFT) and with controlling grid scan line and the overlapping dissolving layer of data scanning line infall;
(4) formation source/leakage metallic film on described substrate with dissolving layer;
(5) source of etching/leakage pattern and etch away described dissolving layer on described source/leakage metallic film, this source/leakage pattern comprises the data scanning line that intersects with controlling grid scan line, the source electrode and the drain electrode of thin film transistor (TFT);
(6) formation is connected to the pixel electrode of the drain electrode of thin film transistor (TFT);
(7) form active Thinfilm pattern corresponding to described source/drain electrode, this active Thinfilm pattern comprises the doping semiconductor layer with raceway groove, the semiconductor layer that forms successively.
8. the method for manufacturing array substrate according to claim 7 is characterized in that, in (7) afterwards, this method also comprises:
(8) on substrate, form passivation layer with active Thinfilm pattern and pixel electrode.
9. the method for manufacturing array substrate according to claim 7 is characterized in that, described dissolving layer material therefor is silicon dioxide, silicon nitride, noncrystalline tin indium oxide, indium zinc oxide or zinc paste.
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| CN2009100805423A CN101840121B (en) | 2009-03-20 | 2009-03-20 | Array substrate and manufacturing method thereof |
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| CN2009100805423A CN101840121B (en) | 2009-03-20 | 2009-03-20 | Array substrate and manufacturing method thereof |
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| CN101840121B CN101840121B (en) | 2012-05-23 |
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| CN102479682A (en) * | 2010-11-30 | 2012-05-30 | 京东方科技集团股份有限公司 | Method of lift off and manufacturing method of TFT array substrate |
| CN102681274A (en) * | 2011-09-29 | 2012-09-19 | 京东方科技集团股份有限公司 | Liquid crystal display array substrate and manufacturing method thereof |
| CN104317089A (en) * | 2014-10-27 | 2015-01-28 | 合肥鑫晟光电科技有限公司 | Array substrate, production method thereof, display panel and display device |
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| KR100765135B1 (en) * | 2001-09-07 | 2007-10-15 | 삼성전자주식회사 | Liquid crystal display device and method for fabricating thereof |
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| CN113871439A (en) * | 2021-09-24 | 2021-12-31 | 深圳市华星光电半导体显示技术有限公司 | Manufacturing method of quantum dot substrate and quantum dot substrate |
| CN113871555A (en) * | 2021-09-26 | 2021-12-31 | 深圳市华星光电半导体显示技术有限公司 | Manufacturing method of quantum dot substrate and quantum dot substrate |
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