CN102664625A - Programmable ECL (emitter coupled logic) device based high-frequency phase shift signal generation circuit - Google Patents
Programmable ECL (emitter coupled logic) device based high-frequency phase shift signal generation circuit Download PDFInfo
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Abstract
The invention discloses a kind of high-frequency phase shift signal generating circuits based on programmable ECL logical device. Existing HF signal generator is expensive and hardware circuit is complicated. The present invention includes quick comparator, PLL frequency multiplier, ECL signal clock distributor, pulse suppressor, the first digital frequency divider and the second digital frequency divider. External timing signal is converted square-wave signal by quick comparator, PLL may be programmed frequency multiplier for the square wave signal frequency multiplication, ECL signal clock distributor distributes the frequency-doubled signal to two-way, frequency-doubled signal is directly divided via the first digital frequency divider all the way, by being divided after the phase shift of one 2 π of pulse suppressor inhibition by the second digital frequency divider, the frequency dividing multiple of the first digital frequency divider and the second digital frequency divider is another way frequency-doubled signal
, the output signal of the first digital frequency divider has with respect to the output signal of the second digital frequency divider
Phase shift. Circuit design principle of the present invention is simple, and reproducibility is strong.
Description
Technical field
The present invention relates to a kind of high frequency phase shift signalling generation circuit, be specifically related to a kind of high frequency phase shift signalling generation circuit based on ECL logical device able to programme.
Background technology
Along with development of electronic technology; The high frequency phase shift signalling in the application of precision engineering, electronics, biomedicine, communication science research more and more widely; Existing common HF signal generator often shows as jitter; Or precision is not high, and costing an arm and a leg of high-performance high-frequency signal generator is not optimal selection for the general user.
Traditional phase shift signalling generation circuit adopts phase-locked loop and counter to constitute address generator in the data realization of going down of different pieces of information memory; Realize the phase shift of signal through the memory location that changes data; This method output flexibly; But because the restriction of phase-lock-ring output frequency is suitable for the low frequency signal application below the 1MHz, and the easy circuit structure out of hand and relative complex of the pith counter of formation phase-locked loop makes the reliability of entire circuit be difficult to guarantee.The HF signal generator based on Direct Digital frequency synthesis DDS technology of development in recent years can be realized the phase shift signalling output of frequency more than 40MHz, and phase shift resolution can reach 0.01 °, but this series products does not all provide phase shift unsteadiness index.In addition, such HF signal generator is external product monopolization, cost an arm and a leg, and hardware circuit is complicated, and volume is bigger, and is not portable.Therefore portable, high stable, low signal-to-noise ratio of independent development, high frequency phase shift signalling generator has the important techniques innovative value cheaply.
The notification number of Chinese invention patent bulletin is that the patent of CN102055428A has been announced a kind of digital phase shifter, and the frequency domain of this type of phase shifter is wide, can be 6～18GHz, and manufacturing process is easy, and rate of finished products is high, and the phase shift precision is high, but the phase shift step value is confined to 11.25 °.The notification number of Chinese invention patent bulletin is that the patent of CN101355350A has been announced a kind of phase-shift circuit, and such phase-shift circuit has the characteristic that low intrinsic postpones, not mentioned frequency domain scope in can announcing.
Summary of the invention
The object of the present invention is to provide that a kind of circuit topological structure based on ECL logical device able to programme is simple, frequency domain is wide, signal stabilization, phase noise is little, cost is low, circuit area is little high frequency phase-shift circuit.
The technical scheme that technical solution problem of the present invention is taked:
The present invention includes quick comparator, PLL frequency multiplier, ECL signal clock distributor, pulse suppressor, first digital frequency divider and second digital frequency divider.Comparator is converted into square-wave signal with external timing signal fast; PLL frequency multiplier able to programme is with this square-wave signal frequency multiplication; ECL signal clock distributor is dispensed to two-way with this frequency-doubled signal; One road frequency-doubled signal is via the direct frequency division of first digital frequency divider; Another road frequency-doubled signal is suppressed by pulse suppressor after the phase shift of one 2 π by the second digital frequency divider frequency division; The frequency division multiple of first digital frequency divider and second digital frequency divider is
; P is an integer, and the output signal of relative second digital frequency divider of output signal of first digital frequency divider has the phase shift of
.
Beneficial effect of the present invention is: 1, circuit design principle is simple, and reproducibility is strong; 2, the circuit volume is little; 3, the phase shift signalling noise is little; 4, phase shift signalling is stable; 5, phase shift precision is high; 6, antijamming capability is strong; 7, cost is low.
Description of drawings
Fig. 1 produces schematic diagram for high frequency phase shift generation circuit phase shift of the present invention.
Fig. 2 is the structural representation of high frequency phase shift generation circuit of the present invention.
Fig. 3 produces principle schematic for pulse of the present invention suppresses ripple.
Fig. 4 is the circuit theory diagrams of comparator in the high frequency phase shift generation circuit of the present invention.
Fig. 5 is the circuit theory diagrams of PLL frequency multiplier in the high frequency phase shift generation circuit of the present invention.
Fig. 6 is the circuit theory diagrams of ECL signal clock distributor in the high frequency phase shift generation circuit of the present invention.
Fig. 7 is the circuit theory diagrams of TTL signal to ECL signal converter in the high frequency phase shift generation circuit of the present invention.
Fig. 8 is the circuit theory diagrams of synchronizer trigger in the high frequency phase shift generation circuit of the present invention.
Fig. 9 is the circuit theory diagrams of first delayer in the high frequency phase shift generation circuit of the present invention and second delayer.
Figure 10 is the circuit theory diagrams of XOR gate in the high frequency phase shift generation circuit of the present invention.
Figure 11 is the circuit theory diagrams of the 3rd delayer in the high frequency phase shift generation circuit of the present invention.
Figure 12 is the circuit theory diagrams of first frequency divider in the high frequency phase shift generation circuit of the present invention and second frequency divider.
Figure 13 is an embodiment of the invention stable output signal property testing experimental result picture.
Embodiment
Further specify the present invention below in conjunction with accompanying drawing.
The present invention includes quick comparator, PLL frequency multiplier, ECL signal clock distributor, pulse suppressor, frequency divider.Fast comparator with external timing signal through being converted into square-wave signal; PLL frequency multiplier able to programme is with this square-wave signal frequency multiplication; ECL signal clock distributor is dispensed to two-way with this frequency-doubled signal; One the tunnel via digital frequency divider 1 direct frequency division, and another road frequency-doubled signal suppresses a pulse (corresponding phase shift is 2 π) back by digital frequency divider 2 frequency divisions by pulse suppressor, and the frequency division multiple of digital frequency divider 1 and digital frequency divider 2 is
(p is an integer), then the output signal of the relative digital frequency divider 2 of output signal of digital frequency divider 1 has
Phase shift; Phase shift principle figure is as shown in Figure 1, and frequency does
f HFHigh-frequency digital logic ECL signal suppresses a pulse with the ECL logical device, then should have the phase shift of 2 π to produce mutually, and behind this signal two divided-frequency, phase-shift phase is π, but because of ECL signal frequency frequency division does
Doubly, then do in frequency
The signal place have value to do
Phase shift signalling produce.
As shown in Figure 2.External clock source signal S
CLKBe converted into square-wave signal through quick comparator, the PLL frequency multiplier is with this square-wave signal frequency multiplication, and establishing the frequency multiplication multiple is N, and then the output signal frequency of frequency multiplier does
f HF(
), this frequency-doubled signal is dispensed to two-way by ECL signal clock distributor, and one road ECL frequency-doubled signal directly is dispensed to frequency divider 1; The output signal of frequency divider 1 is S1; Another road ECL frequency-doubled signal is dispensed to pulse suppressor, and pulse suppressor suppresses certain pulse of this ECL frequency-doubled signal, and the ECL frequency-doubled signal after being suppressed by pulse is sent to frequency divider 2; The output signal of frequency divider 2 is S2, and the frequency division multiple of frequency divider 1 and frequency divider 2 is
, then the phase-shift phase of signal S2 relative signal S1 does
, the frequency of signal S1 and signal S2 is
In conjunction with Fig. 2 and Fig. 3, pulse suppressor of the present invention is made up of TTL to ECL signaling conversion circuit, synchronizer trigger, delayer 1, delayer 2, NOR gate circuit, delayer 3.
Be the pulse suppressor structured flowchart in the frame of broken lines among Fig. 2, pulse suppresses to trigger the TTL signal and converts the ECL signal to through conversion circuit, and this ECL signal is via synchronizer trigger and PLL frequency-doubled signal S
HFSynchronously.With frequency-doubled signal S
HFSynchronous ECL signal is sent to delayer 1 and delayer 2 simultaneously, and delayer 1 output amount of delay is the inhibit signal S of t1
T1, delayer 2 output amount of delay are the inhibit signal S of t2
T2, its waveform is as shown in Figure 3, signal S
T1With signal S
T2Via the XOR gate XOR, XOR gate is output as pulse and suppresses signal, and the pulse duration that this pulse suppresses signal equals frequency-doubled signal
S HFCycle, promptly
As shown in Figure 3, the edge of each outer triggering signal all triggers a pulsewidth and does
T HFThe inhibition signal, this inhibition signal suppresses frequency-doubled signal through delayer 3
S HFThereby, realize the phase shift of 2 π.
Fast the schematic diagram of comparator can be referring to shown in Fig. 4, comprises first capacitor C 1, second capacitor C 2, comparator AD8598 fast.The input pin INA-of comparator AD8598 connects external clock source signal Sclk; The input pin INA+ of comparator AD8598, INB+, INB-, GND, V-ground connection, the output pin QA output signal Sa of comparator AD8598; One end of one end of the pin V+ of comparator AD8598, first capacitor C 1, second capacitor C 2 is connected with 5V; The equal ground connection of the other end of the other end of first electric capacity, second electric capacity; All the other pins of comparator AD8598 are unsettled.
First capacitor C, 1 appearance value is that 100nF, second capacitor C, 2 appearance values are that 10nF plays the power supply filter action in high-frequency circuit.
The schematic diagram of PLL frequency multiplier can be referring to shown in Figure 5, comprises first resistance R 1, the 3rd capacitor C 3, the 4th capacitor C 4, the 5th capacitor C 5, the 6th capacitor C 6.
Doubler MC12349 input pin PREF_EXT connection comparator AD8598 output signal Sa; multiplier MC12349 output pin FOUT,
, respectively, and the signal output signal Sb
; multiplier MC12349 pin S_CLOCK, S_DATA,? S_LOAD, PWR -DOWN?, GND Ground; multiplier MC12349 pin OE,
?, and a third capacitor C3 is connected to one end of +5 V; multiplier MC12349 pin Vcc and the fourth capacitor C4 is connected to one end of 5V; octave device MC12349 PLL-Vcc pin and the first end of the resistor R1, the fifth capacitor C5, sixth capacitor C6 is connected to one end; multiplier MC12349 pin N [1], N [0], M [6] , M [5], M [4], M [3], M [2], M [1], M [0], respectively, and the switch SWITCH? 1 of 1,2,3,4,5,6,7 , 8,9 terminals; multiplier MC12349 pin XTAL1, XTAL2, NC, XTAL_SEL, TEST are vacant; Switch SWITCH-1 of the 10,11,12,13,14,15,16,17,18 ground terminal; third capacitor C3, the fourth capacitor C4, fifth capacitor C5, sixth capacitor C6 and the other end, the other end of the first resistor R1 is +5 V.
The value that the capacitance of the 3rd capacitor C 3, the 4th capacitor C 4, the 5th capacitor C 5 is 10nF, the 6th capacitor C 6 is that 22nF strobes in circuit, and the value of first resistance is 15 Ω work to keep frequency multiplier MC12349 pin PLL_Vcc in circuit a voltage.
The output frequency of PLL frequency multiplier MC12439 is adjustable.The scope of the output frequency of frequency multiplier MC12349 is 50 to 800MHz, and the incoming frequency scope is 10 to 20MHz, output frequency F
OUTWith incoming frequency F
XTALRelation do
, the value of M and N can change through changing the value that is connected switch.
The schematic diagram of ECL clock distributor can be referring to shown in Figure 6, comprises the 7th capacitor C 7, the 8th capacitor C 8, second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, the 7th resistance R 7, the 8th resistance R 8, the 9th resistance R 9, clock distributor MC10EL15.Clock divider MC10EL15 CLK input pin to connect the input signal Sb and sixth resistor R6, seventh resistor R7 end; clock divider MC10EL15 input pin
Connect the input signal
and eighth resistor R8, ninth resistor R9 end; clock divider MC10EL15 pin
, SCLK, SEL, VEE ground; clock divider MC10EL15 pin connected to +5 V and VII Vcc capacitor C7, eighth capacitor C8 end; clock divider MC10EL15 output pin connected to output Q1 signal Sc, Q2 output pin connected to the output signal Sd, output pin
connected to the output signal
, the output pin is connected to the output signal Q3 Se; clock divider MC10EL15 output pin
take a second resistor R2, the end of the third resistor R3; MC10EL15 output pin
then a fourth resistor R4, one end of the fifth resistor R5; third resistor R3, a fifth resistor R5, the seventh resistor R7, the ninth resistor R9, the seventh capacitor C7, the other end of the eighth capacitor C8 to ; second resistor R2, a fourth resistor R4, a sixth resistor R6, the other end of the eighth resistor R8 +5 V; clock divider MC10EL15 pins Q0,
, VBB unconnected.
The 7th capacitor C 7 appearance values are that 10nF, the 8th capacitor C 8 appearance values are that 100nF plays the power supply filter action in high-frequency circuit; The resistance that the resistance of second resistance R 2, the 4th resistance R 4, the 6th resistance R 6, the 8th resistance R 8 is 86 Ω, the 3rd resistance R 3, the 5th resistance R 5, the 7th resistance R 7, the 9th resistance R 9 is 118 Ω, and being chosen for of these resistance values satisfied the direct-current coupling needs of the input of PECL signal and output.
The schematic diagram of TTL-ECL signal converter can be referring to shown in Figure 7, comprises the 9th capacitor C 9, the tenth capacitor C 10, the tenth resistance R the 10, the 11 resistance R 11, signal converter MC10ELT20.The input pin D0 of signal converter MC10ELT20 connects input signal Scomm, and input signal Scomm is an external trigger TTL signal; The output pin Q of signal converter MC10ELT20 connects output signal Sf; The output pin of signal converter MC10ELT20
connects an end of the tenth resistance R 10, an end of the 11 resistance R 11; The pin VCC of signal converter MC10ELT20 connects power supply+5V, an end of the 9th capacitor C 9, an end of the tenth capacitor C 10; The pin GND ground connection of signal converter MC10ELT20; All the other pins of signal converter MC10ELT20 are unsettled; The other end of another termination+5V of the tenth resistance R 10, the other end ground connection of the 11 resistance R 11, the 9th capacitor C 9, the other end ground connection of the tenth capacitor C 10.
The appearance value of the 9th capacitor C 9 is that the appearance value of 10nF, the tenth capacitor C 10 is that 100nF plays the power supply filter action in high-frequency circuit; The resistance of the tenth resistance R 10 is that the resistance of 86 Ω, the 11 resistance R 11 is 118 Ω, and input of PECL signal and the direct-current coupling needs of exporting are satisfied in being chosen for of these resistance values.
The schematic diagram of synchronizer trigger is as shown in Figure 8, comprises the 11 capacitor C the 11, the 12 capacitor C the 12, the 12 resistance R the 12, the 13 resistance R the 13, the 14 resistance R the 14, the 15 resistance R 15, synchronizer trigger MC10EP31.Synchronization triggers MC10EP31 CLK input pin connected input signal Sc (signal distributor MC10EL15 signal Sc is the output signal), one end of resistor R14 fourteenth, fifteenth resistor R15 at one end; synchronous trigger input pin MC10EP31 D received input signal Sf (signal Sf is MC10ELT20 signal converter output signal), one end of resistor R12 twelfth, thirteenth resistor R13 end; synchronous trigger MC10EP31 pin
Connection output signal
; synchronize the trigger MC10EP31 Q Connect the output signal pin Sg; synchronization triggers MC10EP31 pin VCC capacitor C11 is connected at one end eleventh, the twelfth capacitor C12 end; synchronous trigger MC10EP31 pin VEE, RST, SET to ground.
The 11 capacitor C 11 appearance values are that 10nF, the 12 capacitor C 12 appearance values are that 100nF plays the power supply filter action in high-frequency circuit; The resistance that the resistance of the 12 resistance R 12, the 14 resistance R 14 is 86 Ω, the 13 resistance R 13, the 15 resistance R 15 is 118 Ω, and being chosen for of these resistance values satisfied the direct-current coupling needs of the input of PECL signal and output.
The delayer circuit theory diagrams can be referring to shown in Fig. 9, comprises the 13 capacitor C the 13, the 14 capacitor C the 14, the 15 capacitor C the 15, the 16 capacitor C the 16, the 16 resistance R the 16, the 17 resistance R the 17, the 18 resistance R the 18, the 19 resistance R the 19, the 20 resistance R the 20, the 21 resistance R the 21, the 22 resistance R the 22, the 23 resistance R 23, the first delayer MC10EP195-1, the second delayer MC10EP195-2.
First delay MC10EP195-1 IN connector pin input signal Sg, seventeenth end of resistor R17, one end of the sixteenth resistor R16; first delay MC10EP195-1 pin
Connect the input signal
, eighteenth resistance R18 one end of the nineteenth resistors R19 end; first delay MC10EP195-1 output pin
Connection output signal
; first delay MC10EP195-1 output pin Q is connected to the output signal Sh; first delay MC10EP195- a connecting pin VCC +5 V, XIII capacitor C13 end of the fourteenth end of capacitor C14; first delay MC10EP195-1 pin SETMAX,? SETMIN, LEN, VEE ground; first delay MC10EP195 -1 VEF pin VCF and shorting pin, a first delay MC10EP195-1 pin D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10 are connected to the switch SWITCH-2 Pin 18,17,16,15,14,13,12,11,10 and switch SWITCH-3 pin 4 and 3; first delay MC10EP195-1 the rest of the pin unconnected.
Another termination+5V of the other end of the 16 resistance R 16, the 17 resistance R 18; The other end ground connection of the other end of the 17 resistance R 17, the 19 resistance R 19; The other end ground connection of the other end of the 13 capacitor C 13, the 14 capacitor C 14; The pin 1,2,3,4,5,6,7,8,9 of switch SW ITCH-2 and the pin 1 and 2 of switch SW ITCH-3 connect+5V.
Second delay MC10EP195-2 connect the input pin IN Sg, end of a twenty-first resistor R21, one end of the twenty-resistance R20; second delay MC10EP195-2 pin
Connect the input signal
, the twenty- One end of the resistors R22, one end of the twenty-third resistor R23; MC10EP195-2 second delay output pin
Connection output signal
; second delay MC10EP195-2 output pin Q is connected to the output signal Si; second delay device MC10EP195-2 pin VCC is connected +5 V, one end of the fifteenth capacitors C15, C16 capacitor XVI end; second delay MC10EP195-2 pin SETMAX,? SETMIN, LEN, VEE ground; second delay MC10EP195-1 VEF pins shorted to pin VCF, second delay MC10EP195-2 pin D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10 are connected to the switch SWITCH-4 pin 18,17,16,15,14,13,12,11,10 and Switches SWITCH-5 pin 4 and 3; second delay MC10EP195-2 of the other pins unconnected.
Another termination+5V of the other end of the 20 resistance R 20, the 21 resistance R 21; The other end ground connection of the other end of the 22 resistance R 22, the 23 resistance R 23; The other end ground connection of the other end of the 15 capacitor C 15, the 16 capacitor C 16; The pin 1,2,3,4,5,6,7,8,9 of switch SW ITCH-4 and the pin 1 and 2 of switch SW ITCH-5 connect+5V.
The appearance value that the appearance value of the 13 capacitor C the 13, the 15 capacitor C 15 is 10nF, the 14 capacitor C the 14, the 16 capacitor C 16 is 100nF and in high-frequency circuit, plays the power supply filter action; The resistance that the resistance of the 12 resistance R 12, the 14 resistance R 14 is 86 Ω, the 17 resistance R the 17, the 19 resistance R the 19, the 21 resistance R 21, the 23 resistance R 23 is 118 Ω, and being chosen for of these resistance values satisfied the direct-current coupling needs of the input of PECL signal and output.
The NOR gate circuit schematic diagram is shown in figure 10; Comprise the 24 resistance R the 24, the 25 resistance R the 25, the 26 resistance R the 26, the 27 resistance R the 27, the 28 resistance R the 28, the 29 resistance R the 29, the 30 resistance R the 30, the 31 resistance R the 31, the 32 resistance R the 32, the 33 resistance R 23, the 17 capacitor C the 17, the 18 capacitor C 18, XOR gate MC10EP08.XOR gate MC10EP08 input pin
Connect the input signal
, the twenty-fourth resistor R24?'s end, the end of the twenty-fifth resistor R25; XOR gate MC10EP08 input pin D1 is connected input signal Sh, twenty-sixth resistor R26?'s end, the end of the twenty-seventh resistor R27; XOR gate MC10EP08 input pin
Connect the input signal
, the twenty-sixth resistor R28?'s end, the end of the twenty-seventh resistor R29; XOR gate MC10EP08 of Connect the input signal input pin D0 Si, thirtieth resistor R30?'s end, the end of the thirty-first resistor R31; XOR gate MC10EP08 pin VCC connects to +5 V, seventeenth capacitor C17 end of the eighteenth One end of capacitor C18; XOR gate MC10EP08 pin VEE ground; XOR gate MC10EP08 output pin
resistor R32 connected to one end of the thirty-second, thirty-third resistor R33 at one end; XOR gate MC10EP08 output pin Q Connect the output signal Sj.
The other end ground connection of the other end of the 17 capacitor C 17, the 18 capacitor C 18; The other end of the other end of the 24 resistance R 24, the other end of the 26 resistance R 26, the 28 resistance R 28, another termination+5V of the 30 resistance R the 30, the 32 resistance R 32; The other end of the 25 resistance R 25,, the other end of the 27 resistance R 27, the other end ground connection of the other end of the 29 resistance R 29, the 31 resistance R 31.
The appearance value that the appearance value of the 17 capacitor C 17 is 10nF, the 18 capacitor C 18 is that 100nF plays the power supply filter action in high-frequency circuit; The resistance that the resistance of the 24 resistance R the 24, the 26 resistance R the 26, the 28 resistance R 28, the 30 resistance R 30 is 86 Ω, the 25 resistance R the 25, the 27 resistance R the 27, the 29 resistance R 29, the 31 resistance R 31 is 118 Ω, and being chosen for of these resistance values satisfied the direct-current coupling needs of the input of PECL signal and output.
It is shown in figure 11 to realize that through delayer 3 pulse of frequency-doubled signals suppresses schematic diagram, comprises the 18 capacitor C the 18, the 19 capacitor C the 19, the 34 resistance R the 34, the 35 resistance R the 35, the 36 resistance R the 36, the 37 resistance R the 37, the 38 resistance R the 38, the 39 resistance R 39, the 3rd delayer MC10EP195-3.
The third delay MC10EP195-3 pin
Connect the input signal
, the thirty-fourth resistor R34 at one end, the end of the thirty-fifth resistor R35; third delay MC10EP195-3 IN connector pin input signal Sd, third one end of resistor R36 sixteen, thirty-seventh resistor R37 at one end; third delay MC10EP195-3 output pin
resistor R38 connected to one end of the thirty-eighth, thirty-ninth resistor R39 at one end; third delay MC10EP195-3 output pin Q is connected to the output signal Sk; third delay MC10EP195-3 pin VCC is connected 5V, capacitor C19 end of the nineteenth, twenty one end of capacitor C20; third delay MC10EP195-3 pin SETMAX,? SETMIN, LEN, VEE ground; third delay VCF MC10EP195-3 pin shorted to pin VEF, the third delay C10EP195-3 pin D0, D1, D2, D3, D4 , D5, D6, D7, D8, D9, D10 ground; third delay MC10EP195-3 the rest of the pin unconnected.
Another termination+5V of the other end of the 34 resistance R 34, the other end of the 36 resistance R 36, the 38 resistance R 38; The other end ground connection of the other end of the 35 resistance R 35, the other end of the 37 resistance R 37, the 39 resistance R 39; The other end ground connection of the other end of the 19 capacitor C 19, the 20 capacitor C 20.
The appearance value of the 19 capacitor C 19 is that the appearance value of 10nF, the 20 capacitor C 20 is 100nF and in high-frequency circuit, plays the power supply filter action; The resistance that the resistance of the 34 resistance R the 34, the 36 resistance R 36, the 38 resistance R 38 is 86 Ω, the 35 resistance R the 35, the 37 resistance R 37, the 39 resistance R 39 is 118 Ω, and being chosen for of these resistance values satisfied the direct-current coupling needs of the input of PECL signal and output.
The 3rd delayer MC10EP195-3 is different from the delay function of the first delayer MC10EP195-1 and the second delayer MC10EP195-2; The D0 of the 3rd delayer～D10 holds ground connection; Be 0 time of delay; Its specific function is a pulse-triggered; Its course of work is: the high-frequency signal Sd/
of XOR signal Sj and the output of frequency-doubled signal device is sent to the 3rd delayer MC10EP195-3 simultaneously, and the Enable Pin of MC10EP195-3 connects XOR signal Sj, and input connects frequency multiplier output signal; Its characteristic is for when enabling the termination high level; MC10EP195-3 is output as low level, and when Enable Pin was low level, the output signal was input signal; Because the pulsewidth of XOR signal is a high-frequency signal cycle (high level lasting time is a high-frequency signal cycle), so the 3rd delayer is output as the high-frequency signal after a pulse suppresses.
The schematic diagram of frequency divider can be referring to shown in Figure 12, comprises the 21 capacitor C the 21, the 22 capacitor C the 22, the 23 capacitor C the 23, the 24 capacitor C the 24, the 25 capacitor C the 25, the 26 capacitor C the 26, the 27 capacitor C the 27, the 28 capacitor C the 28, the 29 capacitor C the 29, the 30 capacitor C the 30, the 40 resistance R the 40, the 41 resistance R the 41, the 42 resistance R the 42, the 43 resistance R the 43, the 44 resistance R the 44, the 45 resistance R the 45, the 46 resistance R the 46, the 47 resistance R the 47, the 48 resistance R the 48, the 49 resistance R 49, the first digital frequency divider SP8402-1, the second digital frequency divider SP8402-2.
Two input pin CLKIN short circuits of the first digital frequency divider SP8402-1 and connect input signal Sk, an end of the 40 resistance R 40, an end of the 41 resistance R 41; Two input pins of the first digital frequency divider SP8402-1
short circuit and connect an end of the 21 capacitor C 21, an end of the 22 capacitor C 22; The output pin of the first digital frequency divider SP8402-1
connects an end of the 42 resistance R 42; The output pin OUTPUT of the first digital frequency divider SP8402-1 connects an end of the 25 capacitor C 25, an end of the 43 resistance R 43; The pin VCC of the first digital frequency divider SP8402-1 all connects+5V, an end of the 23 capacitor C 23, an end of the 24 capacitor C 24; The pin GND ground connection of the first digital frequency divider SP8402-1; The pin S0 of the first digital frequency divider SP8402-1, S1, S2 connect 3,2,1 pin of switch SW ITCH-6 respectively; The other end of the 21 capacitor C 21, the other end of the 22 capacitor C 22, the other end of the 23 capacitor C 23, the other end ground connection of the 24 capacitor C 24; Other end connection+the 5V of the 40 resistance R 40; 4,5,6 pins of switch SW ITCH-6 connect+5V; The one termination output signal S1 of the other end of the 25 capacitor C 25, the 44 resistance R 44; The other end ground connection of the other end of the 41 resistance R 41, the 42 resistance R 42 other ends, the 43 resistance R 43 other ends, the 44 resistance R 44.
The appearance value of the 21 capacitor C the 21, the 23 capacitor C 23 is 10nF; The appearance value of the 22 capacitor C the 22, the 24 capacitor C 24 is that 100nF plays the power supply filter action in high-frequency circuit; The resistance of the 40 resistance R 40 is that the resistance of 86 Ω, the 41 resistance R 41 is 118 Ω, and the resistance of the 42 resistance R 42 is that the resistance of 330 Ω, the 43 resistance R 43 is that the resistance of 330 Ω, the 44 resistance is 50 Ω; Input of PECL signal and the direct-current coupling needs of exporting are satisfied in being chosen for of these resistance values.
Two input pin CLKIN short circuits of the second digital frequency divider SP8402-2 and connect input signal Se, an end of the 45 resistance R 45, an end of the 46 resistance R 46; Two input pins of the second digital frequency divider SP8402-2
short circuit and connect an end of the 26 capacitor C 26, an end of the 27 capacitor C 27; The output pin of the second digital frequency divider SP8402-2
connects an end of the 47 resistance R 47; The output pin OUTPUT of the second digital frequency divider SP8402-2 connects an end of the 30 capacitor C 30, an end of the 48 resistance R 48; The pin VCC of the second digital frequency divider SP8402-2 all connects+5V, an end of the 28 capacitor C 28, an end of the 29 capacitor C 29; The pin GND ground connection of the second digital frequency divider SP8402-2; The pin S0 of the second digital frequency divider SP8402-2, S1, S2 connect 3,2,1 pin of switch SW ITCH-7 respectively; The other end of the 26 capacitor C 26, the other end of the 27 capacitor C 27, the other end of the 28 capacitor C 28, the other end ground connection of the 29 capacitor C 29; Other end connection+the 5V of the 45 resistance R 45; 4,5,6 pins of switch SW ITCH-7 connect+5V; The one termination output signal S2 of the other end of the 30 capacitor C 30, the 49 resistance R 49; The other end ground connection of the other end of the 46 resistance R 46, the other end of the 47 resistance R 47, the 48 resistance R 48 other ends, the 49 resistance R 49.
The appearance value of the 26 capacitor C the 26, the 28 capacitor C 28 is 10nF; The appearance value of the 27 capacitor C the 27, the 29 capacitor C 29 is that 100nF plays the power supply filter action in high-frequency circuit; The resistance of the 45 resistance R 45 is that the resistance of 86 Ω, the 46 resistance R 46 is 118 Ω, and the resistance of the 47 resistance R 47 is that the resistance of 330 Ω, the 48 resistance R 48 is that the resistance of 330 Ω, the 49 resistance R 49 is 50 Ω; Input of PECL signal and the direct-current coupling needs of exporting are satisfied in being chosen for of these resistance values.
The present invention utilizes the little advantage of ECL signal rising edge and trailing edge time short (
), operating frequency big (
), phase noise and the characteristic of ECL programmable logic device input/output signal programmable frequency; The high frequency phase-shift circuit frequency domain of realizing is wide, the output signal frequency programming is adjustable, and stable output signal, the stepping phase-shift value is adjustable and circuit area is little, cost is low.
The frequency output area of PLL frequency multiplier is 50 to 800MHz (f in the high frequency phase-shift circuit of the present invention
HZ=50～800MHz), the frequency division multiple of frequency divider does
(p=1～8), the frequency output valve of high frequency phase shift generation circuit does
, corresponding stepping phase-shift value does
, then the frequency output area of high frequency phase shift generation circuit is 0.2 ~ 400MHz, attainable phase shift step value is respectively:
,
,
,
,
,
,
,
Embodiments of the invention are the phase-shift value of 2 π/32 for the high frequency phase-shift circuit produces step value, and output frequency is 20MHz.The frequency of external clock source signal Sclk is 10MHz, and frequency multiplier frequency multiplication multiple is set to 64, and then the high-frequency signal of frequency multiplier output is 640MHz; T1 time of delay of delayer 1 is 2200ps, and t2 time of delay of delayer 2 is 3760ps, then t
2-t
1=1560ps=1/640MHz, the frequency division multiple is set to 1/32.Figure 13 is the test experiments figure as a result of present embodiment.We have tested the stability of the 20MHz frequency signal of phase shift generation circuit generation.The acquisition time of signal frequency is about 12 hours, and be 1s each time of integration of measuring.After experimental data being carried out relative Alan's variance calculating, draw the time of integration to 1000s, Alan's standard variance value for 1s
Less than 10
-9We can say that it is insignificant that phase shift produces the swinging of signal of circuit qualitative.
Claims (6)
1. based on the high frequency phase shift signalling generation circuit of ECL logical device able to programme; Comprise quick comparator, PLL frequency multiplier, ECL signal clock distributor, pulse suppressor, first digital frequency divider and second digital frequency divider; It is characterized in that: comparator is converted into square-wave signal with external timing signal fast; PLL frequency multiplier able to programme is with this square-wave signal frequency multiplication; ECL signal clock distributor is dispensed to two-way with this frequency-doubled signal; One road frequency-doubled signal is via the direct frequency division of first digital frequency divider; Another road frequency-doubled signal is suppressed by pulse suppressor after the phase shift of one 2 π by the second digital frequency divider frequency division; The frequency division multiple of first digital frequency divider and second digital frequency divider is
; P is an integer, and the output signal of relative second digital frequency divider of output signal of first digital frequency divider has the phase shift of
.
2. high frequency phase shift signalling generation circuit according to claim 1 is characterized in that: described quick comparator comprises first capacitor C 1, second capacitor C 2 and comparator chip AD8598; The input pin INA-of comparator chip AD8598 connects outside input clock signal Sclk; The input pin INA+ of comparator chip AD8598, INB+, INB-, GND, V-ground connection; The output pin QA of comparator chip AD8598 connects output signal Sa, and an end of the pin V+ of comparator chip AD8598, first capacitor C 1, an end of second capacitor C 2 are connected with 5V; The equal ground connection of the other end of the other end of first capacitor C 1, second capacitor C 2; All the other pins of comparator chip AD8598 are unsettled.
3 according to claim 1, wherein the high-frequency phase shift signal generating circuit characterized in that: said PLL frequency multiplier includes a first resistor R1, the third capacitor C3, the fourth capacitor C4, fifth capacitor C5 and six capacitors C6; multiplier chip MC12349 connected input pin PREF_EXT chip AD8598 comparator output signal Sa; multiplier chip MC12349 output pin FOUT,
, respectively, and the signal output signal Sb
; multiplier chip MC12349 pin S_CLOCK, S_DATA,? S_LOAD, PWR-DOWN, GND Ground; multiplier chip MC12349 pin OE,
, the third capacitor C3 is connected to one end of the +5 V ; frequency chip MC12349 pin Vcc, the fourth capacitor C4 is connected to one end of the 5V; frequency chip MC12349 PLL-Vcc pin of the resistor R1 and the first end of the fifth capacitor C5, sixth capacitor C6 end connector; frequency chip MC12349 pin N [1], N [0], M [6], M [5], M [4], M [3], M [2], M [1] , M [0], respectively, and the switch SWITCH? 1 of 1,2,3,4,5,6,7,8,9 connected to the terminal; multiplier chip MC12349 pin XTAL1, XTAL2, NC, XTAL_SEL, TEST are vacant; Switch SWITCH-? 1 of 10,11,12,13,14,15,16,17,18 terminal grounded; third capacitor C3, the fourth capacitor C4, fifth capacitor C5, sixth capacitor C6 the other end, the other end of the first resistor R1 +5 V.
As claimed in claim 1, wherein the high-frequency phase shift signal generating circuit, wherein: said clock divider ECL signals includes a seventh capacitor C7, the eighth capacitor C8, a second resistor R2, third resistor R3, fourth resistor R4, fifth resistor R5, sixth resistor R6, seventh resistor R7, eighth resistor R8, ninth resistor R9, clock divider chip MC10EL15; clock divider chip MC10EL15 CLK input pin connected input signal Sb and a sixth resistor R6, one end of the seventh resistor R7; clock divider chip MC10EL15 input pin
Connect the input signal
and eighth resistor R8, ninth resistor R9 end; clock distribution chip MC10EL15 pin
, SCLK, SEL, VEE ground; clock divider chip MC10EL15 pin connected to +5 V and VII Vcc capacitor C7, eighth capacitor C8 end; clock divider chip MC10EL15 of output pin connected to the output signal Q1 Sc, the output pin connected to the output signal Q2 Sd, the output pin
connected to the output signal
, the output pin is connected to the output signal Q3 Se; clock divider chip MC10EL15 of Output pin
then a second resistor R2, one end of the third resistor R3; clock divider chip MC10EL15 output pin
take a fourth resistor R4, the end of the fifth resistor R5; Third resistor R3, a fifth resistor R5, the seventh resistor R7, the ninth resistor R9, the seventh capacitor C7, the other end of the eighth capacitor C8 ground; second resistor R2, a fourth resistor R4, a sixth resistor R6, the eighth resistor the other end of R8 +5 V; clock divider chip MC10EL15 pins Q0,
, VBB unconnected.
5. high frequency phase shift signalling generation circuit according to claim 1, it is characterized in that: said pulse suppressor is made up of TTL to ECL change-over circuit, synchronizer trigger, first delayer, second delayer, NOR gate circuit, the 3rd delayer;
Described TTL-ECL signal converter comprises the 9th capacitor C 9, the tenth capacitor C 10, the tenth resistance R the 10, the 11 resistance R 11, signal converter chip MC10ELT20; The input pin D0 of signal converter chip MC10ELT20 connects input signal Scomm, and input signal Scomm is an external trigger TTL signal; The output pin Q of signal converter chip MC10ELT20 connects output signal Sf; The output pin of signal converter chip MC10ELT20
connects an end of the tenth resistance R 10, an end of the 11 resistance R 11; The pin VCC of signal converter chip MC10ELT20 connects power supply+5V, an end of the 9th capacitor C 9, an end of the tenth capacitor C 10; The pin GND ground connection of signal converter chip MC10ELT20; All the other pins of signal converter chip MC10ELT20 are unsettled; The other end of another termination+5V of the tenth resistance R 10, the other end ground connection of the 11 resistance R 11, the 9th capacitor C 9, the other end ground connection of the tenth capacitor C 10;
The synchronization triggers include eleventh capacitor C11, twelfth capacitor C12, twelfth resistor R12, thirteenth resistor R13, fourteenth resistor R14, fifteenth resistor R15, the synchronization triggers chip MC10EP31; synchronization trigger input pin CLK chip MC10EP31 connected input signal Sc, one end of resistor R14 XIV, XV end of resistor R15; synchronous trigger input pin D chip MC10EP31 connected input signal Sf, twelfth resistor R12 one end of the thirteenth resistor R13 end; synchronous trigger chip MC10EP31 pin
Connection output signal
; synchronous trigger pin chip MC10EP31 output signal Q is connected Sg; synchronization triggers Chip MC10EP31 pin VCC capacitor C11 is connected to one end of the eleventh, twelfth capacitor C12 end; synchronous trigger chip MC10EP31 pin VEE, RST, SET ground;
Described first delayer comprises the 13 capacitor C the 13, the 14 capacitor C the 14, the 16 resistance R the 16, the 17 resistance R the 17, the 18 resistance R the 18, the 19 resistance R 19, the first delayer chip MC10EP195-1;
First delay chip MC10EP195-1 IN connector pin input signal Sg, seventeenth resistor R17 end, one end of the sixteenth resistor R16; first delay chip MC10EP195-1 pin
Connection input signal
, one end of the eighteenth resistor R18, one end of the nineteenth resistor R19; first delay MC10EP195-1 chip output pin
Connection output signal
; first delay MC10EP195-1 chip output pin Q is connected to the output signal Sh; first delay MC10EP195-1 chip pin to VCC +5 V, one end of the thirteenth capacitor C13, one end of the fourteenth capacitor C14; first delay MC10EP195-1 chip pins SETMAX,? SETMIN, LEN, VEE ground; first delay pin chip MC10EP195-1 VEF VCF and shorting pins, the first chip delay the argument MC10EP195-1 pin D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10 are connected to the switch SWITCH-2? pin 18,17,16,15,14,13,12,11,10 and Switch SWITCH-3 of the pins 4 and 3; first delay chip MC10EP195-1 of the other pins floating; other end of the sixteenth resistor R16, the other end of the seventeenth resistor R18 +5 V; seventeenth resistor The other end of R17, the R19 resistor nineteenth other end; thirteenth capacitor C13 the other side, the other end of the fourteenth capacitor C14 ground; switch SWITCH-2 pin 1,2,3,4,5 , 6,7,8,9 and Switches SWITCH-3 pins 1 and 2 connected to +5 V;
Second delay chip MC10EP195-2 connect the input pin IN Sg, the end of the twenty-first resistor R21, one end of the twenty-resistance R20; second delay MC10EP195-2 chip pin
Connect the input signal
, the twenty-second end of resistor R22, one end of the twenty-third resistor R23; second delay MC10EP195-2 chip output pin
Connection output signal
; second delay chip MC10EP195-2 output pin Q is connected to the output signal Si; second delay chip MC10EP195-2 pin connected to VCC +5 V, one end of the fifteenth capacitors C15, C16 capacitor XVI end; second delay MC10EP195-2 chip pin SETMAX,? SETMIN, LEN, VEE ground; second delay chip pin VCF MC10EP195-1 VEF shorted to pin, the second delay chip MC10EP195- 2 pin, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10 are connected to the switch SWITCH-4? pin 18,17,16,15,14,13,12,11 , 10 and the switch SWITCH-5 of the pins 4 and 3; second delay MC10EP195-2 of the other pins unconnected; twenty other end of resistor R20, a twenty-first resistor R21 and the other end +5 V; s twenty-two the other end of the resistor R22, the other twenty-third resistor R23 connected to ground; capacitor C15 the other end of the fifteenth, sixteenth other end of capacitor C16; switch SWITCH-4 of the pin 2, 3,4,5,6,7,8,9 & Switch SWITCH-5 pins 1 and 2 connected to +5 V;
The exclusive OR gate circuit comprises a twenty-fourth resistor R24, the twenty-fifth resistor R25, the twenty-sixth resistor R26, the twenty-seventh resistor R27, the twenty-eighth resistor R28, the twenty-ninth resistor R29, thirtieth resistor R30, the thirty-first resistor R31, thirty second resistor R32, the thirty-third resistor R23, seventeenth capacitor C17, eighteenth capacitor C18, XOR gate chip MC10EP08; XOR gate chip MC10EP08 input pin
Connect the input signal
, the twenty-fourth resistor R24?'s end, the end of the twenty-fifth resistor R25; XOR gate chip MC10EP08 input pin D1 is connected input signal Sh, twenty-sixth resistor R26?'s end, one end of the twenty-seventh resistor R27; XOR gate chip MC10EP08 input pin
Connect the input signal
, the twenty-sixth resistor R28 ? the end of the twenty-seventh resistor R29 at one end; XOR gate chip MC10EP08 input pin D0 connect the input signal Si, thirtieth resistor R30?'s end, the end of the thirty-first resistor R31; XOR gate chip MC10EP08 pin VCC connects to +5 V, one end of the seventeenth capacitors C17, C18 capacitor one end of the eighteenth; XOR gate chip MC10EP08 pin VEE ground; XOR gate MC10EP08 output pin
Connection One end of the thirty-second resistor R32, one end of the thirty-third resistor R33; MC10EP08 XOR gate chip output pin Q is connected to the output signal Sj; seventeenth other end of capacitor C17, capacitor C18, the other end of the eighteenth ground; Twenty other end of resistor R24, the twenty-sixth the other end of the resistor R26, 28, the other end of the resistor R28, thirty resistor R30, the thirty-second resistor R32 and the other end +5 V ; the twenty-fifth the other end of resistor R25, 27 and the other end of the resistor R27, 29 and the other end of the resistor R29, the R31 resistor thirty other end;
Described the 3rd delayer comprises the 19 capacitor C the 19, the 20 capacitor C the 20, the 34 resistance R the 34, the 35 resistance R the 35, the 36 resistance R the 36, the 37 resistance R the 37, the 38 resistance R the 38, the 39 resistance R 39, the 3rd delayer chip MC10EP195-3;
Third delay chip MC10EP195-3 pin
Connect the input signal
, the thirty-fourth resistor R34 at one end, the end of the thirty-fifth resistor R35; third delay chip MC10EP195- 3 IN connector pin input signal Sd, one end of the thirty-sixth resistor R36, one end of the thirty-seventh resistor R37; third delay chip MC10EP195-3 output pin
Connection thirty-eighth One end of resistor R38, one end of the thirty-ninth resistor R39; third delay chip MC10EP195-3 output pin Q is connected to the output signal Sk; third delay chip MC10EP195-3 pin VCC is connected +5 V, tenth nine capacitor C19 to one end of one end of twenty capacitor C20; third delay MC10EP195-3 chip pins SETMAX,? SETMIN, LEN, VEE ground; third delay MC10EP195-3 chip and pin pin VCF VEF short circuit, the third delay C10EP195-3 chip pins D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10 ground; third delay MC10EP195-3 of the other pins unconnected ; the thirty-fourth resistor R34 the other end of Article 36, the other end of the resistor R36, 38th resistor R38 and the other end +5 V; thirty-fifth the other end of the resistor R35, the thirty-seventh resistor R37 The other end of Article 39, the other end of resistor R39; nineteenth other end of the capacitor C19, the other twenty-grounded capacitor C20.
6. high frequency phase shift signalling generation circuit according to claim 1 is characterized in that: described first digital frequency divider comprises the 21 capacitor C the 21, the 22 capacitor C the 22, the 23 capacitor C the 23, the 24 capacitor C the 24, the 25 capacitor C the 25, the 40 resistance R the 40, the 41 resistance R the 41, the 42 resistance R the 42, the 43 resistance R the 43, the 44 resistance R 44, the first digital frequency divider chip SP8402-1;
Two input pin CLKIN short circuits of the first digital frequency divider chip SP8402-1 and connect input signal Sk, an end of the 40 resistance R 40, an end of the 41 resistance R 41; Two input pins of the first digital frequency divider chip SP8402-1
short circuit and connect an end of the 21 capacitor C 21, an end of the 22 capacitor C 22; The output pin of the first digital frequency divider chip SP8402-1
connects an end of the 42 resistance R 42;
The output pin OUTPUT of the first digital frequency divider chip SP8402-1 connects an end of the 25 capacitor C 25, an end of the 43 resistance R 43; The pin VCC of the first digital frequency divider chip SP8402-1 all connects+5V, an end of the 23 capacitor C 23, an end of the 24 capacitor C 24; The pin GND ground connection of the first digital frequency divider chip SP8402-1; The pin S0 of the first digital frequency divider chip SP8402-1, S1, S2 connect 3,2,1 pin of switch SW ITCH-6 respectively; The other end of the 21 capacitor C 21, the other end of the 22 capacitor C 22, the other end of the 23 capacitor C 23, the other end ground connection of the 24 capacitor C 24; Other end connection+the 5V of the 40 resistance R 40; 4,5,6 pins of switch SW ITCH-6 connect+5V; One end of the other end of the 25 capacitor C 25, the 44 resistance R 44 connects output signal S1; The other end ground connection of the other end of the 41 resistance R 41, the 42 resistance R 42 other ends, the 43 resistance R 43 other ends, the 44 resistance R 44;
The described second digital frequency divider chip comprises the 26 capacitor C the 26, the 27 capacitor C the 27, the 28 capacitor C the 28, the 29 capacitor C the 29, the 30 capacitor C the 30, the 45 resistance R the 45, the 46 resistance R the 46, the 47 resistance R the 47, the 48 resistance R the 48, the 49 resistance R 49, the second digital frequency divider chip SP8402-2;
Two input pin CLKIN short circuits of the second digital frequency divider chip SP8402-2 and connect input signal Se, an end of the 45 resistance R 45, an end of the 46 resistance R 46; Two input pins of the second digital frequency divider chip SP8402-2
short circuit and connect an end of the 26 capacitor C 26, an end of the 27 capacitor C 27; The output pin of the second digital frequency divider chip SP8402-2
connects an end of the 47 resistance R 47; The output pin OUTPUT of the second digital frequency divider chip SP8402-2 connects an end of the 30 capacitor C 30, an end of the 48 resistance R 48; The pin VCC of the second digital frequency divider chip SP8402-2 all connects+5V, an end of the 28 capacitor C 28, an end of the 29 capacitor C 29; The pin GND ground connection of the second digital frequency divider chip SP8402-2; The pin S0 of the second digital frequency divider chip SP8402-2, S1, S2 connect 3,2,1 pin of switch SW ITCH-7 respectively; The other end of the 26 capacitor C 26, the other end of the 27 capacitor C 27, the other end of the 28 capacitor C 28, the other end ground connection of the 29 capacitor C 29; Other end connection+the 5V of the 45 resistance R 45; 4,5,6 pins of switch SW ITCH-7 connect+5V; The one termination output signal S2 of the other end of the 30 capacitor C 30, the 49 resistance R 49; The other end ground connection of the other end of the 46 resistance R 46, the other end of the 47 resistance R 47, the 48 resistance R 48 other ends, the 49 resistance R 49.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210141411.3A CN102664625B (en) | 2012-05-08 | 2012-05-08 | Programmable ECL (emitter coupled logic) device based high-frequency phase shift signal generation circuit |
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|---|---|---|---|
| CN201210141411.3A CN102664625B (en) | 2012-05-08 | 2012-05-08 | Programmable ECL (emitter coupled logic) device based high-frequency phase shift signal generation circuit |
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| CN102664625B CN102664625B (en) | 2014-06-18 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109905103A (en) * | 2019-02-22 | 2019-06-18 | 西安交通大学 | A kind of stretch circuit combining digital logical operation based on delay |
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| US5230013A (en) * | 1992-04-06 | 1993-07-20 | Motorola, Inc. | PLL-based precision phase shifting at CMOS levels |
| JPH09186564A (en) * | 1995-10-02 | 1997-07-15 | Northern Telecom Ltd | Cmos digital control clm/ecl clock phase shifter |
| US5945860A (en) * | 1996-01-04 | 1999-08-31 | Northern Telecom Limited | CLM/ECL clock phase shifter with CMOS digital control |
| CN1467913A (en) * | 2002-06-19 | 2004-01-14 | 阿尔卡塔尔公司 | Differential high speed cmos to ecl logic converter |
| CN101179263A (en) * | 2007-11-29 | 2008-05-14 | 江南大学 | Digital type pulse fixed lead time shift circuit |
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2012
- 2012-05-08 CN CN201210141411.3A patent/CN102664625B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5230013A (en) * | 1992-04-06 | 1993-07-20 | Motorola, Inc. | PLL-based precision phase shifting at CMOS levels |
| JPH09186564A (en) * | 1995-10-02 | 1997-07-15 | Northern Telecom Ltd | Cmos digital control clm/ecl clock phase shifter |
| US5945860A (en) * | 1996-01-04 | 1999-08-31 | Northern Telecom Limited | CLM/ECL clock phase shifter with CMOS digital control |
| CN1467913A (en) * | 2002-06-19 | 2004-01-14 | 阿尔卡塔尔公司 | Differential high speed cmos to ecl logic converter |
| CN101179263A (en) * | 2007-11-29 | 2008-05-14 | 江南大学 | Digital type pulse fixed lead time shift circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109905103A (en) * | 2019-02-22 | 2019-06-18 | 西安交通大学 | A kind of stretch circuit combining digital logical operation based on delay |
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