JPH09186564A - Cmos digital control clm/ecl clock phase shifter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a current-mode logic/emitter-coupled logic(CML/ECL) clock phase shifter generating a desired phase in response to a control signal which provides a 360 deg. of phase control range and receives two CML clock signals with a known phase difference. SOLUTION: The phase shifter employs a CMOS current switch 10 generating a current signal with an amplitude adjusted by a digital control signal. A differential pair devices provide an amplitude-modulated current signal to an input clock and an input clock modified signal. Two MOS transmission networks invert selectively each amplitude-modulated signal and sums signals from each side of a load network. The phase control resolution is optimum over four quadrants of an orthogonal phase input clock signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase shift circuit, and more particularly to a CMOS digital control CLM / ECL.
It relates to a phase shifter. Where CML is curren
t-mode logic means current mode logic. Also, EC
L means emitter-coupled logic.

[0002]

BACKGROUND OF THE INVENTION It is sometimes necessary to generate clock signals that are phase shifted. Two examples are a timing recovery circuit and a delay locked loop. Conventional clock phase shift circuits are based on cascaded delay cells, variable delay cells, or mixing circuits. In the latter case, the output of the phase shift control is an analog signal that is easily affected by noise and crosstalk. In this case, digital control can be performed by using a digital / analog converter.

[0003]

CMOS and CML
If the / ECL technology is used in some devices, a converter or resistor network is required to convert the CMOS control signals to the CML / ECL format. With such a circuit, the circuit becomes more complex and the power loss increases. Moreover, the phase control range of the mixed clock phase shift circuit is typically limited to 90 °. CMOS and CML / ECL technologies are currently used in the same integrated circuit, and efforts are being made to reduce power loss and improve performance. Therefore, CML
In the / ECL circuit, especially in the high-speed logic circuit, it is necessary to make the CMOS signal function as a control signal.

The present invention is a CM that completely or partially solves the conventional phase shifter drawback.
Mixer-based CML / E with OS digital control
It is an object to provide a CL clock phase shifter.

Further, the CMOS control signal is sent to the CML / EC.
CMOS digitally controlled CML / E without converter or resistor network to convert to L format
An object is to provide a CL phase shifter.

The device of the present invention does not require complementary inputs and reference signals combining high speed CML / ECL logic signals with low speed single ended CMOS control signals.
CM using complementary MOS current source with adjustable current output
Use L / ECL device.

Another object of the present invention is to provide a clock phase shifter which outputs an output clock having a phase that can be programmed to take any value between 0 ° and 360 °.

The phase shifter according to the present invention provides a 360 ° phase control range and operates under the control of CMOS digital words. The device, when given two CML clock signals with a known fixed phase difference, produces the desired phase in response to a digital control signal. The phase control resolution is optimal and comparable for the four quadrants of the quadrature input clock signal.

Another object of the invention is to introduce a mixer-based clock phase shifter in a very compact manner.

An important advantage of the programmable phase shifter according to the invention is that it is compatible with different types of signals. The programmable features of this circuit are implemented by using a hybrid CML-CMOS multiplexer block. This hybrid CML-C
The MOS multiplexer block allows the CMOS supervisory logic block to interface directly to the high speed CML signal path. To achieve this, CMO
No S / CML converter is required, and therefore, the device formation area and power loss can be significantly reduced. Moreover, this circuitry does not affect the high frequency operation of the CML signal path. This approach can be used for other types of signals.

Another advantage of the present invention is that the phase of the finally reproduced clock can be adjusted to obtain an output range of 0 ° to 360 °.

[0012]

A CMOS digital control CLM / ECL clock phase shifter of the present invention provides a first current to a first node and a second current to a first node according to a control digital signal.
A current switch for applying a second current to the node of the high speed signal and the first current, and amplitude-modulating the high speed signal with the first current, and selectively modulating the modulated high speed signal to the first and second The first differential block leading to the route, the high-speed signal and the modified signal of the high-speed signal having a known fixed phase difference and the second current are received, and the high-speed modified signal is amplitude-modulated by the second current and modulated. A second differential block for selectively directing the high speed modified signal to the third and fourth routes, and connecting the first and second routes to the first and second summing nodes according to the control digital signal. And a first transmission circuit for controlling the third and fourth routes according to the control digital signal.
A second transmission circuit connected to the summing node and the second summing node, and to the first and second summing nodes,
And a load network that provides a high speed output signal in the 360 ° phase control range.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is a block diagram of a phase shifter according to the present invention. The current switch 10 is connected to the first differential block 12 and the second differential block 14, and the first current is supplied to the node A and the second current is supplied to the node B. The amplitude of the output current at points A and B is 7
Depending on the digital words d _{0 to} d _k . CMO
Due to the configuration of the S current switch 10, as the amplitude of the current on path A increases, the amplitude of the current on path B similarly decreases, and when the amplitude of the current on node A decreases, the node B increases.
The amplitude of the current at is similarly mirrored to increase.

The first differential block 12 is a CML / EC.
More specifically, the L high-speed clock signal I ₁ (hereinafter, also referred to as a high-speed signal or a clock signal) receives the input signal I _p1 and its inverted signal I _n1 (I ₁ = I _p1 + I _n1 ). Second
Of the differential block 14 is a modified signal I of the high-speed clock signal.
₂ (high-speed clock signal having a predetermined fixed phase difference from the high-speed clock signal I ₁ , hereinafter also referred to as high-speed signal or clock signal), that is, the input signal I _p2 and its inverted signal I _n2 (I ₂ = I _p2 + I _n2 ) is received. High speed signal I
₁ and the modified signal I ₂ of the high-speed signal have a known fixed phase relationship. Although in the disclosed and illustrated embodiment a quadrature clock signal is used, the input clocks I ₁ and I ₂ need not be in quadrature, and other phase relationships may be used. It is obvious to a person skilled in the art that it is possible.

Block 12 amplitude-modulates the input clock signals I _p1 and I _n1 with the current at node A and provides the modulated modulation signal on routes 16 and 18. Route 1
6 has the same phase as the signal I _p1 and transmits a signal A _p1 having an amplitude corresponding to the amplitude of the current at the node A. The modulated signal A _n1 on the route 18 is in phase with the signal I _n1 and has an amplitude corresponding to the amplitude of the current at the node A.

Similarly, block 14 amplitude modulates the input quadrature clocks I _p2 and I _n2 with the current at node B,
The modulated quadrature clock signal is provided on output routes 20 and 22. The output route 20 has the same phase as the signal I _p2 and has a modulation signal B having an amplitude corresponding to the amplitude of the current of the node B.
Transmit _p2 . On the other hand, the modulated signal B _{n2 on} the route 22 has the same phase as the signal I _n2 and has an amplitude corresponding to the amplitude of the current at the node B. In this way, the amplitude modulated clock signal I ₁
And I ₂ are available at the output of the differential pair transistors, both polarities and mirror amplitudes.

For example, signal A _p1 is available on route 16 when I _p1 is present at the input of differential pair transistor 12. At the same time, the signal B _p2 is a modified signal of I _p1 and is obtained at the route 20 as I _p2 existing at the input terminal of the differential pair transistor 14. The sum of the normalized amplitudes of signals A _p1 and B _p2 on routes 18 and 22 is a unit value. Similarly, the sum of the normalized amplitudes of signals A _n1 and B _n2 on routes 18 and 22 is also a unit value.

The two transmitter circuits 24 and 26 reconfigure the signal path of the mixer differential pair transistors using the quadrant decision signals q _A and q _B. The amplitude modulation signals A _p1 and A _n1 output by the differential pair transistor 12 are input to the first transmission circuit 24, and the amplitude modulation signals B _p2 and B _n2 output by the differential pair transistor 14 are input by the second transmission circuit 24. It is input to the circuit 26. Transmitter circuits 24 and 26 selectively invert each modulated signal and add nodes 34 and 36.
Operates to sum the differential signals in each of the
According to the values of the quadrant signals q _A and q _B , a 360 ° phase control range is covered. In fact, the sum is determined by the load network 31, which is a simple resistance network.

FIG. 2 and Table 1 show quadrant signals q _A and q _B.
4 shows changes in output clock phase for various values of. Output signal O _p ~ O _n is determined by combining the phasor _{(O 1 + O 3) ~} (O 2 + O 4).

[0020]

[Table 1]

The phasors labeled O _p and O _n shown in FIG. 2 have amplitudes determined by the current values at nodes A and B, and the amplitude and phase of O _p and O _n are the output signals. It is obvious to a person skilled in the art to determine the phase of O (O = O _p + O _n ).

The angle θ of the output signal O is determined by the relationship between the amplitudes of the two component phasors in the quadrant and the signals q _A and q _B determine the quadrant of the phase of the output clock signal.

As shown in FIGS. 1 and 2 and Table 1, in order to obtain the recovered clock signal in the first quadrant I,
Both q _A and q _B must be a logical “0”.
As is apparent from FIGS. 1 and 2, the signal at node 34 consists of differential signals A _p1 and B _p2 and node 36
The signal at is composed of the signals A _n1 and B _n2 . The output signal O between nodes 34 and 36 is (A _p1 + B _p2 ) − (A
_{n1 + B n2) = (A} p1 -A n1) + (B p2 -B n2) = O p + O n
It is. There are 0 DEG DEG 90 the phase angle of the output signal O _p and O _n, has an amplitude respectively set as the current A and B. As shown in FIG. 2, the phase angle θ1 of the output signal O ₁ obtained by adding O _p1 and O _n1 is between 0 ° and 90 °. This phase angle can be changed by changing the amplitude of the input clock signal which affects the final clock signal. For example, for phasor pairs O _n2 and O _p2 , different phase angles θ
2 is obtained and the output clock is O ₂ .

When the signal O _n is positive and O _p is negative, the phase angle of its output signal O is between 90 ° and 180 ° and is determined by the amplitude of the current at nodes A and B. In this case, q _A must be a logic “0” and q _B must be a logic “1” when the output clock is in the second quadrant (II).

For the output clock in quadrant III,
Both q _A and q _B will be a logical “1”. In this case, the phase of the output signal O changes between 180 ° and 270 °,
It is determined by the amplitude of the signal O _p ~ O _n.

To obtain the output clock in quadrant IV,
q _A becomes a logic “1” and q _B becomes a logic “0”. Signal O _p is a positive, Q _n is negative, each phase 27
0 ° and 0 °, that is, 360 °. These signals are each modulated by the currents at nodes A and B in the differential pair transistors. The phase of the output clock O can be varied between 270 ° and 360 ° by varying the amplitude of the differential signal applied to the load network.

The load network 31 is connected between the summing node 34 and 36, as described above, in accordance with digital control signals d ₀ to d _k, adds the differential signal for setting the phase of the output signal O _p and O _n .

FIG. 3 is an electric circuit diagram of an embodiment of the present invention.
Shown in CMOS current is switched from the SW ₀ to SW _m parallel-connected CMOS pair to SW _'0 ~SW' _m. The operation of the switch will be described later in more detail with reference to FIGS. 4 and 5. Three current sources 11, 13 and 15
Are CMOS pairs SW ₀ -SW ' ₀ , SW ₁ -S, respectively.
W _'1, SW ₃ -SW' is connected to the ₃ series, supplies a weighted current A and B. For example, the current source 11 supplies a current weighted by the coefficient e _{0 at the} node A or B according to the level of the signal d ₀ .

Similarly, the current source 13 supplies a current weighted by the coefficient e _{1 at the} node A or B according to the level of the signal d ₁ . The current source 15 is
Depending on the level of the signal d ₂ , it supplies at node A or B a current weighted by a factor e ₂ . FIG.
And nodes A and B as described above with reference to FIG.
The value of the current at determines the phase of the output signal. It will be apparent to those skilled in the art that the number of current sources used in the phase shifter can be selected depending on the application, as will be described in more detail below with reference to FIGS. 4 and 5. The number of current sources can be increased to increase the resolution of the phase angle.

It is also clear that the k-th digit of the control word is selected according to the number of current sources and the quadrant signal is preferably part of the control word.

The first differential pair transistor 12 comprises bipolar transistors Q1 and Q2 used to modulate the input clock signals I _p1 and I _n1 with the current A, and outputs at the outputs 16 and 18 the modulation signals A _p1 and Supply A _n1 . The second differential pair transistor 14 comprises bipolar transistors Q3 and Q4 used to modulate the input clock signals I _p2 and I _n2 with the current B, and outputs the modulation signals B _p2 and B _n2 to the outputs 20 and 22. Supply.

The amplitude of the modulation signals A _p1 , A _n1 , B _p2 and B _n2 output by the differential pair transistors 12 and 14 is determined using a CMOS logic control current switch connected to the emitter node of the differential pair transistors. Controlled.

The first transmission circuit 24 includes a transistor Q5
And a first CMOS pair 21 consisting of Q6 and a second CMOS pair 23 consisting of transistors Q7 and Q8.
Consists of In each CMOS pair, the drain is
Commonly connected to receive the collector current of one of the differential pair transistors. Thus, the drain of the first CMOS pair 21 is connected to the collector of the transistor Q1 and the drain of the second CMOS pair 23 is connected to the collector of the transistor Q2. The sources of transistors Q5 and Q7 are connected to node 34, and the sources of transistors Q6 and Q8 are connected to node 36.
Connected to.

The control terminals (gates) of the transistors Q5 and Q8 are commonly connected to receive the quadrant signal q _A , and the control terminals of the transistors Q6 and Q7 are commonly connected to receive the inverted signal of q _A. Inverter 3
7 is a transistor Q5 and Q8 is a transistor Q
It is used to provide the opposite of the 6 and Q7 states.

When q _A is high, Q5 and Q8 are "off" and Q6 and Q7 are "on". Modulated signal A _p1 is obtained at summing node 34 through transistors Q2 and Q7, and modulated signal A _n1 is summed node 36.
Is obtained. Therefore, the output signal O ₂ is obtained through the transistors Q1 and Q6 along the first track (T1) formed between the node A and the summing node 36.

When q _A is low, Q5 and Q8 are "on" and Q6 and Q7 are "off". A
_p1 is available at summing node 34 through transistors Q1 and Q5, while A _n1 is available at summing node 36 through transistors Q2 and Q8.

The second transmission circuit 26 comprises CMOS pairs 25 and 27 controlled by the quadrant signal q _B. CMOS
As in the case of pair 21 and 23, the drains of transistors Q9 and Q10 are commonly connected to the collector of transistor Q3, and the drains of transistors Q11 and Q12 are commonly connected to the collector of transistor Q4. The sources of transistors Q9 and Q11 are connected to summing node 34, and the sources of transistors Q11 and Q12 are connected to summing node 36.

The control terminals (gates) of transistors Q9 and Q12 are commonly connected to receive quadrant signal q _B , and the control terminals of transistors Q10 and Q11 are commonly connected to receive an inverted signal of q _B. Inverter 38 is used to cause transistors Q10 and Q11 to turn on when transistors Q9 and Q12 are "off."

When q _B is high, transistors Q9 and Q12 are "off" and Q10 and Q11 are "on". Signal B _p2 is _generated by transistors Q3 and Q10.
Given to the summing node 36 through the signal B _n2 is obtained summing node 36 through transistors Q4 and Q11.

When q _B is low, transistors Q9 and Q12 are "on" and transistors Q10 and Q11 are "off". Signal B _p2 is transistor Q3
And the signal B _n2 obtained at the addition node 34 through Q9.
Is a summing node 3 through transistors Q4 and Q12.
6 is obtained.

The signals output by the transmission circuits 24 and 26 are added in the load resistors R1 and R2. The capacitor C is provided for filtering and removes high frequency components. The resulting output signal O _p and O _n is sent to the limiter amplifier 39 to generate a square wave clock output.

A basic current switch 40 that can be used in the CMOS current switch 10 is shown in FIG. This circuit is disclosed in U.S. Pat. No. 5,420,529 (Inventor Guay et al., Registration date March 30, 1995, applicant Northern Telecom Limited).

The basic current switch 40 is composed of an NMOS transistor 41 and a PMOS transistor 42. Gates G1 and G2 of the NMOS transistor 41 and the PMOS transistor 42 are connected to the node 43 and receive the digital control signal d. The source S1 of the NMOS transistor 41 and the drain D2 of the PMOS transistor 42 are connected to the node 44 and the constant current source 45.
Connected to. The current source 45 has the other end connected to the negative supply rail. The negative supply rail may be grounded as shown, but this is not essential. It is clear that the current source can be constituted by any current source circuit, which will be obvious to a person skilled in the art.

As shown by the broken line in FIG.
The substrate of transistor 41 is connected to V _SS or node 44, and the substrate of PMOS transistor 42 is connected to Vdd or source S2. The exact construction depicted here is not critical to the invention. Other connections may be used. The drain D1 is connected to the node A and the source S2 is connected to the node B.

The basic current switch 40 requires a single input and does not require complementary inputs or reference levels. The signal d is a CMOS input control signal.

During operation, the current from current source 45
Depending on the input signal d provided at 3, it is routed either to the path between node A and ground or between node B and ground. When the input voltage d is low, the NMOS transistor 41 is “off”, the PMOS transistor 42 is “on”, and the current generated by the current source 45 flows to the node B. When the input voltage d is high, the NMOS transistor 41 is “on” and the PMOS transistor 42 is “off”. The output current generated by the constant current source 45 flows from node A to ground.

The operating region of the complementary MOS transistor is
It is determined by the circuit added to nodes A and B. The drain-source voltage of the complementary MOS transistor in the "on" state is selected to be small enough to hold the current source in its high impedance region.

FIG. 5 is a block diagram of the CMOS current switch 10 used in the present invention. When a plurality of current switches of the type shown in FIG. 4 are connected in parallel, the current value can be adjusted. The value of the output current of the node A can be preset by means of the digital words d _{0 to} d _n , which determines which current switch constitutes this circuit.

A current source that receives a logic "1" forms the current at node A, and a current source that receives a logic "0" forms the current at node B. For example, if a 4-digit control signal d ₀ = 1, d ₁ = 0, d ₂ = 1 and d ₃ = 1 is applied to the bus 7, the current of the node A is caused by SW ₀ , SW ₂ and SW ₃ . Is supplied by the current, and the current of node B is supplied by the current by SW ₁ .

By giving different weights to SW _{0 to} SW _n , the current value of the node A can be selected with a wide range. A current switch with a weighted current level can be used, each providing a binary incremented current value. For example, the current source 51
Can be chosen to have weights e ₀ , current source 52 to weight e ₁ , current source 53 to weight e ₂ , and current source 54 to weight e _k . Here, k is the number of current sources minus one.

FIG. 6 is a diagram generally showing a configuration diagram of an example in which the phase shifter of the present invention is applied to a clock recovery circuit. As can be seen from FIG. 1, the phase shifter 1 is connected to the output terminal of the clock recovery PLL block 2 and operates with the PLL output clock and its quadrature phase component. The phase shifter 1 is
The inputs 3 and 4 receive the clock output I and the quadrature clock Q, respectively. Output Clock O _p and O _n obtained at a terminal 5, and 6 are phase-controlled by a digital control signal d ₀ to d _n which is supplied to the terminal 7.

FIG. 7 is an oscilloscope waveform showing the influence on the phase shifter by changing the control word, which is measured using the "residual characteristic" display mode. The clock is operating at 200 MHz and the phase shifter used has 8-bit resolution, ie q _A and q _B have 2-bit resolution and weighting currents A and B have 6-bit resolution.

The step size of about 200 ps shown in FIG. 7 is obtained by changing the fourth least significant bit. Approximately 5 ps even if the least significant bit is toggled
It only changes. This is smaller than the resolution of an oscilloscope that displays precisely.

While particular embodiments of the present invention have been illustrated and described, it will be obvious to those skilled in the art that various applications and choices can be made to the invention. However, such applications and choices are within the scope of the present invention.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a clock phase shift circuit of the present invention.

FIG. 2 is a diagram showing a change in an output clock phase according to an amplitude of an input clock signal.

FIG. 3 is a schematic diagram of the circuit of FIG.

FIG. 4 is a schematic diagram of a conventional current switching circuit.

FIG. 5 is a configuration diagram of a variable current switching circuit according to the present invention.

FIG. 6 is a configuration diagram of a clock recovery circuit using the clock phase shifter of the present invention.

FIG. 7 is a graph showing the output voltage for various values of the control signal on the time axis.

[Explanation of symbols]

1 ... Phase shifter, 2 ... Clock recovery PLL block, 3,
4, 7 ... Input end, 5, 6 ... Output end, 10 ... CMOS current switch, 40 ... Basic current switch, 11, 13, 15
Current source, 12 ... First differential block, 14 ... Second differential block, 16, 18 ... Route, 20, 22 ... Route, 21, 23 ... CMOS pair, 24 ... First transmission circuit,
26 ... 2nd transmission circuit, 25, 27 ... CMOS pair, 31
... load network, 34, 36 ... addition node, 37,
38 ... Inverter, 39 ... Limiter amplifier, 51, 52,
53, 54 ... current source, C ... Capacitor, d ₀ to d _k ... digital words, Q1, Q2, Q3, Q4 , Q5, Q6, Q
7, Q8, Q11, Q12 ... Transistors, R1, R2
…Load resistance

Front Page Continuation (72) Inventor Bernard Guy Canada, H3J, 2W5, Quebec, Montreal, Rufus-Rockhead # 203, 2625 (72) Inventor Michael Altman Canada, K2L, 2 Kei 1, Ontario, Kanata, Barlow Crescent 12

Claims (18)

[Claims] 1. In a CMOS digital control CLM / ECL clock phase shifter for changing the phase of a high speed signal in a 360 ° phase control range: a first current is applied to a first node and a second node is applied according to a control digital signal. A current switch for applying a second current to the high speed signal and the first current, and amplitude-modulates the high speed signal with the first current to selectively output the modulated high speed signal to the first and the second currents. A first differential block leading to a second route, a modified signal of the high speed signal having a known fixed phase difference from the high speed signal, and the second current, and receiving the high speed modified signal as the second current A second differential block which is amplitude-modulated by means of, and selectively guides the modulated high-speed modified signal to third and fourth routes, and the first and second differential blocks in accordance with the control digital signal.
A first transmitting circuit connecting the root of the above to the first addition node and the second addition node, and the third and fourth transmission circuits according to the control digital signal.
And a second transmitting circuit for connecting the root of the above to the first and second adding nodes, and for supplying a high-speed output signal in the phase control range of 360 °, which is connected to the first and second adding nodes. A CMOS digital control CLM / ECL clock phase shifter comprising a load network. 2. A CMOS digitally controlled CLM / ECL clock phase shifter according to claim 1, wherein said first differential block comprises: an emitter connected to said first node and said first and second respectively. First and second semiconductor devices having collectors connected to the root; means for applying the high-speed signal to the base of the first semiconductor device; and an inverted signal of the high-speed signal to the base of the second semiconductor device. CM comprising means for giving
OS digital control CLM / ECL clock phase shifter. 3. The CMOS digitally controlled CLM / ECL clock phase shifter of claim 1, wherein the second differential block comprises: an emitter connected to the second node and first and second routes, respectively. Third and fourth semiconductor devices having collectors connected to each other, means for applying the high-speed signal to the base of the third semiconductor device, and an inverted signal of the high-speed signal to the base of the fourth semiconductor device. CM comprising means for giving
OS digital control CLM / ECL clock phase shifter. 4. The CMOS digital control CLM / ECL clock phase shifter according to claim 1, wherein the first transmission circuit has: a common terminal on the first route and an output terminal on the first and second sides, respectively. Connected to the summing node of
A first switch for switching the modulated high-speed signal and an inverted signal of the modulated high-speed signal between the first and second summing nodes according to a first quadrant digit of the control digital signal; Is connected to the second route and output terminals are connected to the first and second summing nodes, respectively, and the modulated high-speed modified signal and the modulated high-speed signal are generated according to an inverted signal of the first quadrant digit. A second switch for switching the inversion signal of the second switch between the first and second addition nodes.
S Digitally controlled CLM / ECL clock phase shifter. 5. The CMOS digital control CLM / ECL clock phase shifter according to claim 4, wherein the first switch includes a drain commonly connected to the first route and the first and second drains, respectively. A CMOS digitally controlled CLM / ECL clock phase shifter comprising a pair of CMOS transistors having a source connected to a summing node and a gate connected to receive the first quadrant digit. 6. The CMOS digital control CLM / ECL clock phase shifter according to claim 4, wherein the second switch has a drain commonly connected to the second route, and a first and a second addition, respectively. A CMOS digital control CLM / ECL clock phase shifter comprising a pair of CMOS transistors having a source connected to a node and a source connected to receive the first inverted signal quadrant digit. . 7. The CMOS digital control CLM / ECL clock phase shifter according to claim 1, wherein the second transmission circuit has: a common terminal on the third route and an output terminal on the first and second sides, respectively. Connected to the summing node of
A third switch for switching the modulated high speed modified signal and an inverted signal of the modulated high speed modified signal between the first and second summing nodes according to a second quadrant digit of the control digital signal; A common terminal is connected to the fourth route and output terminals are connected to the first and second summing nodes, respectively, and the modulated high-speed modified signal and the modulated high-speed signal are output according to the second inverted signal quadrant digit. A CMO comprising a fourth switch for switching an inversion signal of the modified signal between the first and second addition nodes.
S Digitally controlled CLM / ECL clock phase shifter. 8. The CMOS digital control CLM / ECL clock phase shifter according to claim 7, wherein the third switch includes a drain commonly connected to the third route, and the first and second drains, respectively. A CMOS digitally controlled CLM / ECL clock phase shifter comprising a pair of CMOS transistors having a source connected to a summing node and a gate connected to receive the second quadrant digit. 9. The CMOS digital control CLM / ECL clock phase shifter according to claim 7, wherein the fourth switch has a drain both connected to the fourth route, and the first and second drains, respectively. A pair of CMOs having a source connected to a summing node and a gate connected to receive the second inverted signal quadrant digit.
CMO characterized by being composed of S-transistors
S Digitally controlled CLM / ECL clock phase shifter. 10. The CMOS digital control CLM / ECL clock phase shifter of claim 1, wherein the load network is: a first resistor connected between the first summing node and a power supply terminal; A CMO comprising a second resistor connected between a second summing node and the power supply terminal.
S Digitally controlled CLM / ECL clock phase shifter. 11. The CMOS digital control CLM / ECL clock phase shifter according to claim 1, wherein the current switch includes: a current source for supplying a control current to a common node, and a pair of CMOS transistors including an NMOS transistor and a PMOS transistor. A source of the NMOS transistor and the PMOS
The drains of the transistors are commonly connected to a corresponding current source, the gates of the MOS transistors receive the digit of the control signal, the drains of the NMOS transistors are commonly connected to a first node, and the sources of the PMOS transistors are second. CMOS digital control C, which is commonly connected to the first node and the second current and leads the first and second currents to the first and second nodes, respectively.
LM / ECL clock phase shifter. 12. The CMOS digitally controlled CLM / ECL clock phase shifter of claim 1, wherein the current switches are: k current sources each supplying a control current to each kth common node, and an NMOS transistor. And a pair of CMOS transistors k consisting of a PMOS transistor, each source of the NMOS transistor and the PMO.
The drains of the S transistors are commonly connected to the corresponding kth common node, the gates of the MOS transistors receive the digit of the control signal, and the drains of the NMOS transistors are commonly connected to the first node. The sources of the transistors are commonly connected to a second node, and lead a component current to the first node and a complementary component current to the second node according to the kth digit. Control C
LM / ECL clock phase shifter. 13. The CMOS digitally controlled CLM / ECL clock phase shifter of claim 12, wherein the sum of the component currents from the k CMOS transistor pairs forms the first current, and the k currents. CMOS digitally controlled CLM / ECL clock phase shifter, wherein the complementary component currents from the pair of CMOS transistors form the second current. 14. The CMOS digital control CLM / ECL clock phase shifter according to claim 13, wherein:
And a CMOS digital control CLM / ECL clock phase shifter, wherein the sum of the normalized amplitudes of the first and second currents obtained at the second node is equal to a unit value. 15. In a CMOS digitally controlled CLM / ECL clock phase shifter for changing the phase of a high speed signal in a 360 ° phase control range: a first current at a first node,
Means for applying a second current to a second node and adjusting the amplitudes of the first and second currents according to a control digital signal; receiving the high speed signal and the first current; A first differential block that amplitude-modulates with a first current and selectively guides the modulated high-speed signal to first and second routes; and the high-speed signal having a known fixed phase difference from the high-speed signal. The second high-speed modified signal is amplitude-modulated by the second current, and the modulated high-speed modified signal is selectively guided to the third and fourth routes.
Differential block, and the first and second differential digital signals according to the control digital signal.
A first transmitting circuit for connecting the respective routes to the first adding node and the second adding node respectively, and the third and fourth transmitting circuits according to the control digital signal.
A second transmission circuit for connecting the respective routes to the first addition node and the second addition node, respectively, and a phase control range of 360 ° for a high-speed output signal, which is connected to the first and second addition nodes. A CMOS digital control CLM / ECL clock phase shifter comprising: 16. The CMOS digital control CLM / ECL clock phase shifter according to claim 14, wherein:
And the sum of the normalized amplitudes of the second current is equal to the unit value CMOS digital control CLM / E
CL clock phase shifter. 17. The CMOS digital control CLM / ECL clock phase shifter according to claim 15, further comprising:
CMOS digital control CLM / characterized by comprising a current source for generating the first and second currents
ECL clock phase shifter. 18. The CMOS digital control CLM / ECL clock phase shifter according to claim 2, wherein the first and second semiconductor devices are bipolar transistors.
CL clock phase shifter.