CN102656673B - 晶片结构的电耦合 - Google Patents

晶片结构的电耦合 Download PDF

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Publication number
CN102656673B
CN102656673B CN201080056932.8A CN201080056932A CN102656673B CN 102656673 B CN102656673 B CN 102656673B CN 201080056932 A CN201080056932 A CN 201080056932A CN 102656673 B CN102656673 B CN 102656673B
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CN
China
Prior art keywords
wafer
opening
width
conductive
lid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201080056932.8A
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English (en)
Chinese (zh)
Other versions
CN102656673A (zh
Inventor
刘连军
L·H·卡尔林
A·J·马格纳斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
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Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN102656673A publication Critical patent/CN102656673A/zh
Application granted granted Critical
Publication of CN102656673B publication Critical patent/CN102656673B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/007—Interconnections between the MEMS and external electrical signals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H10W42/261—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their shapes or dispositions
    • H10W42/276—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their shapes or dispositions the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/60—Seals
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/09—Packages
    • B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
    • B81B2207/097—Interconnects arranged on the substrate or the lid, and covered by the package seal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/17—Containers or parts thereof characterised by their materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/17—Containers or parts thereof characterised by their materials
    • H10W76/18—Insulating materials, e.g. resins, glasses or ceramics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W95/00—Packaging processes not covered by the other groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Micromachines (AREA)
  • Dicing (AREA)
CN201080056932.8A 2009-12-15 2010-11-22 晶片结构的电耦合 Expired - Fee Related CN102656673B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/638,424 2009-12-15
US12/638,424 US8138062B2 (en) 2009-12-15 2009-12-15 Electrical coupling of wafer structures
PCT/US2010/057624 WO2011081741A2 (en) 2009-12-15 2010-11-22 Electrical coupling of wafer structures

Publications (2)

Publication Number Publication Date
CN102656673A CN102656673A (zh) 2012-09-05
CN102656673B true CN102656673B (zh) 2015-05-20

Family

ID=44143393

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201080056932.8A Expired - Fee Related CN102656673B (zh) 2009-12-15 2010-11-22 晶片结构的电耦合

Country Status (5)

Country Link
US (1) US8138062B2 (https=)
JP (1) JP5721742B2 (https=)
CN (1) CN102656673B (https=)
TW (1) TWI555069B (https=)
WO (1) WO2011081741A2 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8637981B2 (en) 2011-03-30 2014-01-28 International Rectifier Corporation Dual compartment semiconductor package with temperature sensor
US8633088B2 (en) 2012-04-30 2014-01-21 Freescale Semiconductor, Inc. Glass frit wafer bond protective structure
US9580302B2 (en) 2013-03-15 2017-02-28 Versana Micro Inc. Cell phone having a monolithically integrated multi-sensor device on a semiconductor substrate and method therefor
CN103466541B (zh) * 2013-09-12 2016-01-27 上海矽睿科技有限公司 晶圆级封装方法以及晶圆
US9630832B2 (en) * 2013-12-19 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacturing
US9826630B2 (en) 2014-09-04 2017-11-21 Nxp Usa, Inc. Fan-out wafer level packages having preformed embedded ground plane connections and methods for the fabrication thereof
KR20180032985A (ko) 2016-09-23 2018-04-02 삼성전자주식회사 집적회로 패키지 및 그 제조 방법과 집적회로 패키지를 포함하는 웨어러블 디바이스
CN107827079B (zh) * 2017-11-17 2019-09-20 烟台睿创微纳技术股份有限公司 一种mems芯片的制作方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1346949A2 (en) * 2002-03-06 2003-09-24 Robert Bosch Gmbh Si wafer-cap wafer bonding method using local laser energy, device produced by the method, and system used in the method
US20060001114A1 (en) * 2004-06-30 2006-01-05 Jen-Yi Chen Apparatus and method of wafer level package
US20070161210A1 (en) * 2006-01-12 2007-07-12 Shih-Feng Shao Method for wafer level packaging and fabricating cap structures
US20080131662A1 (en) * 2006-12-05 2008-06-05 Jordan Larry L Alignment of a cap to a MEMS wafer
US20080290430A1 (en) * 2007-05-25 2008-11-27 Freescale Semiconductor, Inc. Stress-Isolated MEMS Device and Method Therefor

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3613838B2 (ja) 1995-05-18 2005-01-26 株式会社デンソー 半導体装置の製造方法
SG111972A1 (en) 2002-10-17 2005-06-29 Agency Science Tech & Res Wafer-level package for micro-electro-mechanical systems
JP3905041B2 (ja) * 2003-01-07 2007-04-18 株式会社日立製作所 電子デバイスおよびその製造方法
US20040166662A1 (en) 2003-02-21 2004-08-26 Aptos Corporation MEMS wafer level chip scale package
JP4551638B2 (ja) * 2003-08-01 2010-09-29 富士フイルム株式会社 固体撮像装置の製造方法
DE10350460B4 (de) * 2003-10-29 2006-07-13 X-Fab Semiconductor Foundries Ag Verfahren zur Herstellung von mikromechanische und/ oder mikroelektronische Strukturen aufweisenden Halbleiterbauelementen, die durch das feste Verbinden von mindestens zwei Halbleiterscheiben entstehen, und entsprechende Anordnung
US7034393B2 (en) 2003-12-15 2006-04-25 Analog Devices, Inc. Semiconductor assembly with conductive rim and method of producing the same
US7495462B2 (en) 2005-03-24 2009-02-24 Memsic, Inc. Method of wafer-level packaging using low-aspect ratio through-wafer holes
US20080191334A1 (en) 2007-02-12 2008-08-14 Visera Technologies Company Limited Glass dam structures for imaging devices chip scale package

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1346949A2 (en) * 2002-03-06 2003-09-24 Robert Bosch Gmbh Si wafer-cap wafer bonding method using local laser energy, device produced by the method, and system used in the method
US20060001114A1 (en) * 2004-06-30 2006-01-05 Jen-Yi Chen Apparatus and method of wafer level package
US20070161210A1 (en) * 2006-01-12 2007-07-12 Shih-Feng Shao Method for wafer level packaging and fabricating cap structures
US20080131662A1 (en) * 2006-12-05 2008-06-05 Jordan Larry L Alignment of a cap to a MEMS wafer
US20080290430A1 (en) * 2007-05-25 2008-11-27 Freescale Semiconductor, Inc. Stress-Isolated MEMS Device and Method Therefor

Also Published As

Publication number Publication date
TW201128691A (en) 2011-08-16
TWI555069B (zh) 2016-10-21
US8138062B2 (en) 2012-03-20
US20110143476A1 (en) 2011-06-16
WO2011081741A3 (en) 2011-09-09
JP5721742B2 (ja) 2015-05-20
JP2013513971A (ja) 2013-04-22
WO2011081741A2 (en) 2011-07-07
CN102656673A (zh) 2012-09-05

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