CN102637581A - Method for preventing outgassing of boron doped layer - Google Patents
Method for preventing outgassing of boron doped layer Download PDFInfo
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- CN102637581A CN102637581A CN2012100982487A CN201210098248A CN102637581A CN 102637581 A CN102637581 A CN 102637581A CN 2012100982487 A CN2012100982487 A CN 2012100982487A CN 201210098248 A CN201210098248 A CN 201210098248A CN 102637581 A CN102637581 A CN 102637581A
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Abstract
The invention relates to the field of manufacturing of semiconductors and particularly relates to a method for preventing outgassing of a boron doped layer. According to the method for preventing the outgassing of the boron doped layer provided by the invention, a technology that plasmas are utilized for strengthening chemical vapor deposition is adopted for depositing a layer of amorphous carbon film on a P-type silicon substrate, thereby effectively preventing the phenomenon of outgassing in an annealing process since no silification metal prevention layer exists in the B doped layer, further improving the yield of products.
Description
Technical field
The present invention relates to the manufacturing field of semiconductor integrated circuit, relate in particular to a kind of method that prevents the boron-dopped layer outgas.
Background technology
At present; Boron in the silicon (Boron) is in the high-temperature annealing process process; The easy doping content that outgas (out-gasing) phenomenon takes place and then influence boron in the silicon; Thereby cause the resistance value of silicon substrate (Si Sub) to change, the boron that diffuses out simultaneously can get into the zone of the boron that undoped originally, can cause the inefficacy of respective regions electric property.
Removing the common method that adopts of above-mentioned harmful effect is before high-temperature annealing process; Utilize metal silicide blocking layer (salicide block; Be called for short SAB); Be the silicon oxide layer that using plasma strengthens chemical gaseous phase depositing process deposition one deck 150A ~ 400A, outgas phenomenon (out-gasing) takes place with the boron that is used for stoping silicon when the high-temperature annealing process, and this metal silicide blocking layer can also be as the barrier layer of silicide (salicide).
But; Owing to do not need the metal silicide blocking layer in some technology; Like self-aligned silicide structure (salicide formation) is that directly sputter is used to form the material of silicide (salicide), owing to do not have metal silicide blocking layer (SAB) in this technology through after contact hole (CT) or contact wire (line) formation; So can form boron outgas (out-gasing) phenomenon when carrying out high-temperature annealing process after boron (B) injects, thereby cause the reduction of product yield.
Summary of the invention
The invention discloses a kind of method that prevents the boron-dopped layer outgas, wherein, may further comprise the steps:
Step S1: adopt ion implantation technology on a silicon substrate, to form the boron ion doped layer;
Step S2: the deposition amorphous c film covers the upper surface of said boron ion doped layer;
Step S3: after carrying out thermal anneal process, adopt cineration technics and wet clean process to remove said amorphous c film successively.
The above-mentioned method that prevents the boron-dopped layer outgas wherein, adopts B or BF2 that said silicon substrate is carried out ion implantation technology among the step S1.
The above-mentioned method that prevents the boron-dopped layer outgas, wherein, using plasma enhancing chemical vapor deposition method deposits said amorphous c film among the step S2.
The above-mentioned method that prevents the boron-dopped layer outgas, wherein, cineration technics described in the step S3 is a plasma ashing technology.
The above-mentioned method that prevents the boron-dopped layer outgas, wherein, the implantation concentration of said ion implantation technology is 1E14-1E16, the injection energy is 1k-20k.
The above-mentioned method that prevents the boron-dopped layer outgas, wherein, the thickness of said amorphous c film is 200A-1000A.
The above-mentioned method that prevents the boron-dopped layer outgas, wherein, the temperature of said plasma enhanced chemical vapor deposition technology is 300 ℃-500 ℃.
The above-mentioned method that prevents the boron-dopped layer outgas, wherein, the temperature of thermal anneal process is 900 ℃-1050 ℃ among the step S3.
The above-mentioned method that prevents the boron-dopped layer outgas, wherein, the time of said thermal anneal process is 5s-300s, environment is N
2, Ar and He.
The above-mentioned method that prevents the boron-dopped layer outgas, wherein, said silicon substrate is the P type, also is provided with grid on the said silicon substrate.
In sum; Owing to adopted technique scheme; The present invention proposes a kind of method that prevents the boron-dopped layer outgas; Through utilizing plasma enhanced chemical vapor deposition technology (Plasma Enhanced Chemical Vapor Deposition; Be called for short PECVD) deposit one deck amorphous carbon (amorphous carbon) film on P type silicon chip substrate, thus can effectively avoid B in annealing process (Boron) doped region owing to there is not metal silicide blocking layer (SAB) to cause the generation of outgas (out-gasing) phenomenon and then the yield of raising product.
Description of drawings
Fig. 1 is the schematic flow sheet that the present invention prevents the method for boron-dopped layer outgas;
Fig. 2-the 7th, the present invention prevent the structure schematic flow sheet of the method for boron-dopped layer outgas.
Embodiment
Be further described below in conjunction with the accompanying drawing specific embodiments of the invention:
Fig. 1 is the schematic flow sheet that the present invention prevents the method for boron-dopped layer outgas;
Fig. 2-the 7th, the present invention prevent the structure schematic flow sheet of the method for boron-dopped layer outgas.
Shown in Fig. 1-7, at first, on P type silicon substrate 1, adopt B or BF
2Carry out ion and inject (implant) technology 2, form structure as shown in Figure 3, the surface portion that is about to P type silicon substrate 1 forms B ion doped layer 3 and excess silicon substrate 11; Wherein, on the P type silicon substrate 1 a plurality of grid structures can also be set, and the implantation concentration that carries out ion implantation technology 2 is 1E14-1E16, the injection energy is 1k-20k.
Afterwards; In temperature is under the 300-500 ℃ of adjusting; Using plasma strengthens chemical vapor deposition method (Plasma Enhanced Chemical Vapor Deposition; Be called for short PECVD) 4, deposition amorphous carbon (amorphous carbon deposition) film 5 covers the upper surface of B ion doped layer 3; Wherein, the thickness of this amorphous thin film 5 is 200-1000A.
Then, at N
2, in the environment such as Ar and He, under 900-1050 ℃ temperature conditions, carry out the thermal anneal process (Anneal) 6 of 5-300s; Because barrier and stability that amorphous carbon is excellent; So amorphous c film 5; When carrying out thermal anneal process 6, can effectively stop the B in the B ion doped layer 3 that outgas (out-gasing) phenomenon takes place, and then guarantee the resistance value of the silicon substrate that B mixes and the electric property of B zone (like the excess silicon substrate 11) that undope.
At last, adopt plasma ashing technology (plasma ashing) and wet clean process (wet clean) to remove amorphous c film 5 successively after, to continue subsequent process steps.
In sum; Owing to adopted technique scheme; The present invention proposes a kind of method that prevents the boron-dopped layer outgas; Through utilizing plasma enhanced chemical vapor deposition technology deposit one deck amorphous c film on P type silicon chip substrate, thereby can effectively avoid in annealing process the B doped region owing to there not being metal silicide blocking layer (SAB) to cause the generation of outgas phenomenon, and then improve the yield of product; And removing amorphous c film only needs traditional plasma ashing and wet clean process to get final product, and technology is simple.
Through explanation and accompanying drawing, provided the exemplary embodiments of the ad hoc structure of embodiment, based on the present invention's spirit, also can do other conversion.Although foregoing invention has proposed existing preferred embodiment, yet these contents are not as limitation.
For a person skilled in the art, read above-mentioned explanation after, various variations and revise undoubtedly will be obvious.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.Any and all scope of equal value and contents all should be thought still to belong in the intent of the present invention and the scope in claims scope.
Claims (10)
1. a method that prevents the boron-dopped layer outgas is characterized in that, may further comprise the steps:
Step S1: adopt ion implantation technology on a silicon substrate, to form the boron ion doped layer;
Step S2: the deposition amorphous c film covers the upper surface of said boron ion doped layer;
Step S3: after carrying out thermal anneal process, adopt cineration technics and wet clean process to remove said amorphous c film successively.
2. the method that prevents the boron-dopped layer outgas according to claim 1 is characterized in that, adopts B or BF among the step S1
2Said silicon substrate is carried out ion implantation technology.
3. the method that prevents the boron-dopped layer outgas according to claim 2 is characterized in that, using plasma enhancing chemical vapor deposition method deposits said amorphous c film among the step S2.
4. the method that prevents the boron-dopped layer outgas according to claim 3 is characterized in that, cineration technics described in the step S3 is a plasma ashing technology.
5. the method that prevents the boron-dopped layer outgas according to claim 4 is characterized in that, the implantation concentration of said ion implantation technology is 1E14-1E16, and the injection energy is 1k-20k.
6. the method that prevents the boron-dopped layer outgas according to claim 5 is characterized in that, the thickness of said amorphous c film is 200A-1000A.
7. the method that prevents the boron-dopped layer outgas according to claim 6 is characterized in that, the temperature of said plasma enhanced chemical vapor deposition technology is 300 ℃-500 ℃.
8. the method that prevents the boron-dopped layer outgas according to claim 7 is characterized in that, the temperature of thermal anneal process is 900 ℃-1050 ℃ among the step S3.
9. the method that prevents the boron-dopped layer outgas according to claim 8 is characterized in that, the time of said thermal anneal process is 5s-300s, and environment is N
2, Ar and He.
10. according to any described method that prevents the boron-dopped layer outgas among the claim 1-9, it is characterized in that said silicon substrate is the P type, also be provided with grid on the said silicon substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN2012100982487A CN102637581A (en) | 2012-04-06 | 2012-04-06 | Method for preventing outgassing of boron doped layer |
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| CN2012100982487A CN102637581A (en) | 2012-04-06 | 2012-04-06 | Method for preventing outgassing of boron doped layer |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103489763A (en) * | 2013-09-29 | 2014-01-01 | 武汉新芯集成电路制造有限公司 | Method for preventing doping ions from outgassing in process of ion implantation |
| CN105990133A (en) * | 2015-03-03 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Method for preventing diffusion of dopant of doped wafer in high-temperature technological process |
| CN109103203A (en) * | 2018-06-29 | 2018-12-28 | 武汉华星光电技术有限公司 | A kind of cmos tft and preparation method thereof |
| CN112956000A (en) * | 2018-10-31 | 2021-06-11 | 恩特格里斯公司 | Boron doped amorphous carbon hardmask and method |
| WO2023134099A1 (en) * | 2022-01-12 | 2023-07-20 | 长鑫存储技术有限公司 | Preparation method for doped structure, and semiconductor structure |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020160592A1 (en) * | 2001-04-30 | 2002-10-31 | Yong Sun Sohn | Method for forming ultra-shallow junctions using laser annealing |
| US20050186765A1 (en) * | 2004-02-23 | 2005-08-25 | Yi Ma | Gate electrode dopant activation method for semiconductor manufacturing |
| JP2005303010A (en) * | 2004-04-12 | 2005-10-27 | Matsushita Electric Ind Co Ltd | Silicon carbide element and its manufacturing method |
| CN1839465A (en) * | 2003-08-22 | 2006-09-27 | 微米技术有限公司 | Masking methods |
| CN1864247A (en) * | 2003-10-03 | 2006-11-15 | 应用材料股份有限公司 | Absorber layer for dynamic surface annealing processing |
| US20070015373A1 (en) * | 2005-07-13 | 2007-01-18 | General Electric Company | Semiconductor device and method of processing a semiconductor substrate |
| US20080108210A1 (en) * | 2006-11-03 | 2008-05-08 | Vijay Parihar | Low temperature process for depositing a high extinction coefficient non-peeling optical absorber for a scanning laser surface anneal of implanted dopants |
| CN101256938A (en) * | 2007-03-02 | 2008-09-03 | 应用材料股份有限公司 | Absorber layer candidates and techniques for application |
| US20090250793A1 (en) * | 2008-04-08 | 2009-10-08 | Yuri Sokolov | Bpsg film deposition with undoped capping |
-
2012
- 2012-04-06 CN CN2012100982487A patent/CN102637581A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020160592A1 (en) * | 2001-04-30 | 2002-10-31 | Yong Sun Sohn | Method for forming ultra-shallow junctions using laser annealing |
| CN1839465A (en) * | 2003-08-22 | 2006-09-27 | 微米技术有限公司 | Masking methods |
| CN1864247A (en) * | 2003-10-03 | 2006-11-15 | 应用材料股份有限公司 | Absorber layer for dynamic surface annealing processing |
| US20050186765A1 (en) * | 2004-02-23 | 2005-08-25 | Yi Ma | Gate electrode dopant activation method for semiconductor manufacturing |
| JP2005303010A (en) * | 2004-04-12 | 2005-10-27 | Matsushita Electric Ind Co Ltd | Silicon carbide element and its manufacturing method |
| US20070015373A1 (en) * | 2005-07-13 | 2007-01-18 | General Electric Company | Semiconductor device and method of processing a semiconductor substrate |
| US20080108210A1 (en) * | 2006-11-03 | 2008-05-08 | Vijay Parihar | Low temperature process for depositing a high extinction coefficient non-peeling optical absorber for a scanning laser surface anneal of implanted dopants |
| CN101256938A (en) * | 2007-03-02 | 2008-09-03 | 应用材料股份有限公司 | Absorber layer candidates and techniques for application |
| US20090250793A1 (en) * | 2008-04-08 | 2009-10-08 | Yuri Sokolov | Bpsg film deposition with undoped capping |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103489763A (en) * | 2013-09-29 | 2014-01-01 | 武汉新芯集成电路制造有限公司 | Method for preventing doping ions from outgassing in process of ion implantation |
| CN105990133A (en) * | 2015-03-03 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Method for preventing diffusion of dopant of doped wafer in high-temperature technological process |
| CN109103203A (en) * | 2018-06-29 | 2018-12-28 | 武汉华星光电技术有限公司 | A kind of cmos tft and preparation method thereof |
| CN112956000A (en) * | 2018-10-31 | 2021-06-11 | 恩特格里斯公司 | Boron doped amorphous carbon hardmask and method |
| CN112956000B (en) * | 2018-10-31 | 2022-07-12 | 恩特格里斯公司 | Boron doped amorphous carbon hardmask and method |
| WO2023134099A1 (en) * | 2022-01-12 | 2023-07-20 | 长鑫存储技术有限公司 | Preparation method for doped structure, and semiconductor structure |
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Application publication date: 20120815 |