CN102623451B - Pixel array substrate - Google Patents
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- CN102623451B CN102623451B CN201210099730.2A CN201210099730A CN102623451B CN 102623451 B CN102623451 B CN 102623451B CN 201210099730 A CN201210099730 A CN 201210099730A CN 102623451 B CN102623451 B CN 102623451B
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- 239000000758 substrate Substances 0.000 title claims abstract description 109
- 230000004888 barrier function Effects 0.000 claims description 60
- 239000000463 material Substances 0.000 claims description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
- 238000010276 construction Methods 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 abstract description 5
- 230000000994 depressogenic effect Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- 238000005530 etching Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 230000012447 hatching Effects 0.000 description 3
- 238000012423 maintenance Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses a pixel array substrate, which comprises a substrate, a plurality of scanning lines, a plurality of data lines, a plurality of common lines, a plurality of capacitors, a plurality of active elements and a plurality of pixel electrodes. The substrate has a surface. The plurality of scanning lines, the plurality of data lines and the plurality of common lines are arranged on the substrate. The capacitors are arranged on the substrate and coupled to the common line, wherein the opposite surfaces of the upper electrodes of the capacitors have undulation. The active elements are disposed on the substrate. The pixel electrodes are disposed on the substrate, wherein each pixel electrode is electrically connected to the corresponding scan line and data line through different active devices.
Description
Technical field
The present invention relates to a kind of substrate, and particularly relate to a kind of image element array substrates.
Background technology
Social multimedia technology is quite flourishing now, is mostly indebted to the progress of semiconductor element and display.With regard to display, have high image quality, low consumpting power, the advantageous characteristic such as radiationless Thin Film Transistor-LCD become the main flow in market gradually.
Along with people are for the high-resolution demand of display, in display, the area of each pixel (pixel) certainly will will reduce, and the element area of display also certainly will will reduce.But as shown in Figure 1, capacitor design is on the market mostly the structure of plane formula at present.Specifically, by forming one first electrode 112 and one second electrode 116 on substrate 110, and configure an insulating barrier 114 between the first electrode 112 and the second electrode 116, to form a capacitance structure, wherein the size of the magnitude of the stored charge of capacitance structure depend on electric capacity relative to substrate 110 surface shared by size.
Therefore, similarly be Organic Light Emitting Diode (Organic Light Emitting Diode, OLED) display, when each pixel of correspondence needs more thin-film transistor quantity, wish to get high-resolution, then increase the electric capacity area of plane and certainly will become quite difficulty, and when the electric capacity area of plane cannot reduce, in order to obtain the magnitude of the stored charge that can maintain normal display frame, improving screen resolution and will become difficulty.On the other hand, similarly be that Electronic Paper (Electronic paper) display needs larger capacitor design to maintain the GTG of display frame, now, be limited to the requirement of magnitude of the stored charge and the elemental area of display cannot be reduced, thus making the resolution limitations of display.
Summary of the invention
The object of the present invention is to provide a kind of image element array substrates, it has excellent magnitude of the stored charge.
One embodiment of the invention provide a kind of image element array substrates, and it comprises a substrate, multi-strip scanning line, a plurality of data lines, many shared lines, multiple electric capacity, multiple active element and multiple pixel electrode.Substrate has a surface.Multi-strip scanning line, a plurality of data lines and many shared lines are configured on substrate.Multiple capacitance arrangement is on substrate and be coupled to bridging line, and wherein the top electrode apparent surface of each electric capacity has fluctuating.Multiple active element is configured on substrate.Multiple pixel electrode is configured on substrate, and wherein each pixel electrode is electrically connected with corresponding scan line and data wire respectively by different active elements.
In one embodiment of this invention, the maximum difference of height of the top electrode apparent surface of aforesaid each electric capacity is 50 nanometer to 2000 nanometers.
In one embodiment of this invention, the top electrode of aforesaid each electric capacity is wavy perpendicular to the section on surface.
In one embodiment of this invention, aforesaid image element array substrates, wherein sees it from the direction of vertical surface, and the top electrode of each electric capacity has many depressed areas parallel to each other.
In one embodiment of this invention, aforesaid image element array substrates, wherein sees it from the direction of vertical surface, and the top electrode of each electric capacity has multiple pitting district.
In one embodiment of this invention, the material of the passage of aforesaid active element is low temperature polycrystalline silicon or amorphous silicon.
Another embodiment of the present invention provides a kind of image element array substrates, and it comprises a substrate, one first insulating barrier, multiple active element, many articles of the first holding wires, multiple bottom electrode, many shared lines, one second insulating barrier, many articles of secondary signal lines, multiple top electrode, one the 3rd insulating barrier and multiple pixel electrodes.First insulating barrier is configured on substrate, and has multiple groove.A part for each active element is embedded in the first insulating barrier or is all configured on the first insulating barrier.Many the first holding wire, multiple bottom electrode and many shared lines are configured on the first insulating barrier.A part for each bottom electrode is arranged at least one groove, and each bridging line connects bottom electrode.Second insulating barrier covers the first insulating barrier, the first holding wire, bottom electrode and bridging line, and between the grid and source-drain electrode of each active element.Many secondary signal lines and multiple top electrode are configured on the second insulating barrier, and wherein top electrode and bottom electrode are coupled as multiple electric capacity accordingly.3rd insulating barrier covers the second insulating barrier, secondary signal line and top electrode, and has multiple contact window.Multiple pixel electrode is configured on the 3rd insulating barrier, and each pixel electrode is by the drain electrode of the active element of a contact window electrical connection correspondence.
In one embodiment of this invention, the degree of depth of aforesaid each groove is 50 nanometer to 2000 nanometers.
In one embodiment of this invention, aforesaid first insulating barrier is wavy at the section of the reeded part of tool.
In one embodiment of this invention, aforesaid image element array substrates, the groove that wherein each bottom electrode covers is strip groove parallel to each other.
In one embodiment of this invention, aforesaid image element array substrates, the groove that wherein each bottom electrode covers is multiple point-like grooves.
In one embodiment of this invention, the material of the passage of aforesaid active element is low temperature polycrystalline silicon or amorphous silicon.
In one embodiment of this invention, the drain electrode of the active element that aforesaid each top electrode electrical connection is corresponding.
In one embodiment of this invention, aforesaid first insulating barrier is a single or multiple lift structure.
Based on above-mentioned, in image element array substrates of the present invention, add electric capacity area in a direction perpendicular to a substrate, and then increase magnitude of the stored charge.Therefore, when high-resolution demand makes Pixel Dimensions micro, electric capacity area shared on substrate can be reduced to reach identical aperture opening ratio.That is, magnitude of the stored charge can be promoted when not needing sacrifice aperture opening ratio.In other words, under identical Pixel Dimensions, can aperture opening ratio be increased and promote display brightness.Or under same brightness, can backlight illumination be reduced because of the lifting of aperture opening ratio.On the other hand, under the magnitude of the stored charge that maintenance is identical, the area that electric capacity is shared on substrate can be reduced, make Pixel Dimensions micro, improve the resolution of display.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate appended accompanying drawing to be described in detail below.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the plane formula capacitance structure of prior art;
Fig. 2 A to Fig. 2 G is the Making programme upper schematic diagram of the image element array substrates of one embodiment of the invention;
Fig. 3 is the upper schematic diagram of the image element array substrates of one embodiment of the invention;
Fig. 4 is the upper schematic diagram of the image element array substrates of another embodiment of the present invention;
Fig. 5 A to Fig. 5 F is the Making programme upper schematic diagram of the image element array substrates of another embodiment of the present invention;
Fig. 6 is the upper schematic diagram of the image element array substrates of one embodiment of the invention;
Fig. 7 is the upper schematic diagram of the image element array substrates of another embodiment of the present invention.
Main element symbol description
110,210,510: substrate
112: the first electrodes
116: the second electrodes
114: insulating barrier
200,400,500,700: image element array substrates
212: the first insulating sublayer layers
214: the second insulating sublayer layers
216a, 516: passage
216b: source doping region
216c: drain doping region
218: the three insulating sublayer layers
220,520: the first insulating barriers
222,522: grid
224,524: bottom electrode
226,526: scan line
228,528: bridging line
230,530: the second insulating barriers
240,540: active element
242b, 542b: source electrode
242c, 542c: drain electrode
244,244 ', 544,544 ': top electrode
246,546: data wire
250,550: the three insulating barriers
260,560: pixel electrode
518: ohmic contact pattern
S, S ': surface
U, U ': groove
D
u, D
u ': the degree of depth
W1, W2, W3: opening
C1, C2, C3, C4: electric capacity
D, D ': maximum difference of height
A-A ': hatching line
A1, A2, A3, A4: depressed area
Embodiment
Fig. 2 A to Fig. 2 G is the Making programme generalized section of the image element array substrates of one embodiment of the invention.
Please refer to Fig. 2 A, a surperficial S of a substrate 210 is formed one first insulating sublayer layer 212 and one second insulating sublayer layer 214 in order.In the present embodiment, substrate 210 is such as glass substrate, and the material of the first insulating sublayer layer 212 is such as silicon nitride (SiN
x), and the material of the second insulating sublayer layer 214 is such as Si oxide (SiO
x), but the present invention is not as limit.
Please refer to Fig. 2 B, the second insulating sublayer layer 214 is formed a channel material layer (not illustrating).The material of this channel material layer can be low temperature polycrystalline silicon or amorphous silicon.In the present embodiment, the material of channel layer material is low temperature polycrystalline silicon, and wherein polysilicon can be the material by thermal annealing (annealing), amorphous silicon being become polysilicon.
Then, this channel material layer of patterning and the part that retains for layout passage.And utilize doping (doping) N-type or P type admixture, to form a passage 216a of one source pole doped region 216b, a drain doping region 216c and the admixture that do not adulterate, wherein passage 216a is configured between source doping region 216b and drain doping region 216c.Specifically, if the admixture of the source doping region 216b of passage 216a both sides and drain doping region 216c doping is N-type, then N-type metal-oxide-semiconductor (MOS) (NMOS) transistor is defined as.Otherwise, then P type metal-oxide-semiconductor (MOS) (PMOS) transistor is defined as.
Please refer to Fig. 2 C, the second insulating sublayer layer 214 forms one the 3rd insulating sublayer layer 218, and this 3rd insulating sublayer layer 218 covers passage 216, source doping region 216b and drain doping region 216c.In addition, the first insulating sublayer layer 212, second insulating sublayer layer 214 and the 3rd insulating sublayer layer 218 form the first insulating barrier 220 of a sandwich construction.
Then, etch the second insulating sublayer layer 214 and the 3rd insulating sublayer layer 218 to form groove U, and expose part first insulating sublayer layer 212, the degree of depth D of its further groove
ube 50 nanometer to 2000 nanometers.In the present embodiment, the mode forming groove U is such as etch similar wavy figure by dry ecthing (dry etching) or wet etching (wet etching).Certainly, the quantity of groove and shape are all without particular restriction.The present embodiment retains the first insulating sublayer layer 212 between the region and substrate 210 of wish layout electric capacity, interferes with each other to avoid the material of the first insulating sublayer layer about 212.Specifically, for manufacture craft is convenient, the material of the first insulating sublayer layer 212 of the present embodiment can select the material different from the second insulating sublayer layer 214, more suitable etchant of arranging in pairs or groups, make in the etching process forming groove U, the first insulating sublayer layer 212 can as etch stop.But the present invention, not as limit, in other embodiments, also can configure the first insulating sublayer layer 212.
Please refer to Fig. 2 D, the first insulating barrier 220 is formed many first holding wires (not illustrating), multiple bottom electrode 224, many shared lines (not illustrating) and grid 222.A part for each bottom electrode 224 is arranged at least one groove U.In the present embodiment, the material of the first holding wire, bottom electrode 224, bridging line and grid 222 can be metal, alloy or metal laminated, but the present invention is not as limit.
Please refer to Fig. 2 E, form one second insulating barrier 230, to cover the first insulating barrier 220, first holding wire, bottom electrode 224, bridging line and grid 222.Then, form contact window W1, this contact window W1 runs through the second insulating barrier 230 and the 3rd insulating sublayer layer 218, and exposes part source doping region 216b and drain doping region 216c.In the present embodiment, the method forming contact window W1 is such as etching, but the present invention is not as limit.
Please refer to Fig. 2 F, second insulating barrier 230 is formed many secondary signal lines (not illustrating), multiple top electrode 244, source electrode 242b and drain electrode 242c, and wherein source electrode 242b and drain electrode 242c is electrically connected with source doping region 216b and drain doping region 216c respectively by contact window W1.Now, multiple active element 240 completes.In the present embodiment, active element 240 part is embedded in the first insulating barrier 220, and the second insulating barrier 230 active element 240 grid 222 and source electrode 242b and drain between 242c.At this, source electrode 242b and drain electrode 242c is defined as source-drain electrode jointly.In addition, top electrode 244 and bottom electrode 224 are coupled as multiple electric capacity C1 accordingly by the second insulating barrier 230.The surperficial S of top electrode 244 opposing substrate 210 of electric capacity C1 has fluctuating.In the present embodiment, the top electrode 244 of electric capacity C1 is wavy perpendicular to the section of surperficial S.In addition, the maximum difference of height D of the top electrode 244 apparent surface S of electric capacity C1 is 50 nanometer to 2000 nanometers.
Then, form one the 3rd insulating barrier 250, to cover the second insulating barrier 230, secondary signal line and top electrode 244, and optionally the wavelike structure of electric capacity C1 is filled and led up.In the present embodiment, the material of the 3rd insulating barrier 250 is such as organic photoresist (Organic photoresist).In addition, the 3rd insulating barrier 250 has contact window W2.In the present embodiment, the method forming contact window W2 is such as etching, but the present invention is not as limit.
Please refer to Fig. 2 G, the 3rd insulating barrier 250 forms multiple pixel electrode 260, and pixel electrode 260 is electrically connected the drain electrode 242c of corresponding active element 240 by contact window W2.So far, namely image element array substrates 200 is done.
Next be further described with the top view of this image element array substrates 200.Fig. 3 is the upper schematic diagram of the image element array substrates of Fig. 2 G, and is Fig. 2 G along the section of A-A ' hatching line in Fig. 3.
Please refer to Fig. 3 and Fig. 2 G, the image element array substrates 200 of the present embodiment comprise there is a surperficial S substrate 210 and placement substrate 210 on multi-strip scanning line 226, a plurality of data lines 246, many shared lines 228, multiple electric capacity C1, multiple active element 240 and multiple pixel electrode 260.Wherein every shared line 228 is coupled to multiple electric capacity C1, and each shared line 228 connects multiple bottom electrode 224.In addition, grid 222 is overlapping in the orthographic projection (not illustrating) of substrate 210 with passage 216a in the orthographic projection (not illustrating) of substrate 210.In addition, each pixel electrode 260 is electrically connected with corresponding scan line 226 and data wire 246 respectively by different active elements 240.In the present embodiment, see it from the direction of vertical surface S, the top electrode 244 of each electric capacity C1 has many depressed area A1 parallel to each other.
It should be noted that the image element array substrates 200 of the present embodiment utilizes many depressed area A1 parallel to each other to increase electric capacity C1 perpendicular to the surface area on substrate 210 direction, and then increase magnitude of the stored charge.Therefore, the image element array substrates 200 of the present embodiment can promote magnitude of the stored charge under identical aperture opening ratio.In addition, the image element array substrates 200 of the present embodiment also can reduce electric capacity C1 area shared over the substrate 210 under identical magnitude of the stored charge, makes Pixel Dimensions micro, improves the resolution of display.
In addition, the top electrode 244 of electric capacity C1, except can having above-mentioned many depressed area A1 parallel to each other, in other embodiments, also can replace strip depressed area A1 in multiple pitting district.Fig. 4 is the upper schematic diagram of the image element array substrates of another embodiment of the present invention.Please refer to Fig. 4, the image element array substrates 400 of the present embodiment has similar structure to the image element array substrates 300 in Fig. 3, and the similar component of similar symbology and there is similar effect, therefore repeat no more.The top electrode 244 ' that the two difference is in the electric capacity C2 of the image element array substrates 400 in the present embodiment has multiple pitting district A2.In addition, multiple pitting district A2 also has the function of above-mentioned many depressed area A1 parallel to each other.For example, multiple pitting district A2 can increase electric capacity C2 perpendicular to the surface area on substrate 210 direction, and then increases magnitude of the stored charge.In addition, multiple pitting district A2 also can reduce electric capacity C2 area shared over the substrate 210 under identical magnitude of the stored charge, makes Pixel Dimensions micro, improves the resolution of display.
In addition, image element array substrates of the present invention is except can having the active element of above-mentioned low temperature polycrystalline silicon, and in other embodiments, image element array substrates of the present invention also can have the active element of amorphous silicon.Below will be described in detail with Fig. 5 A to Fig. 5 F, Fig. 6 and Fig. 7.
Fig. 5 A to Fig. 5 F is the Making programme generalized section of the image element array substrates of another embodiment of the present invention.
Please refer to Fig. 5 A, at upper formation one first insulating barrier 520 of a surperficial S ' of a substrate 510.Then, etch the first insulating barrier 520 to form groove U ', and expose part substrate 510, the degree of depth D of its further groove
u 'be 50 nanometer to 2000 nanometers.In the present embodiment, the mode forming groove U is such as etch similar wavy figure by dry ecthing or wet etching.Certainly, the quantity of groove and shape are all without particular restriction.
Please refer to Fig. 5 B, the first insulating barrier 520 is formed many first holding wires (not illustrating), multiple bottom electrode 524, many common-battery lines (not illustrating) and grid 522.A part for each bottom electrode 524 is arranged at least one groove U '.In the present embodiment, the material of the first holding wire, bottom electrode 524, bridging line and grid 522 can be metal, alloy or metal laminated, but the present invention is not as limit.
Please refer to Fig. 5 C, formation one second insulating barrier 530, passage 516 and an ohmic contact pattern 518 are on the first insulating barrier 520 in succession, and are positioned at above grid 522.
Please refer to Fig. 5 D, the second insulating barrier 530 and ohmic contact pattern 518 are formed many secondary signal lines (not illustrating), multiple top electrode 544, source electrode 542b and drain electrode 542c in succession.Now, multiple active element 540 completes.In the present embodiment, active element 540 is bottom gate configuration, but the present invention is not as limit.In other embodiments, active element also can be the structure of top grid, and also or be anyly familiar with this operator and slightly can do this structure and change, therefore the present invention does not limit the structure of active element.In the present embodiment, active element 540 is all configured on the first insulating barrier 520, and this second insulating barrier 530 active element 540 grid 522 and source electrode 542b and drain between 542c.At this, source electrode 542b and drain electrode 542c is defined as source-drain electrode jointly.In addition, top electrode 544 and bottom electrode 524 are coupled as multiple electric capacity C3 accordingly by the second insulating barrier 530, and wherein the surperficial S ' of top electrode 544 opposing substrate 510 of electric capacity C3 has fluctuating.In the present embodiment, the top electrode 544 of electric capacity C3 is wavy perpendicular to the section of surperficial S '.In addition, the maximum difference of height D ' of the top electrode 544 apparent surface S ' of electric capacity C3 is 50 nanometer to 2000 nanometers.
Please refer to Fig. 5 E, form one the 3rd insulating barrier 550, to cover the second insulating barrier 530, secondary signal line and top electrode 544, and optionally the wavelike structure of electric capacity C3 is filled and led up.In the present embodiment, the material of the 3rd insulating barrier 550 is such as organic photoresist.In addition, the 3rd insulating barrier 550 has multiple contact window W3.In the present embodiment, the method forming contact window W3 is such as that etching or laser divest, but the present invention is not as limit.
Please refer to Fig. 5 F, the 3rd insulating barrier 550 forms multiple pixel electrode 560, and pixel electrode 560 is electrically connected the drain electrode 542c of corresponding active element 540 by contact window W3.So far, namely image element array substrates 500 is done.
Next be further described with the top view of this image element array substrates 500.Fig. 6 is the upper schematic diagram of the image element array substrates of Fig. 5 F, and is Fig. 5 F along the section of A-A ' hatching line in Fig. 6.
Please refer to Fig. 6 and Fig. 5 F, the image element array substrates 500 of the present embodiment comprise there is a surperficial S ' substrate 510 and placement substrate 510 on multi-strip scanning line 526, a plurality of data lines 546, many shared lines 528, multiple electric capacity C3, multiple active element 540 and multiple pixel electrode 560.Wherein every shared line 528 is coupled to multiple electric capacity C3, and each shared line 528 connects multiple bottom electrode 524.In addition, grid 522 is overlapping in the orthographic projection (not illustrating) of substrate 510 with passage 516 in the orthographic projection (not illustrating) of substrate 510.In addition, each pixel electrode 560 is electrically connected with corresponding scan line 526 and data wire 546 respectively by different active elements 540.In the present embodiment, see it from the direction of vertical surface S ', the top electrode 544 of each electric capacity C3 has many depressed area A3 parallel to each other.
It should be noted that the image element array substrates 500 of the present embodiment has the function similar to the image element array substrates 200 in Fig. 3.For example, image element array substrates 500 utilizes many depressed area A3 parallel to each other to increase electric capacity C3 perpendicular to the surface area on substrate 510 direction, and then increases magnitude of the stored charge.Therefore, the image element array substrates 500 of the present embodiment can promote magnitude of the stored charge under identical aperture opening ratio, or under identical magnitude of the stored charge, reduce electric capacity C3 area shared on substrate 510.In other words, the image element array substrates 500 of the present embodiment, under the magnitude of the stored charge that maintenance is identical, by reducing electric capacity C3 area shared on substrate 510, makes Pixel Dimensions micro, and then improves the resolution of display.
In addition, the top electrode 544 of electric capacity C3, except can having above-mentioned many depressed area A3 parallel to each other, in other embodiments, also can replace strip depressed area A3 in multiple pitting district.Fig. 7 is the upper schematic diagram of the image element array substrates of another embodiment of the present invention.Please refer to Fig. 7, the image element array substrates 700 of the present embodiment has similar structure to the image element array substrates 500 in Fig. 6, and similar symbol tool represents similar component and has similar effect, therefore repeats no more.The top electrode 544 ' that the two difference is in the electric capacity C4 of the image element array substrates 700 in the present embodiment has multiple pitting district A4.In addition, multiple pitting district A4 also has the function of above-mentioned many depressed area A3 parallel to each other.For example, multiple pitting district A2 can increase electric capacity C2 perpendicular to the surface area on substrate 210 direction, and then increases magnitude of the stored charge.In addition, multiple pitting district A2 also can reduce electric capacity C2 area shared over the substrate 210 under identical magnitude of the stored charge, makes Pixel Dimensions micro, improves the resolution of display.
In sum, in image element array substrates of the present invention, add electric capacity area in a direction perpendicular to a substrate, and then increase magnitude of the stored charge.Therefore, when high-resolution demand makes Pixel Dimensions micro, the aperture opening ratio of image element array substrates can be sacrificed, and be issued to excellent magnitude of the stored charge at the area reducing electric capacity shared on substrate.In other words, the image element array substrates of the embodiment of the present invention, under identical Pixel Dimensions, can increase aperture opening ratio, and then promotes display brightness.Or under the brightness of same display, can backlight illumination be reduced because of the lifting of aperture opening ratio.On the other hand, under the magnitude of the stored charge that maintenance is identical, the area that electric capacity is shared on substrate can be reduced, make Pixel Dimensions micro, improve the resolution of display, and then be applicable to needs compared with the display of large charge memory space or the display needing more active element, be such as the display such as Electronic Paper or Organic Light Emitting Diode.
Although disclose the present invention in conjunction with above execution mode; but itself and be not used to limit the present invention; this operator is familiar with in any art; without departing from the spirit and scope of the present invention; a little change and retouching can be done, therefore being as the criterion of should defining with the claim of enclosing of protection scope of the present invention.
Claims (8)
1. an image element array substrates, comprising:
Substrate;
First insulating barrier, is configured on this substrate, and has multiple groove;
Multiple active element, respectively a part for this active element is embedded in this first insulating barrier or is all configured on this first insulating barrier;
Many the first holding wires, multiple bottom electrode and many shared lines, be configured on this first insulating barrier, wherein respectively a part for this bottom electrode is arranged in those grooves, and respectively this bridging line connects those bottom electrodes;
Second insulating barrier, covers this first insulating barrier, those first holding wires, those bottom electrodes and those bridging lines, and between the grid and source-drain electrode of each this active element;
Many secondary signal lines and multiple top electrode, be configured on this second insulating barrier, wherein those top electrodes and those bottom electrodes are coupled as multiple electric capacity accordingly;
3rd insulating barrier, covers this second insulating barrier, those secondary signal lines and those top electrodes, and has multiple contact window; And
Multiple pixel electrode, is configured on the 3rd insulating barrier, and respectively this pixel electrode is by the source-drain electrode of this active element of those contact windows electrical connection correspondence.
2. image element array substrates as claimed in claim 1, wherein respectively the degree of depth of this groove is 50 nanometer to 2000 nanometers.
3. image element array substrates as claimed in claim 1, wherein this first insulating barrier is wavy at the section of the part with those grooves.
4. image element array substrates as claimed in claim 1, those grooves that wherein respectively this bottom electrode covers are strip groove parallel to each other.
5. image element array substrates as claimed in claim 1, those grooves that wherein respectively this bottom electrode covers are multiple point-like grooves.
6. image element array substrates as claimed in claim 1, wherein the material of the passage of those active elements is low temperature polycrystalline silicon or amorphous silicon.
7. image element array substrates as claimed in claim 1, wherein respectively this top electrode is electrically connected the source-drain electrode of this corresponding active element.
8. image element array substrates as claimed in claim 1, wherein this first insulating barrier is a sandwich construction.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100149591A TWI460840B (en) | 2011-12-29 | 2011-12-29 | Pixel array substrate |
| TW100149591 | 2011-12-29 |
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| Publication Number | Publication Date |
|---|---|
| CN102623451A CN102623451A (en) | 2012-08-01 |
| CN102623451B true CN102623451B (en) | 2015-02-25 |
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| CN201210099730.2A Active CN102623451B (en) | 2011-12-29 | 2012-04-06 | Pixel array substrate |
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| TWI595299B (en) * | 2014-01-23 | 2017-08-11 | 元太科技工業股份有限公司 | Pixel array |
| KR102304725B1 (en) * | 2014-10-16 | 2021-09-27 | 삼성디스플레이 주식회사 | Thin film transistor array substrate, method of manufacturing thereof and organic light-emitting display including the same |
| CN105226046A (en) * | 2015-10-13 | 2016-01-06 | 格科微电子（上海）有限公司 | Metal-insulator-metal capacitor and preparation method thereof |
| CN105304609B (en) * | 2015-10-13 | 2019-12-17 | 格科微电子（上海）有限公司 | Metal layer-insulating layer-metal layer capacitor and manufacturing method thereof |
| CN106298803A (en) * | 2016-08-18 | 2017-01-04 | 深圳市华星光电技术有限公司 | Array base palte and preparation method thereof, display panels |
| CN108806572A (en) * | 2017-05-05 | 2018-11-13 | 元太科技工业股份有限公司 | Dot structure |
| CN108447874B (en) * | 2018-03-22 | 2019-10-29 | 绵阳京东方光电科技有限公司 | Array substrate and its manufacturing method, display panel, electronic device |
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| CN110690256B (en) * | 2019-08-29 | 2023-02-03 | 福建华佳彩有限公司 | Flexible TFT substrate and manufacturing method thereof |
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| CN102623451A (en) | 2012-08-01 |
| TWI460840B (en) | 2014-11-11 |
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