CN101136339A - Indicator element and manufacturing method therefor - Google Patents
Indicator element and manufacturing method therefor Download PDFInfo
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- CN101136339A CN101136339A CNA2007101520817A CN200710152081A CN101136339A CN 101136339 A CN101136339 A CN 101136339A CN A2007101520817 A CNA2007101520817 A CN A2007101520817A CN 200710152081 A CN200710152081 A CN 200710152081A CN 101136339 A CN101136339 A CN 101136339A
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Abstract
This invention discloses a display element and a manufacturing method, in which, the method includes: first of all forming a first patternized conduction layer with a grid on a base board and a dielectric layer covering it, then forming a patternized semiconductor layer on the dielectric layer including a channel region and a source and a drain oppositely at either side of the channel region, after that, depositing a blocking layer selectively to cover the semiconductor layer and finally, forming a second patternized conduction layer on the blocking layer above the source and the drain. The display element includes a patternized blocking layer and a patternized semiconductor layer, and the blocking layer covers the semiconductor layer.
Description
Technical field
The present invention relates to a kind of display element and manufacture method thereof.Particularly, relate to a kind of thin-film transistor (thin-film transistor) and manufacture method thereof, relate in particular to and use electroless plating (electroless plating) mode on transistorized semiconductor layer, to form the required barrier layer (barrier layer) of copper electrode with selective deposition with copper electrode.
Background technology
Along with the panel size increase of liquid crystal indicator and the lifting of resolution requirements, in the panel technology of liquid crystal indicator, replacing traditional aluminium with copper (Cu) gradually is the plain conductor material.Aforementioned replacement is because of compared to aluminium, and copper has low-resistivity, low thermal coefficient of expansion, high-melting-point, high thermal conductivity and preferable anti-electromigration ability advantages such as (electro-migration).Thereby, adopt copper conductor can make panel have more intensive circuit and reach more excellent display quality.In addition, also can save the technology cost.Therefore, copper conductor technology is the trend of large scale and high desorbed solution crystal device.
Yet present liquid crystal indicator technology is for using the copper metal still to have many problems.Say it for example, copper can't form that tack between oxide layer, copper and the dielectric layer of self-protection is bad, copper has high diffusion coefficient in semiconductor material layer and dielectric layer and copper in low temperature can and pasc reaction generate silicide or the like.Foregoing problems all may cause the electrical deterioration of lead in the liquid crystal indicator, and then influences the quality of liquid crystal indicator.
For reducing the problems referred to above, industry is generally used copper metal and barrier layer collocation at present.For example, when with the copper metal during as the source of thin-film transistor/drain electrode, produce diffusion effect for avoiding copper directly to contact with the semi-conducting material of semiconductor layer, one barrier layer is set between copper and semiconductor layer usually, and this barrier layer materials is made of metals such as nickel, tantalum, titanium, molybdenum, chromium, tungsten or its alloy usually.
Fig. 1 shows the generalized section of the traditional display element that adopts aforementioned combination.Wherein, definition has transistor area 111 and capacitive region 113 on a substrate 11.Have a transistor arrangement in the transistor area 111, from bottom to top comprise grid 131, dielectric layer 15, patterned semiconductor layer 17, patterning barrier layer 19, source/drain electrode 211, protective layer 23 and patterning pixel electrode 25 in regular turn.Wherein, patterned semiconductor layer 17 comprises a channel layer 171 and source/drain electrode layer 173.From bottom to top comprise one first lead 133, dielectric layer 15, patterning barrier layer 19, second lead 213, protective layer 23 and patterning pixel electrode 25 in the capacitive region 113 in regular turn.Wherein, the grid 131 and first lead 133 respectively are the part of one first patterned conductive layer 13, source/the drain electrode 211 and second lead 213 respectively are the part of one second patterned conductive layer 21, and the material of first patterned conductive layer 13 and second patterned conductive layer 21 is a copper, but also visually need adopt for example aluminium or other suitable conductive metallic material.
Structure shown in Figure 1 is between the semiconductor layer 17 of the source/drain electrode 211 of copper metal and semi-conducting material, utilizes general depositional mode and carries out little shadow and etch process forms a barrier layer 19, so that both are isolated.Though this operation can solve aforementioned diffusion effect problem, because of the resistivity of barrier layer 19 usually far above conductive layer 13,21, this will cause overall electrical resistance obviously to improve.In this, in display element, enclose the zone at place as dotted line, in fact do not need to be provided with barrier layer, but consider because of the restriction or the convenience of little shadow and etch process, can't avoid usually having barrier layer in these zones.If can make the double-decker of conductive layer and barrier layer not be stored in unnecessary zone, can avoid the increase of unnecessary resistance, promote transistorized usefulness.
In addition, when carrying out little shadow and etch process, when especially using wet etching process, electrochemical reaction taking place easily between copper and barrier layer, causes edge generation barrier layer 19 undercutting (undercut) phenomenon of patterning second lead 213.This phenomenon may cause the electrical deterioration of thin-film transistor, and the live width of wayward lead.
As shown in the above description, in the thin-film transistor technology of present tool copper electrode, form a barrier layer under copper electrode,, will cause the undercut phenomenon of unnecessary resistance increase and barrier layer though can avoid the diffusion effect of copper.In view of this, providing the method for a manufacturing display element that can address the above problem simultaneously, is the ardent expectation of an industry for this reason.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of method of making the display element structure, the problem of the improper increase of the diffusion effect of copper electrode and overall electrical resistance in the solution prior art.
Another purpose of the present invention is to provide a kind of display element structure, the problem of the improper increase of the diffusion effect of copper electrode and overall electrical resistance in the solution prior art.
For achieving the above object, the invention provides a kind of method of making the display element structure, the method includes the steps of: at first, a dielectric layer that forms one first patterned conductive layer and cover this first patterned conductive layer on a substrate in regular turn, wherein first patterned conductive layer comprises a grid.Then, form a patterned semiconductor layer on dielectric layer, wherein this patterned semiconductor layer comprises a channel region, and the one source pole and the drain electrode that are positioned at the channel region two opposite sides.Afterwards, selective deposition one barrier layer is only to coat this source electrode and this drain electrode.At last, form one second patterned conductive layer, the barrier layer above covering this source electrode and draining.
For achieving the above object, the present invention also provides a kind of method of making the display element structure, the method includes the steps of: at first, define in one in regular turn and form one first patterned conductive layer and a dielectric layer on the substrate that a transistor area and a capacitive region are arranged, wherein this first patterned conductive layer comprises a grid, and this dielectric layer covers this first patterned conductive layer.Then, form a patterned semiconductor layer on this dielectric layer of this transistor area, wherein this patterned semiconductor layer has a channel region, and the one source pole and the drain electrode that are positioned at these channel region two opposite sides.Afterwards, selective deposition one barrier layer is only to coat this patterned semiconductor layer.Then, form one second patterned conductive layer, on the barrier layer above covering this source electrode and draining and the dielectric layer of this capacitive region.Form a patterning protective layer again on substrate, its tool one opening is to expose this second patterned conductive layer of part of this drain electrode top.At last, form a pixel electrode on partially patterned protective layer with this opening in, electrically connect with this second patterned conductive layer of part with this drain electrode top.
And, for achieving the above object, the invention provides a kind of display element structure, this display element structure is formed on the substrate, and comprises: a grid is arranged on this substrate; One dielectric layer covers this substrate and this grid; One patterned semiconductor layer is arranged on this dielectric layer, and it has a channel region that is positioned on this grid, and the one source pole and the drain electrode that are positioned at these passage two opposite sides; One barrier layer only coats this source electrode and this drain electrode; And one second patterned conductive layer, be arranged on this barrier layer and this dielectric layer.
The present invention adopts as electroless selective deposition program, can be in the manufacture process of thin-film transistor, formation one only coats the barrier layer of semiconductor layer and does not cover other zone, thereby has solved the diffusion effect problem of copper electrode, and avoids the improper increase of overall electrical resistance.In specific words, the present invention deposits the technology that optionally electroless plating program is used for making thin-film transistor with tool.Also promptly, before forming copper electrode, carry out an electroless plating program,, so, under the situation that need not increase technology photomask number, obtain an even barrier layer to form a barrier layer that only coats semiconductor layer.
For above-mentioned purpose of the present invention, technical characterictic and advantage can be become apparent, hereinafter cooperate appended accompanying drawing to be elaborated with preferred embodiment.
Description of drawings
Fig. 1 is traditional viewing area structural profile schematic diagram; And
Fig. 2 A to Fig. 7 is the schematic diagram of the technology of the present invention content.
Wherein, Reference numeral:
11,301: substrate 111,3011: transistor area
113,3013: capacitive region 13,303: the first patterned conductive layers
131,3031: grid 133,3033: the first leads
15,305: dielectric layer 17,307: semiconductor layer
171,3071: channel layer 173,3073: source/drain electrode layer
19,309: barrier layer 21,313: the second patterned conductive layers
211: source/drain electrode 213,3135: the second leads
23,315: protective layer 25,317: pixel electrode
3133: 3151: the first openings of drain electrode
3153: the second openings
Embodiment
At first, with reference to figure 2A.Definition has a transistor area 3011 and a capacitive region 3013 on a substrate 301.Substrate 301 is general normal to be glass substrate, but is not limited thereto, and also can optionally use quartz base plate, macromolecular material substrate or other transparent material substrate.Implement as the proper procedure of sputter (sputter) on substrate 301, to deposit a conductive layer.The material of conductive layer is a copper, but also can select for example aluminium or other suitable conductive metallic material.Utilizing little shadow and etching program again is that one first patterned conductive layer, 303, the first patterned conductive layers 303 comprise first lead 3033 that a grid 3031 and that is positioned at transistor area 3011 is positioned at capacitive region 3013 with this conductive layer of patterning.
Again with reference to figure 2B, use the depositing operation (for example chemical vapor deposition method) of any suitable prior art to form a dielectric layer 305, cover this first patterned conductive layer 303.The material of dielectric layer 305 is a silicon nitride, but also can optionally use composite bed or other suitable dielectric materials layer of silicon oxide layer, silicon nitride and silica.
Then, form a patterned semiconductor layer 307 on the transistor precalculated position of dielectric layer 305.In detail, with reference to figure 3,, on dielectric layer 305, form a channel layer 3071 and one source/drain electrode layer 3073 in regular turn by the depositing operation (for example chemical vapor deposition method) of any suitable prior art.Generally speaking, channel layer 3071 is an amorphous silicon layer, and source/drain electrode layer 3073 is a doped amorphous silicon layer, for example is N type ion doping amorphous silicon layer.Then, carry out a little shadow and an etching program, with patterning channel layer 3071 and source/drain electrode layer 3073, on the transistor precalculated position, to form a patterned semiconductor layer 307.Usually, formed channel layer 3071 will become the channel region on the transistor gate, and formed source/drain electrode layer 3073 will provide source electrode and the drain electrode that is positioned at channel region two offsides.
Afterwards, with reference to figure 4, carry out a selective deposition program to form a barrier layer 309, barrier layer 309 only coats patterned semiconductor layer 307.The material of this barrier layer is generally metal material, and it can be selected from the material of following group: nickel, chromium, cobalt, manganese, niobium, ruthenium, tantalum, titanium, molybdenum, tungsten, gold, silver, other transition metal and aforesaid combination.This selective deposition program can be for example electroless plating program.
The electroless plating program, in brief, a kind of for electroless plating method, it does not need impressed current, but under a suitable environmental condition, utilize the electric charge that the reducing agent oxidation is disengaged in the electroplate liquid, metal ion around supplying with, make the metal ion reduce deposition on plating piece surface with catalytic action, when plating piece surface catalysis electroless plating reaction is carried out, and make metal be attached on the plating piece surface and after forming a metal level, this metal level continues the reduce deposition of layer of metal under the catalysis again, thereby metal layer thickness is increased gradually, the metal level of the even and fine and close characteristic of a tool is provided.Generally speaking, the electroless plating program can be selected suitable electroplate liquid according to the metal material that desire forms, so that this metal material only is deposited on the certain material surface.Hence one can see that, and the electroless plating program has the characteristic of selective deposition, also promptly optionally only is deposited on the surface of tool catalytic.Utilize this characteristic to form barrier layer, can avoid the trouble and the restriction of traditional little shadow and etch process.
Below describe as example with the barrier layer that uses the electroless plating program on patterned semiconductor layer, to form the nickel metal.Can in this illustration electroless plating program, use one to contain nickel plating solution, for example sulfur acid nickel (NiSO
4) liquid.Preferably, this electroplate liquid can comprise the NiSO of 0.01 to 0.1 molar concentration
46H
2Hydrazine (the N of O, percentage by weight 1 to 20
2H
4), the sal-ammoniac (NH of 0.01 to 0.5 molar concentration
4Cl) and the NH of percentage by weight 0.5 to 5.0
4OH.In a particular aspect, for adopting the NiSO that comprises 0.03 molar concentration
46H
2The N of O, percentage by weight 30
2H
4, 0.1 molar concentration NH
4The NH of Cl and percentage by weight 1.4
4The electrolyte of OH is to carry out the electroless deposition of nickel metal layer.In the electroless plating program of this embodiment, the nickel metal in fact only is formed on the patterned semiconductor layer 307 that contains the silicon-silicon bond knot, and does not form on the dielectric layer 305 that contains silicon-nitrogen bond, so the nickel barrier layer will only be coated on patterned semiconductor layer 307.Formed nickel barrier layer even compact, its thickness are generally 10 to 800 nanometers (nm).
Continue,, deposit one second conductive layer 311 in substrate 301 tops with proper procedure as sputter with reference to figure 5A.One suitable material of second conductive layer 311 is a copper, also can optionally use aluminium or other conducting metal.Afterwards, shown in Fig. 5 B, carry out a little shadow and an etching program, form one second patterned conductive layer 313 with patterning second conductive layer 311, it comprises the source electrode 3131 and drain electrode 3133 of transistor area 3011, and second lead 3135 of capacitive region 3013.Detailed speech for removing part doped amorphous silicon layer 3073 and the part barrier layer 309 that is positioned at grid 3031 tops in the transistor area 3011 simultaneously in etching program.Can Wet-type etching or dry-etching carry out this part and remove.Thereby in transistor area 3011, be positioned on this barrier layers 309 of this patterned semiconductor layer 307 tops (also promptly being positioned on the barrier layer 309 of source electrode and drain electrode top) and stay part second patterned conductive layer 313, promptly respectively with the source electrode 3131 and drain electrode 3133 of source electrode with the drain electrode electrically connect.Relatively, in capacitive region 3013, on the dielectric layer 305 above first lead 3033, stay part second patterned conductive layer 313 as second lead 3135.
By the content of Fig. 5 B as can be known, utilize the electroless plating program optionally only to form barrier layer 309 around semiconductor layer 307, that is, formed barrier layer 309 only coats semiconductor layer 307, and need not increase the photomask number of technology.In addition, because the electroless plating program only forms barrier layer 309 around patterned semiconductor layer 307, so barrier layer 309 exists only between patterned semiconductor layer 307 and source electrode 3131 and the drain electrode 3133.That is, part second patterned conductive layer 313 belows that only are positioned on the patterned semiconductor layer 307 are provided with barrier layer 309, and all the other second patterned conductive layer 313 belows partly then barrier layer free 309 exist, as the dotted line sign place among Fig. 5 B.This result not only can reduce the interface that exposes second patterned conductive layer 313 and barrier layer 309, avoid in second patterned conductive layer, 313 edge generation barrier layers, 309 undercut phenomenon, and can reduce second patterned conductive layer 313 and barrier layer 309 double-deck existence zones, thereby the minimizing unnecessary resistance promotes transistorized overall efficiency.
Continue with reference to figure 6, form a patterning protective layer 315 in substrate 301 tops, it has one first opening 3151, to expose part drain electrode 3133; It also has one second opening 3153, to expose part second lead 3135.The material of patterning protective layer 315 is generally silicon nitride, but also can optionally use composite bed or other suitable dielectric materials layer of silicon oxide layer, silicon nitride layer and silica.
At last, with reference to figure 7, form a pixel electrode 317 on this patterning protective layer 315 of part with opening 3151,3153 in, pixel electrode 317 and this drain electrode 3133 and second lead 3135 are electrically connected.
In sum, the present invention is by the selective deposition program, the means of especially electroless plating program, can be under the situation that need not increase technology photomask number, in reaching the purpose that only on semiconductor layer, forms the barrier layer of even compact on the transistor technology, and can avoid the problems such as live width of electrical deterioration of the caused thin-film transistor of barrier layer undercut phenomenon and wayward lead, and reduce because of the caused resistance of the double-decker of conductive layer and barrier layer.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; being familiar with those of ordinary skill in the art ought can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (25)
1. a method of making the display element structure is characterized in that, comprises:
One substrate is provided;
Form one first patterned conductive layer and a dielectric layer in regular turn on this substrate, wherein this first patterned conductive layer comprises a grid, and this dielectric layer is for covering this first patterned conductive layer;
Form a patterned semiconductor layer on this dielectric layer, this patterned semiconductor layer comprises a channel region and reaches in the one source pole and a drain electrode of these channel region two opposite sides;
Selective deposition one barrier layer is only to coat this patterned semiconductor layer; And
Form one second patterned conductive layer, cover this barrier layer of this source electrode and this drain electrode top.
2. method according to claim 1 is characterized in that, this barrier layer is to comprise the metal that is selected from following group: nickel, chromium, cobalt, manganese, niobium, ruthenium, tantalum, titanium, molybdenum, tungsten, gold, silver, other transition metal and aforesaid combination.
3. method according to claim 1 is characterized in that, this selective deposition step comprises carries out an electroless plating.
4. method according to claim 3 is characterized in that, this electroless plating use one contains nickel plating solution and carries out.
5. method according to claim 4 is characterized in that this electroplate liquid comprises the NiSO of 0.01 to 0.1 molar concentration
46H
2The N of O, percentage by weight 1 to 20
2H
4, 0.01 to 0.5 molar concentration NH
4The NH of Cl and percentage by weight 0.5 to 5.0
4OH.
6. method according to claim 1 is characterized in that the material of this second patterned conductive layer comprises copper.
7. method according to claim 1 is characterized in that the material of this second patterned conductive layer comprises aluminium.
8. method according to claim 1 is characterized in that this channel region belongs to an amorphous silicon layer.
9. method according to claim 1 is characterized in that, this source electrode and this drain electrode belong to a doped amorphous silicon layer.
10. method according to claim 9 is characterized in that, this doped amorphous silicon layer is a N type ion heavily doped amorphous silicon layer.
11. method according to claim 1 is characterized in that, the thickness of this barrier layer is 10 to 800 nanometers.
12. a method of making the display element structure is characterized in that, comprises:
Provide a definition that the substrate of one transistor area and a capacitive region is arranged;
Form one first patterned conductive layer and a dielectric layer in regular turn on this substrate, this first patterned conductive layer is for comprising a grid, and this dielectric layer is this first patterned conductive layer of covering;
Form a patterned semiconductor layer on the dielectric layer of this transistor area, this patterned semiconductor layer comprises the one source pole and a drain electrode of a channel region and channel region two opposite sides;
Selective deposition one barrier layer is only to coat this patterned semiconductor layer;
Form one second patterned conductive layer, cover this barrier layer of this source electrode and this drain electrode top and this dielectric layer of this capacitive region;
Form a patterning protective layer on this substrate, its tool one opening is to expose this second patterned conductive layer of part of this drain electrode top; And
Form a pixel electrode on this patterning protective layer of part with this opening in, electrically connect with this part second patterned conductive layer with this drain electrode top.
13. method according to claim 12 is characterized in that, this selective deposition step comprises carries out an electroless plating.
14. method according to claim 13, it is characterized in that this electroless plating use one contains the electroplate liquid that is selected from following group metal and carries out: nickel, chromium, cobalt, manganese, niobium, ruthenium, tantalum, titanium, molybdenum, tungsten, gold, silver, other transition metal and aforesaid combination.
15. method according to claim 13 is characterized in that, this electroless plating uses one to contain nickel plating solution.
16. method according to claim 15 is characterized in that, this electroplate liquid comprises the NiSO of 0.01 to 0.1 molar concentration
46H
2The N of O, percentage by weight 1 to 20
2H
4, 0.01 to 0.5 molar concentration NH
4The NH of Cl and percentage by weight 0.5 to 5.0
4OH.
17. method according to claim 12 is characterized in that, the material of this second patterned conductive layer is a copper.
18. method according to claim 12 is characterized in that, the material of this second patterned conductive layer is an aluminium.
19. method according to claim 12 is characterized in that, the thickness of this barrier layer is 10 to 800 nanometers.
20. a display element structure is formed on the substrate, it is characterized in that, comprises:
One grid is arranged on this substrate;
One dielectric layer covers this substrate and this grid;
One patterned semiconductor layer is arranged on this dielectric layer, comprises an one source pole and a drain electrode that is positioned at the channel region on this grid and is positioned at these passage two opposite sides;
One barrier layer only coats this patterned semiconductor layer; And
One second patterned conductive layer is arranged on this barrier layer and this dielectric layer.
21. display element structure according to claim 20 is characterized in that the material of this second patterned conductive layer is for comprising copper.
22. display element structure according to claim 20 is characterized in that the material of this second patterned conductive layer is for comprising aluminium.
23. display element structure according to claim 20 is characterized in that the material of this barrier layer is for comprising nickel.
24. display element structure according to claim 20 is characterized in that, this barrier layer comprises the metal that is selected from following group: the alloy of chromium, cobalt, manganese, niobium, ruthenium, tantalum, titanium, molybdenum, tungsten, gold, silver, other transition metal and aforementioned metal.
25. display element structure according to claim 20 is characterized in that, the thickness of this barrier layer is 10 to 800 nanometers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101520817A CN100530570C (en) | 2007-10-09 | 2007-10-09 | Indicator element and manufacturing method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101520817A CN100530570C (en) | 2007-10-09 | 2007-10-09 | Indicator element and manufacturing method therefor |
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| Publication Number | Publication Date |
|---|---|
| CN101136339A true CN101136339A (en) | 2008-03-05 |
| CN100530570C CN100530570C (en) | 2009-08-19 |
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|---|---|---|---|
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102623451A (en) * | 2011-12-29 | 2012-08-01 | 友达光电股份有限公司 | Pixel array substrate |
| CN107316907A (en) * | 2017-06-23 | 2017-11-03 | 南京中电熊猫液晶显示科技有限公司 | Coplanar type thin film transistor (TFT) and its manufacture method |
| CN109100893A (en) * | 2018-06-29 | 2018-12-28 | 武汉华星光电技术有限公司 | Display panel and preparation method thereof, array substrate |
| CN113113427A (en) * | 2021-03-23 | 2021-07-13 | Tcl华星光电技术有限公司 | Array substrate, preparation method thereof and display panel |
| CN114185209A (en) * | 2022-02-17 | 2022-03-15 | 成都中电熊猫显示科技有限公司 | Array substrate, display panel and display device |
-
2007
- 2007-10-09 CN CNB2007101520817A patent/CN100530570C/en active Active
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102623451A (en) * | 2011-12-29 | 2012-08-01 | 友达光电股份有限公司 | Pixel array substrate |
| TWI460840B (en) * | 2011-12-29 | 2014-11-11 | Au Optronics Corp | Pixel array substrate |
| CN102623451B (en) * | 2011-12-29 | 2015-02-25 | 友达光电股份有限公司 | Pixel array substrate |
| CN107316907A (en) * | 2017-06-23 | 2017-11-03 | 南京中电熊猫液晶显示科技有限公司 | Coplanar type thin film transistor (TFT) and its manufacture method |
| CN109100893A (en) * | 2018-06-29 | 2018-12-28 | 武汉华星光电技术有限公司 | Display panel and preparation method thereof, array substrate |
| CN109100893B (en) * | 2018-06-29 | 2021-11-09 | 武汉华星光电技术有限公司 | Display panel, preparation method thereof and array substrate |
| CN113113427A (en) * | 2021-03-23 | 2021-07-13 | Tcl华星光电技术有限公司 | Array substrate, preparation method thereof and display panel |
| CN114185209A (en) * | 2022-02-17 | 2022-03-15 | 成都中电熊猫显示科技有限公司 | Array substrate, display panel and display device |
| CN114185209B (en) * | 2022-02-17 | 2022-05-27 | 成都中电熊猫显示科技有限公司 | Array substrate, display panel and display device |
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| Publication number | Publication date |
|---|---|
| CN100530570C (en) | 2009-08-19 |
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