CN100401466C - Manufacturing method of thin-film transistor array substrate and metal layer - Google Patents
Manufacturing method of thin-film transistor array substrate and metal layer Download PDFInfo
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- CN100401466C CN100401466C CNB2005100728397A CN200510072839A CN100401466C CN 100401466 C CN100401466 C CN 100401466C CN B2005100728397 A CNB2005100728397 A CN B2005100728397A CN 200510072839 A CN200510072839 A CN 200510072839A CN 100401466 C CN100401466 C CN 100401466C
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- 239000000758 substrate Substances 0.000 title claims abstract description 156
- 239000002184 metal Substances 0.000 title claims abstract description 91
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 91
- 239000010409 thin film Substances 0.000 title claims abstract description 83
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 238000009413 insulation Methods 0.000 claims abstract description 28
- 238000009713 electroplating Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 117
- 238000007747 plating Methods 0.000 claims description 81
- 229920002120 photoresistant polymer Polymers 0.000 claims description 55
- 238000000059 patterning Methods 0.000 claims description 49
- 239000012774 insulation material Substances 0.000 claims description 48
- 239000004020 conductor Substances 0.000 claims description 38
- 239000000463 material Substances 0.000 claims description 31
- 238000005229 chemical vapour deposition Methods 0.000 claims description 25
- 238000000151 deposition Methods 0.000 claims description 18
- 230000008021 deposition Effects 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 15
- 229910021417 amorphous silicon Inorganic materials 0.000 description 9
- 239000007769 metal material Substances 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000005234 chemical deposition Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005289 physical deposition Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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Abstract
The present invention relates to a manufacturing method of a thin-film transistor array substrate and a metal layer, which comprises the following steps: firstly, a substrate is provided, and a patterned first metal layer is formed on the substrate in an electroplating mode; secondly, a grid insulation layer is formed on the substrate, and the grid insulation layer can cover the first metal layer; finally, a semiconductor layer is formed on the grid insulation layer above the first metal layer, and a patterned second metal layer is formed on the semiconductor layer, wherein the first metal layer, the second metal layer and the semiconductor layer form a plurality of thin film transistors, a plurality of scanning wirings and a plurality of data wirings on the substrate, and the scanning wirings and the data wirings are coupled to the thin film transistors.
Description
Technical field
The present invention is about a kind of thin film transistor (TFT) array (Thin Film Transistor Array, TFT Array) manufacture method of substrate and metal level thereof, and especially in regard to a kind of method of utilizing galvanoplastic (Plating) to make thin film transistor array substrate and metal level thereof.
Prior art
(Cathode Ray Tube CRT) because of having excellent display quality and its economy, monopolizes monitor market in recent years to cathode ray tube always.Yet, operate the environment of most terminating machine/display equipments on the table for the individual, or consider that with the environmental protection and the viewpoint of saving the energy still there are many problems in cathode ray tube for the usability in space and the consumption of the energy.Therefore, have that high image quality, space utilization efficient are good, the Thin Film Transistor-LCD (Thin Film Transistor Liquid CrystalDisplay, TFT LCD) of low-power consumption, advantageous characteristic such as radiationless becomes the main flow in market gradually.
Conventional Thin Film Transistor-LCD is many with the metallic circuit material of aluminium as thin film transistor array substrate.Yet, under the market trend of Thin Film Transistor-LCD large scaleization now, certainly will need to increase the metallic circuit length of Thin Film Transistor-LCD inside.Wherein incident, be that the impedance of metallic circuit increases, make signal delay in the Thin Film Transistor-LCD, and then cause problems such as the show image of Thin Film Transistor-LCD is not good.
Summary of the invention
In view of this, purpose of the present invention just is to provide a kind of method of utilizing galvanoplastic to make thin film transistor array substrate, to improve the phenomenon of signal delay in the large scale Thin Film Transistor-LCD.
A further object of the present invention provides a kind of galvanoplastic of utilizing to form the method for the metal level in the thin film transistor array substrate, makes the material of the metal level in the thin film transistor array substrate have various selectivity.
Based on above-mentioned or other purposes, the present invention proposes a kind of manufacture method of thin film transistor array substrate, and its step is as follows: a substrate at first is provided, and forms the first metal layer of patterning with plating mode on substrate; On substrate, form a gate insulation layer afterwards, and gate insulation layer can cover the first metal layer; On the gate insulation layer above the first metal layer, form a semiconductor layer then; And on semiconductor layer, form second metal level of patterning.Wherein, the first metal layer, second metal level and the semiconductor layer multi-strip scanning wiring and many data arranges that on substrate, constitute a plurality of thin-film transistors and be coupled to thin-film transistor.
In a preferred embodiment of the invention, the method that forms the first metal layer of patterning on substrate for example comprises the following steps: at first, for example on substrate, utilize physical vaporous deposition or chemical vapour deposition technique to form one first conductive material layer, and first conductive material layer is carried out the step of a patterning, to form one first plating seed layer of patterning.And this for example is that first conductive material layer is carried out photoetching process and etch process to the step that first conductive material layer carries out patterning.Then, be electrode with first plating seed layer again, electroplate and form the first metal layer.
In addition, form after first plating seed layer of patterning on substrate, and electroplate before the formation the first metal layer, for example can utilize chemical vapour deposition technique forms earlier an insulation material layer comprehensively on substrate.Then, insulation material layer is carried out patterning.The step of this patterning for example is to form earlier a photoresist layer on insulation material layer, and then is mask with first plating seed layer, by the opposite side of substrate photoresist layer is exposed dorsad.Afterwards, photoresist layer is developed, and be mask, insulation material layer is carried out removing photoresist layer again after the etching, make insulation material layer expose first plating seed layer with the photoresist layer.
In a preferred embodiment of the invention, for example for example comprise the following steps: at first to utilize in the method that forms first plating seed layer of patterning on the substrate chemical vapour deposition technique forms an insulation material layer on substrate; On insulation material layer, form the photoresist layer of patterning then; Be mask with the photoresist layer again, after overexposure and step of developing, etching insulation material layer again is so that insulation material layer exposes the substrate of part; For example utilize then physical vaporous deposition forms one first conductive material layer comprehensively on substrate; At last, utilize for example photoresist lift off method (Lift Off) to remove photoresist layer and first conductive material layer that is positioned on the photoresist layer, to form first plating seed layer.
In a preferred embodiment of the invention, the method that forms the first metal layer on substrate comprises the following steps: at first, for example utilizes physical vaporous deposition or chemical vapour deposition technique to form one first plating seed layer on substrate comprehensively.Then, be electrode with first plating seed layer, electroplate and form one first metal material layer.Afterwards, on first metal material layer, utilize for example mask layer of chemical vapour deposition technique formation, and mask layer is carried out photoetching process and etch process, with the patterned mask layer.At last, first metal material layer and first plating seed layer are carried out etching, to form the first metal layer by mask layer.In addition, the material of mask layer for example is silicon nitride or silica.
In a preferred embodiment of the invention, the method that forms semiconductor layer for example is to form channel layer earlier on gate insulation layer, forms ohmic contact layer then on channel layer.In addition, the material of the first metal layer for example is a copper.
In a preferred embodiment of the invention, wherein the method at second metal level that forms patterning on the semiconductor layer comprises: for example at first utilize physical vaporous deposition or chemical vapour deposition technique to form one deck second conductive material layer on semiconductor layer, then second conductive material layer is carried out photoetching process and etch process with the second conductive material layer patterning, to form second plating seed layer.Afterwards, be electrode with second plating seed layer, electroplate and form second metal level.In one embodiment, the material of second metal level for example is a copper.
The present invention also proposes a kind of method that forms the metal level in the thin film transistor array substrate, and it comprises the following steps: at first to provide a substrate; On substrate, form a plating seed layer then; Be electrode afterwards with the plating seed layer, electroplate and form metal level.
In a preferred embodiment of the invention, for example be on substrate, to form earlier conductive material layer in the method that forms plating seed layer on the substrate; Patterning conductive material layer then is to form plating seed layer.And on substrate, form after the plating seed layer, and before electroplating the formation metal level, for example more comprise and utilize physical vaporous deposition or chemical vapour deposition technique on substrate, to form an insulation material layer comprehensively, and the patterning insulation material layer, so that insulation material layer exposes plating seed layer.
In addition, the method for patterning insulation material layer for example comprises the following steps: at first to form a photoresist layer on insulation material layer; Be mask then with the plating seed layer, photoresist layer exposed dorsad by the opposite side of substrate; Afterwards photoresist layer is developed; Be mask with the photoresist layer then, insulation material layer carried out etching, and remove photoresist layer.
In a preferred embodiment of the invention, comprise in the method that forms plating seed layer on the substrate: for example at first utilize chemical vapour deposition technique forms an insulation material layer on substrate; On insulation material layer, form the photoresist layer of patterning then; Be mask afterwards with the photoresist layer, the etching insulation material layer is so that insulation material layer exposes the substrate of part; For example utilize then physical vaporous deposition forms first conductive material layer comprehensively on substrate; And utilize for example photoresist lift off method to remove photoresist layer and first conductive material layer that is positioned on the photoresist layer, to form first plating seed layer.
In a preferred embodiment of the invention, on substrate, form plating seed layer comprehensively, and after electroplating the formation metal level, more comprise metal level and plating seed layer are carried out photoetching process and etch process.In addition, the method for formation plating seed layer for example is physical vaporous deposition or chemical vapour deposition technique.
In a preferred embodiment of the invention, the material of metal level for example is a copper.
Based on above-mentioned, the present invention is applied to galvanoplastic in the technology of thin film transistor array substrate and metal level thereof.Different with routine techniques is that the use galvanoplastic have increased the material selectivity of thin film transistor array substrate inner metal layer to make thin film transistor array substrate.Therefore, when making thin film transistor array substrate, can select for example copper or the lower metal material of other impedances for use, with promote thin-film transistor on the thin film transistor array substrate, scan wiring and data arrange electrically, and then improve the phenomenon of signal delay in the large scale liquid crystal display, and promote the image quality of LCD.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, cited below particularlyly go out preferred embodiment, and be described with reference to the accompanying drawings as follows.
Description of drawings
Fig. 1 shows the flow chart that the preferred embodiment of the present invention forms thin film transistor array substrate;
Fig. 2 A～2H shows a kind of schematic diagram of making thin film transistor array substrate of first embodiment of the invention in regular turn;
Fig. 3 A～3G shows a kind of schematic diagram of making thin film transistor array substrate of second embodiment of the invention in regular turn;
Fig. 4 A～4G shows a kind of schematic diagram of making thin film transistor array substrate of third embodiment of the invention in regular turn;
Fig. 5 A～5G shows a kind of schematic diagram of making thin film transistor array substrate of fourth embodiment of the invention respectively.
Execution mode
Fig. 1 shows the flow chart that the preferred embodiments of the present invention form thin film transistor array substrate.Please refer to Fig. 1, the method that the present invention makes thin film transistor array substrate mainly comprises the following steps: at first to provide a substrate, and as step S100, this substrate for example is a transparent substrates.And form electrode on the thing owing to use galvanoplastic to plate in desire, and just can electroplate, therefore need utilize physical vaporous deposition (as sputtering method) or chemical vapour deposition technique on substrate, to deposit layer of metal, as step S110 to form plating seed layer.Afterwards, be electrode again with the plating seed layer, and use galvanoplastic on substrate, to form the first metal layer, as step S120.Then, on substrate, utilize chemical vapour deposition technique to form the gate insulation layer that covers the first metal layer, as step S130.Afterwards, on the gate insulation layer above the first metal layer, form a semiconductor layer, as step S140.At last, on semiconductor layer, form second metal level, as step S150.
In order to be described in more detail feature of the present invention, below will be described in detail the method for making thin film transistor array substrate of the present invention with regard to a plurality of different embodiment.
First embodiment
Fig. 2 A～2G shows a kind of schematic diagram of making thin film transistor array substrate of first embodiment of the invention in regular turn.At first shown in Fig. 2 A, provide a substrate 100, this substrate 100 for example is a transparent substrates.Next shown in Fig. 2 B, on substrate, form a plating seed layer 114.Then, shown in Fig. 2 C, plating seed layer 114 is carried out photoetching process and etch process with plating seed layer 114 patternings.Afterwards, shown in Fig. 2 D, utilize the plating seed layer 114 of patterning to be electrode, on substrate 100, form the metal level 110 of a patterning in the mode of electroplating.Wherein, the material of metal level 110 for example is a copper.And, shown in Fig. 2 E, for example utilize that chemical vapour deposition technique forms a gate insulation layer 120 on substrate 100, the material of this gate insulation layer 120 for example is silicon nitride (silicon nitride) or silica (silicon oxide), and gate insulation layer 120 can cover metal level 110.Then, shown in Fig. 2 F, form a channel layer 132 earlier on the gate insulation layer above the patterned metal layer 110 120, form an ohmic contact layer 134 then on channel layer 132, wherein channel layer 132 constitutes a semiconductor layer 130 with ohmic contact layer 134.In addition, the material of channel layer 132 for example is amorphous silicon (amorphous silicon), and the material of ohmic contact layer 134 for example is the n+ doped amorphous silicon.And in another preferred embodiment of the present invention, the material of channel layer 132 can for example be a polysilicon also.Then, shown in Fig. 2 G, on semiconductor layer 130, form the plating seed layer 142 of a patterning earlier.Shown in Fig. 2 H, on plating seed layer 142, utilize galvanoplastic to form metal level 140 then.
Behind above-mentioned making step, can on substrate 100, constitute a plurality of thin-film transistors, multi-strip scanning wiring and many data arranges at formed metal level 110,140 and semiconductor layer 130 on the substrate 100, to form a thin film transistor array substrate.
Second embodiment
Fig. 3 A～3G shows a kind of schematic diagram of making thin film transistor array substrate of second embodiment of the invention in regular turn.At first as shown in Figure 3A, for example utilize physical deposition method or chemical deposition on substrate 100, to form a conductive material layer 112 comprehensively.Shown in Fig. 3 B, earlier conductive material layer 112 is carried out photoetching process and etch process then, make conductive material layer 112 patternings, and the conductive material layer 112 after the patterning is plating seed layer 114.For example utilize afterwards chemical vapour deposition technique deposits one deck insulation material layer 116 on substrate 100, this insulating layer material for example is silica or silicon nitride, and coating one deck photoresist layer 118 on insulation material layer 116, be mask with plating seed layer 114 then, photoresist layer 118 exposed dorsad from the opposite side of substrate 100.Shown in Fig. 3 C, photoresist layer 118 is developed then, and be mask, insulation material layer 116 is carried out etch process, to expose plating seed layer 114 with photoresist layer 118.Shown in Fig. 3 D, remove photoresist layer 118 afterwards, and on plating seed layer 114, utilize the galvanoplastic plated metal to form metal level 110.
It should be noted that the present embodiment and the first embodiment difference are to form after the plating seed layer 114, present embodiment forms insulation material layer 116 earlier on substrate 100, and insulation material layer 116 can cover plating seed layer 114.Afterwards, insulation material layer 116 is carried out photoetching process and etch process, plating seed layer 114 is come out, and use galvanoplastic to form metal level 110.And in first embodiment, then be directly to utilize the conductive material layer 112 of patterning as plating seed layer 114, and use galvanoplastic on plating seed layer 114, to form metal level 110, not deposition of insulative material layer 116 on substrate 100.
Next, shown in Fig. 3 E, for example utilize that chemical vapour deposition technique forms a gate insulation layer 120 on substrate 100, the material of this gate insulation layer 120 for example is silicon nitride or silica, and gate insulation layer 120 can cover metal level 110 and insulation material layer 116.Then, shown in Fig. 3 F, form a channel layer 132 earlier on the gate insulation layer above the patterned metal layer 110 120, form an ohmic contact layer 134 then on channel layer 132, wherein channel layer 132 constitutes a semiconductor layer 130 with ohmic contact layer 134.In addition, the material of channel layer 132 for example is an amorphous silicon, and the material of ohmic contact layer 134 for example is the n+ doped amorphous silicon.And in another preferred embodiment of the present invention, the material of channel layer 132 can for example be a polysilicon also.Afterwards, shown in Fig. 3 G, above semiconductor layer 130, form the plating seed layer 142 of one deck patterning earlier, form the metal level 140 of patterning then by plating seed layer 142 with galvanoplastic.
Behind above-mentioned making step, can on substrate 100, constitute a plurality of thin-film transistors, multi-strip scanning wiring and many data arranges at formed metal level 110,140 and semiconductor layer 130 on the substrate 100, to form a thin film transistor array substrate.
The 3rd embodiment
Fig. 4 A～4G shows a kind of schematic diagram of making thin film transistor array substrate of third embodiment of the invention in regular turn.At first shown in Fig. 4 A, for example utilize on substrate 100 earlier that chemical vapour deposition technique forms insulation material layer 116, photoresist layer 118 of coating earlier on insulation material layer 116 then, and utilize photoetching process and etch process with photoresist layer 118 patternings.Shown in Fig. 4 B, be mask then, insulation material layer 116 is carried out etch process, and make insulation material layer 116 expose the substrate 100 of part with photoresist layer 118.Afterwards shown in Fig. 4 C, for example utilize physical vaporous deposition forms conductive material layer 112 comprehensively on substrate 100, and utilize for example photoresist lift off method so that photoresist layer 118 and the conductive material layer 112 that is positioned at photoresist layer 118 tops are removed, and the conductive material layer 112 that is not removed is plating seed layer 114.Shown in Fig. 4 D, on plating seed layer 114, utilize galvanoplastic depositing metal layers 110 then.
Next, shown in Fig. 4 E, for example utilize that chemical vapour deposition technique forms a gate insulation layer 120 on substrate 100, the material of this gate insulation layer 120 for example is silicon nitride or silica, and gate insulation layer 120 can cover metal level 110 and insulation material layer 116.Then, shown in Fig. 4 F, form a channel layer 132 earlier on the gate insulation layer above the patterned metal layer 110 120, form an ohmic contact layer 134 then on channel layer 132, wherein channel layer 132 constitutes a semiconductor layer 130 with ohmic contact layer 134.In addition, the material of channel layer 132 for example is an amorphous silicon, and the material of ohmic contact layer 134 for example is the n+ doped amorphous silicon.And in another preferred embodiment of the present invention, the material of channel layer 132 can for example be a polysilicon also.Afterwards, shown in Fig. 4 G, above semiconductor layer 130, form the plating seed layer 142 of one deck patterning earlier, form the metal level 140 of patterning then by plating seed layer 142 with galvanoplastic.
Behind above-mentioned making step, can on substrate 100, constitute a plurality of thin-film transistors, multi-strip scanning wiring and many data arranges at formed metal level 110,140 and semiconductor layer 130 on the substrate 100, to form a thin film transistor array substrate.
The 4th embodiment
Fig. 5 A～5G shows a kind of schematic diagram of making thin film transistor array substrate of fourth embodiment of the invention respectively.At first shown in Fig. 5 A, for example utilize physical vaporous deposition or chemical vapour deposition technique on substrate 100, to form plating seed layer 114 comprehensively, and be electrode with plating seed layer 114, electroplate and form metal material layer 212.Then, shown in Fig. 5 B, utilize chemical deposition on metal material layer 212, to form a mask layer 119, the material of this mask layer 119 for example is silicon nitride or silica, and mask layer 119 is carried out photoetching process and etch process, with mask layer 119 patternings.Afterwards, shown in Fig. 5 C, carry out etch process by 119 pairs of metal material layers 212 of mask layer and plating seed layer 114, and remove mask layer 119.At last, shown in Fig. 5 D, the metal material layer 212 and the plating seed layer 114 that are carried over promptly constitute metal level 110.
Next, shown in Fig. 5 E, for example utilize that chemical vapour deposition technique forms a gate insulation layer 120 on substrate 100, the material of this gate insulation layer 120 for example is silicon nitride or silica, and gate insulation layer 120 can cover metal level 110.Then, shown in Fig. 5 F, form a channel layer 132 earlier on the gate insulation layer above the patterned metal layer 110 120, form an ohmic contact layer 134 then on channel layer 132, wherein channel layer 132 constitutes a semiconductor layer 130 with ohmic contact layer 134.In addition, the material of channel layer 132 for example is an amorphous silicon, and the material of ohmic contact layer 134 for example is the n+ doped amorphous silicon.And in another preferred embodiment of the present invention, the material of channel layer 132 can for example be a polysilicon also.Afterwards, shown in Fig. 5 G, above semiconductor layer 130, form the plating seed layer 142 of one deck patterning earlier, form the metal level 140 of patterning then by plating seed layer 142 with galvanoplastic.
Behind above-mentioned making step, can on substrate 100, constitute a plurality of thin-film transistors, multi-strip scanning wiring and many data arranges at formed metal level 110,140 and semiconductor layer 130 on the substrate 100, to form a thin film transistor array substrate.
In sum, the present invention is applied to galvanoplastic to make in the technology of thin film transistor array substrate and metal level thereof.Galvanoplastic are very fast except the speed with plated metal, and outside the comparatively cheap advantage of cost, and different with routine techniques is, use galvanoplastic to make thin film transistor array substrate, increased the material selectivity of thin film transistor array substrate inner metal layer.Therefore, when making thin film transistor array substrate, can select for example copper or the lower metal material of other impedances for use, with promote thin-film transistor, scanning lines and data arrange in the thin film transistor array substrate electrically, and then improve the phenomenon of signal delay in the large scale liquid crystal display, and promote its image quality.
Though the present invention discloses as mentioned above with preferred embodiment; but it is not to be used for limiting the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; should make variations and modifications, so protection scope of the present invention is as the criterion when later attached claims institute restricted portion.
Claims (25)
1. the manufacture method of a thin film transistor array substrate comprises:
A substrate is provided;
On this substrate, form one first plating seed layer of patterning;
On this substrate, form an insulation material layer, to cover this first plating seed layer;
On this insulation material layer, form a photoresist layer;
With this first plating seed layer is mask, by the opposite side of this substrate this photoresist layer is exposed dorsad;
This photoresist layer is developed;
With this photoresist layer is mask, and this insulation material layer is carried out etching, to expose first plating seed layer of this patterning;
With plating mode, on this substrate, form a first metal layer of patterning;
Remove this photoresist layer;
On this substrate, form a gate insulation layer, and this gate insulation layer covers this first metal layer;
On this gate insulation layer above this first metal layer, form a semiconductor layer; And
Form one second metal level of patterning on this semiconductor layer, wherein this first metal layer, this second metal level and this semiconductor layer multi-strip scanning that constitutes a plurality of thin-film transistors and be coupled to those thin-film transistors on this substrate connects up and many data arranges.
2. the manufacture method of thin film transistor array substrate as claimed in claim 1, the method that wherein forms this first metal layer of patterning on this substrate comprises:
With this first plating seed layer is electrode, electroplates to form this first metal layer.
3. the manufacture method of thin film transistor array substrate as claimed in claim 1, the method that wherein forms this first plating seed layer of patterning on this substrate comprises:
On this substrate, form one first conductive material layer; And
This first conductive material layer of patterning is to form this first plating seed layer.
4. the manufacture method of thin film transistor array substrate as claimed in claim 3, the method that wherein forms this first conductive material layer on this substrate comprises physical vaporous deposition or chemical vapour deposition technique.
5. the manufacture method of thin film transistor array substrate as claimed in claim 1, the method that wherein forms this insulation material layer on this substrate comprises chemical vapour deposition technique comprehensively.
6. the manufacture method of thin film transistor array substrate as claimed in claim 1, the method that wherein forms this first plating seed layer of patterning on this substrate comprises:
On this substrate, form an insulation material layer;
On this insulation material layer, form a photoresist layer of patterning;
With this photoresist layer is mask, and this insulation material layer of etching is so that this insulation material layer exposes this substrate of part;
On this substrate, form one first conductive material layer comprehensively; And
Remove this photoresist layer and this first conductive material layer that is positioned on this photoresist layer, to form this first plating seed layer.
7. the manufacture method of thin film transistor array substrate as claimed in claim 6, the method that wherein forms this insulation material layer on this substrate comprises chemical vapour deposition technique.
8. the manufacture method of thin film transistor array substrate as claimed in claim 6, the method that wherein forms this first conductive material layer on this substrate comprises physical vaporous deposition comprehensively.
9. the manufacture method of thin film transistor array substrate as claimed in claim 6 wherein removes this photoresist layer and comprises the photoresist lift off method with the method that is positioned at this first conductive material layer on this photoresist layer.
10. the manufacture method of thin film transistor array substrate as claimed in claim 1, the method that wherein forms this second metal level of patterning on this semiconductor layer comprises:
On this semiconductor layer, form one second plating seed layer of patterning; And
With this second plating seed layer is electrode, electroplates to form this second metal level.
11. the manufacture method of thin film transistor array substrate as claimed in claim 10, the method that wherein forms this second plating seed layer of patterning on this semiconductor layer comprises:
On this semiconductor layer, form one second conductive material layer; And
This second conductive material layer of patterning is to form this second plating seed layer.
12. the manufacture method of thin film transistor array substrate as claimed in claim 11, the method that wherein forms this second conductive material layer on this semiconductor layer comprises physical vaporous deposition or chemical vapour deposition technique.
13. the manufacture method of thin film transistor array substrate as claimed in claim 10, wherein the material of this second metal level comprises copper.
14. the manufacture method of thin film transistor array substrate as claimed in claim 1, the method that wherein forms this semiconductor layer comprises:
Form a channel layer; And
On this channel layer, form an ohmic contact layer.
15. the manufacture method of thin film transistor array substrate as claimed in claim 1, wherein the material of this first metal layer comprises copper.
16. a method that forms the metal level in the thin film transistor array substrate comprises:
A substrate is provided;
On this substrate, form one first plating seed layer of patterning;
On this substrate, form an insulation material layer, to cover this first plating seed layer;
On this insulation material layer, form a photoresist layer;
With this first plating seed layer is mask, by the opposite side of this substrate this photoresist layer is exposed dorsad;
This photoresist layer is developed;
With this photoresist layer is mask, and this insulation material layer is carried out etching, to expose first plating seed layer of this patterning;
With this plating seed layer is electrode, electroplates to form metal level; And
Remove this photoresist layer.
17. the method for the metal level in the formation thin film transistor array substrate as claimed in claim 16, the method that wherein forms this plating seed layer on this substrate comprises:
On this substrate, form a conductive material layer; And
This conductive material layer of patterning is to form this plating seed layer.
18. the method for the metal level in the formation thin film transistor array substrate as claimed in claim 17, the method that wherein forms this conductive material layer on this substrate comprises physical vaporous deposition or chemical vapour deposition technique.
19. the method for the metal level in the formation thin film transistor array substrate as claimed in claim 16, the method that forms this plating seed layer on this substrate comprises:
On this substrate, form an insulation material layer;
On this insulation material layer, form a photoresist layer of patterning;
With this photoresist layer is mask, and this insulation material layer of etching is so that this insulation material layer exposes this substrate of part;
On this substrate, form one first conductive material layer comprehensively; And
Remove this photoresist layer and this first conductive material layer that is positioned on this photoresist layer, to form this first plating seed layer.
20. the manufacture method of thin film transistor array substrate as claimed in claim 19, the method that wherein forms this insulation material layer on this substrate comprises chemical vapour deposition technique.
21. the manufacture method of thin film transistor array substrate as claimed in claim 19, the method that wherein forms this first conductive material layer comprises physical vaporous deposition.
22. the manufacture method of thin film transistor array substrate as claimed in claim 19 wherein removes this photoresist layer and comprises the photoresist lift off method with the method that is positioned at this first conductive material layer on this photoresist layer.
23. the method for the metal level in the formation thin film transistor array substrate as claimed in claim 16, on this substrate, form this plating seed layer comprehensively, and after electroplating this metal level of formation, more comprise this metal level and this plating seed layer are carried out photoetching process and etch process.
24. the method for the metal level in the formation thin film transistor array substrate as claimed in claim 23, the method that wherein forms this plating seed layer comprises physical vaporous deposition or chemical vapour deposition technique.
25. the method for the metal level in the formation thin film transistor array substrate as claimed in claim 16, wherein the material of this metal level comprises copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100728397A CN100401466C (en) | 2005-05-23 | 2005-05-23 | Manufacturing method of thin-film transistor array substrate and metal layer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100728397A CN100401466C (en) | 2005-05-23 | 2005-05-23 | Manufacturing method of thin-film transistor array substrate and metal layer |
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| Publication Number | Publication Date |
|---|---|
| CN1870216A CN1870216A (en) | 2006-11-29 |
| CN100401466C true CN100401466C (en) | 2008-07-09 |
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| CN105428245B (en) | 2016-01-26 | 2019-03-01 | 京东方科技集团股份有限公司 | Dot structure and preparation method thereof, array substrate and display device |
| CN108899756B (en) * | 2018-06-06 | 2020-04-28 | 青岛海信宽带多媒体技术有限公司 | Method for depositing metal electrode |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1305223A (en) * | 1999-12-08 | 2001-07-25 | 三星Sdi株式会社 | Method of manufacturing thin film transistor |
| US20040051180A1 (en) * | 2002-09-17 | 2004-03-18 | Masaki Kado | Interconnect, interconnect forming method, thin film transistor, and display device |
| US20040157352A1 (en) * | 2000-11-13 | 2004-08-12 | Kim Soo Kil | Method for forming thin film and method for fabricating liquid crystal display using the same |
| CN1529545A (en) * | 2003-09-29 | 2004-09-15 | 威盛电子股份有限公司 | Selective electroplating method |
| US20040203181A1 (en) * | 2003-04-11 | 2004-10-14 | Quanyuan Shang | Methods to form metal lines using selective electrochemical deposition |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1305223A (en) * | 1999-12-08 | 2001-07-25 | 三星Sdi株式会社 | Method of manufacturing thin film transistor |
| US20040157352A1 (en) * | 2000-11-13 | 2004-08-12 | Kim Soo Kil | Method for forming thin film and method for fabricating liquid crystal display using the same |
| US20040051180A1 (en) * | 2002-09-17 | 2004-03-18 | Masaki Kado | Interconnect, interconnect forming method, thin film transistor, and display device |
| US20040203181A1 (en) * | 2003-04-11 | 2004-10-14 | Quanyuan Shang | Methods to form metal lines using selective electrochemical deposition |
| CN1529545A (en) * | 2003-09-29 | 2004-09-15 | 威盛电子股份有限公司 | Selective electroplating method |
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