TW201327757A - Pixel array substrate - Google Patents
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Description
本發明是有關於一種基板，且特別是關於一種畫素陣列基板。This invention relates to a substrate, and more particularly to a pixel array substrate.
現今社會多媒體技術相當發達，多半受惠於半導體元件與顯示器的進步。就顯示器而言，具有高畫質、低消耗功率、無輻射等優越特性之薄膜電晶體液晶顯示器已逐漸成為市場之主流。Today's social multimedia technology is quite developed, and most of them benefit from the advancement of semiconductor components and displays. As far as the display is concerned, a thin film transistor liquid crystal display having superior characteristics such as high image quality, low power consumption, and no radiation has gradually become the mainstream of the market.
隨著人們對於顯示器高解析度的訴求，顯示器內各畫素(pixel)的面積勢必要縮小，而顯示器之元件面積也勢必要減縮。然而，如圖1所示，目前市面上的電容設計大多為平面式的結構。具體而言，藉由在基板110上形成一第一電極112與一第二電極116，並配置一絕緣層114於第一電極112與第二電極116之間，以形成一電容結構，其中電容結構之電荷儲存量的大小取決於電容相對於基板110的表面所佔之面積大小。With the demand for high resolution of the display, the area of each pixel in the display must be reduced, and the component area of the display is also bound to shrink. However, as shown in Figure 1, the current capacitive design on the market is mostly a planar structure. Specifically, a first electrode 112 and a second electrode 116 are formed on the substrate 110, and an insulating layer 114 is disposed between the first electrode 112 and the second electrode 116 to form a capacitor structure, wherein the capacitor The amount of charge storage of the structure depends on the area occupied by the capacitance relative to the surface of the substrate 110.
因此，像是有機發光二極體(Organic Light Emitting Diode,OLED)顯示器，在對應每個畫素需要更多的薄膜電晶體數量時，欲得到高解析度，則增加電容平面面積勢必變得相當困難，而在電容平面面積無法縮小的情況下，為了得到可維持正常顯示畫面之電荷儲存量，提高畫面解析度將變得困難。另一方面，像是電子紙(Electronic paper)顯示器需要較大的電容設計以維持顯示畫面的灰階，此時，受限於電荷儲存量的要求而無法縮小顯示器的畫素面積，因而使顯示器的解析度受限。Therefore, for an Organic Light Emitting Diode (OLED) display, when a larger number of thin film transistors is required for each pixel, in order to obtain a high resolution, increasing the capacitance plane area is bound to become equivalent. Difficult, and when the area of the capacitor plane cannot be reduced, it is difficult to improve the resolution of the screen in order to obtain the amount of charge storage that can maintain the normal display screen. On the other hand, an electronic paper display, such as an electronic paper, requires a large capacitance design to maintain the gray scale of the display. At this time, the pixel area of the display cannot be reduced due to the limitation of the amount of charge storage, thereby making the display The resolution is limited.
本發明提供一種畫素陣列基板，其具有優良的電荷儲存量。The present invention provides a pixel array substrate which has an excellent charge storage amount.
本發明之一實施例提供一種畫素陣列基板，其包括一基板、多條掃描線、多條資料線、多條共用線、多個電容、多個主動元件以及多個畫素電極。基板具有一表面。多條掃描線、多條資料線與多條共用線配置於基板上。多個電容配置於基板上且耦接於共用線，其中各電容的上電極相對表面具有起伏。多個主動元件配置於基板上。多個畫素電極配置於基板上，其中每一畫素電極分別透過不同的主動元件與對應之掃描線及資料線電性連接。An embodiment of the present invention provides a pixel array substrate including a substrate, a plurality of scan lines, a plurality of data lines, a plurality of common lines, a plurality of capacitors, a plurality of active elements, and a plurality of pixel electrodes. The substrate has a surface. A plurality of scan lines, a plurality of data lines, and a plurality of common lines are disposed on the substrate. The plurality of capacitors are disposed on the substrate and coupled to the common line, wherein the upper electrodes of the capacitors have undulations on opposite surfaces. A plurality of active components are disposed on the substrate. The plurality of pixel electrodes are disposed on the substrate, wherein each of the pixel electrodes is electrically connected to the corresponding scan line and the data line through different active components.
在本發明之一實施例中，前述之各電容的上電極相對表面的最大高低差為50奈米至2000奈米。In an embodiment of the invention, the maximum height difference of the opposing surfaces of the capacitors is 50 nm to 2000 nm.
在本發明之一實施例中，前述之各電容的上電極垂直於表面的剖面呈波浪狀。In an embodiment of the invention, the upper electrode of each of the capacitors has a wavy cross section perpendicular to the surface.
在本發明之一實施例中，前述之畫素陣列基板，其中從垂直表面的方向觀之，各電容的上電極具有互相平行的多條凹陷區。In an embodiment of the invention, the pixel array substrate, wherein the upper electrode of each capacitor has a plurality of recessed regions parallel to each other, viewed from a direction of a vertical surface.
在本發明之一實施例中，前述之畫素陣列基板，其中從垂直表面的方向觀之，各電容的上電極具有多個點狀凹陷區。In an embodiment of the invention, the pixel array substrate described above, wherein the upper electrode of each capacitor has a plurality of dot-shaped recessed regions as viewed from a direction of a vertical surface.
在本發明之一實施例中，前述之主動元件的通道的材質為低溫多晶矽或非晶矽。In an embodiment of the invention, the channel of the active element is made of low temperature polycrystalline germanium or amorphous germanium.
本發明之另一實施例提供一種畫素陣列基板，其包括一基板、一第一絕緣層、多個主動元件、多條第一訊號線、多個下電極、多條共用線、一第二絕緣層、多條第二訊號線、多個上電極、一第三絕緣層以及多個畫素電極。第一絕緣層配置於基板上，且具有多個凹槽。各主動元件之一部分埋置於第一絕緣層中或全部配置於第一絕緣層上。多條第一訊號線、多個下電極與多條共用線配置於第一絕緣層上。各個下電極的一部份位於至少一個凹槽中，且各個共用線連接下電極。第二絕緣層覆蓋第一絕緣層、第一訊號線、下電極與共用線，且位於各主動元件的閘極與源汲極之間。多條第二訊號線與多個上電極配置於第二絕緣層上，其中上電極與下電極對應地耦合為多個電容。第三絕緣層覆蓋第二絕緣層、第二訊號線與上電極，且具有多個接觸窗開口。多個畫素電極配置於第三絕緣層上，各畫素電極通過一個接觸窗開口電性連接對應的主動元件的汲極。Another embodiment of the present invention provides a pixel array substrate including a substrate, a first insulating layer, a plurality of active components, a plurality of first signal lines, a plurality of lower electrodes, a plurality of common lines, and a second An insulating layer, a plurality of second signal lines, a plurality of upper electrodes, a third insulating layer, and a plurality of pixel electrodes. The first insulating layer is disposed on the substrate and has a plurality of grooves. One of the active elements is partially embedded in the first insulating layer or entirely disposed on the first insulating layer. The plurality of first signal lines, the plurality of lower electrodes and the plurality of common lines are disposed on the first insulating layer. A portion of each of the lower electrodes is located in at least one of the grooves, and each of the common lines is connected to the lower electrode. The second insulating layer covers the first insulating layer, the first signal line, the lower electrode and the common line, and is located between the gate of each active element and the source drain. The plurality of second signal lines and the plurality of upper electrodes are disposed on the second insulating layer, wherein the upper electrode and the lower electrode are correspondingly coupled to the plurality of capacitors. The third insulating layer covers the second insulating layer, the second signal line and the upper electrode, and has a plurality of contact openings. The plurality of pixel electrodes are disposed on the third insulating layer, and each of the pixel electrodes is electrically connected to the drain of the corresponding active component through a contact window opening.
在本發明之一實施例中，前述之各凹槽的深度為50奈米至2000奈米。In an embodiment of the invention, each of the aforementioned grooves has a depth of from 50 nanometers to 2,000 nanometers.
在本發明之一實施例中，前述之第一絕緣層在具有凹槽的部分的剖面呈波浪狀。In an embodiment of the invention, the first insulating layer has a wavy cross section in a portion having a groove.
在本發明之一實施例中，前述之畫素陣列基板，其中各個下電極覆蓋的凹槽為互相平行的條狀凹槽。In an embodiment of the invention, in the pixel array substrate, the grooves covered by the respective lower electrodes are strip-shaped grooves parallel to each other.
在本發明之一實施例中，前述之畫素陣列基板，其中各個下電極覆蓋的凹槽為多個點狀凹槽。In an embodiment of the invention, in the pixel array substrate, the groove covered by each of the lower electrodes is a plurality of dot-shaped grooves.
在本發明之一實施例中，前述之主動元件的通道的材質為低溫多晶矽或非晶矽。In an embodiment of the invention, the channel of the active element is made of low temperature polycrystalline germanium or amorphous germanium.
在本發明之一實施例中，前述之各個上電極電性連接對應的主動元件的汲極。In an embodiment of the invention, each of the foregoing upper electrodes is electrically connected to the drain of the corresponding active component.
在本發明之一實施例中，前述之第一絕緣層係為一單層或多層結構。In an embodiment of the invention, the first insulating layer is a single layer or a multilayer structure.
基於上述，在本發明之畫素陣列基板中，增加了電容在垂直於基板的方向上的面積，進而增加電荷儲存量。因此，在高解析度的需求使得畫素尺寸微縮的情況下，可減少電容在基板上所佔的面積以達到相同的開口率。也就是說，在不需要犧牲開口率的情況下即可提升電荷儲存量。換言之，在相同的畫素尺寸下，可增加開口率而提升顯示器亮度。或是在相同亮度下，因為開口率的提升而可減少背光亮度。另一方面，在維持相同的電荷儲存量下，可減少電容在基板上所佔的面積，使畫素尺寸微縮，提高顯示器的解析度。Based on the above, in the pixel array substrate of the present invention, the area of the capacitance in the direction perpendicular to the substrate is increased, thereby increasing the charge storage amount. Therefore, in the case where the demand for high resolution is such that the pixel size is reduced, the area occupied by the capacitance on the substrate can be reduced to achieve the same aperture ratio. That is to say, the charge storage amount can be increased without sacrificing the aperture ratio. In other words, at the same pixel size, the aperture ratio can be increased to increase the brightness of the display. Or at the same brightness, the brightness of the backlight can be reduced because of the increase in aperture ratio. On the other hand, while maintaining the same charge storage amount, the area occupied by the capacitance on the substrate can be reduced, the pixel size can be reduced, and the resolution of the display can be improved.
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.
圖2A至圖2G為本發明一實施例之畫素陣列基板的製作流程剖面示意圖。2A to 2G are schematic cross-sectional views showing a process of fabricating a pixel array substrate according to an embodiment of the present invention.
請參照圖2A，於一基板210之一表面S上依序地形成一第一子絕緣層212以及一第二子絕緣層214。在本實施例中，基板210例如是玻璃基板，第一子絕緣層212的材質例如是氮化矽(SiNx)，而第二子絕緣層214的材質例如是矽氧化物(SiOx)，但本發明不以此為限。Referring to FIG. 2A, a first sub-insulating layer 212 and a second sub-insulating layer 214 are sequentially formed on a surface S of a substrate 210. In this embodiment, the substrate 210 is, for example, a glass substrate, the material of the first sub-insulating layer 212 is, for example, tantalum nitride (SiN x ), and the material of the second sub-insulating layer 214 is, for example, tantalum oxide (SiO x ). However, the invention is not limited thereto.
請參照圖2B，於第二子絕緣層214上形成一通道材料層(未繪示)。此通道材料層的材質可為低溫多晶矽或是非晶矽。在本實施例中，通道層材料的材質為低溫多晶矽，其中多晶矽可以是藉由熱退火(annealing)將非晶矽轉變成多晶矽的材質。Referring to FIG. 2B, a channel material layer (not shown) is formed on the second sub-insulating layer 214. The material layer of the channel can be made of low temperature polycrystalline germanium or amorphous germanium. In this embodiment, the material of the channel layer material is a low temperature polysilicon, wherein the polysilicon may be a material that converts amorphous germanium into polycrystalline germanium by thermal annealing.
接著，圖案化此通道材料層而保留欲佈局通道的部分。並利用摻雜(doping)N型或P型摻質，以形成一源極摻雜區216b、一汲極摻雜區216c以及未摻雜摻質之一通道216a，其中通道216a配置於源極摻雜區216b以及汲極摻雜區216c之間。具體而言，若通道216a兩側之源極摻雜區216b以及汲極摻雜區216c摻雜之摻質為N型，則定義為N型金氧半導體(NMOS)電晶體。反之，則定義為P型金氧半導體(PMOS)電晶體。Next, the channel material layer is patterned to retain portions of the channel to be laid out. And doping doping N-type or P-type dopants to form a source doped region 216b, a drain doped region 216c, and one of the undoped dopant channels 216a, wherein the channel 216a is disposed at the source Between the doped region 216b and the drain doped region 216c. Specifically, if the source doped region 216b on both sides of the channel 216a and the dopant doped by the drain doped region 216c are N-type, it is defined as an N-type metal oxide semiconductor (NMOS) transistor. On the contrary, it is defined as a P-type metal oxide semiconductor (PMOS) transistor.
請參照圖2C，於第二子絕緣層214上形成一第三子絕緣層218，此第三子絕緣層218覆蓋通道216、源極摻雜區216b以及汲極摻雜區216c。此外，第一子絕緣層212、第二子絕緣層214以及第三子絕緣層218構成一多層結構之第一絕緣層220。Referring to FIG. 2C, a third sub-insulating layer 218 is formed on the second sub-insulating layer 214. The third sub-insulating layer 218 covers the channel 216, the source doping region 216b, and the drain doping region 216c. In addition, the first sub-insulating layer 212, the second sub-insulating layer 214, and the third sub-insulating layer 218 constitute a first insulating layer 220 of a multi-layer structure.
接著，蝕刻第二子絕緣層214以及第三子絕緣層218以形成凹槽U，並暴露出部分第一子絕緣層212，其中凹槽的深度DU為50奈米至2000奈米。在本實施例中，形成凹槽U的方式例如是藉由乾蝕刻(dry etching)或是濕蝕刻(wet etching)來蝕刻出類似波浪狀的圖形。當然，凹槽的數量以及形狀都無特殊限制。本實施例在欲佈局電容的區域以及基板210之間保留第一子絕緣層212，以避免第一子絕緣層212上下的材料互相干擾。具體而言，為製程方便，本實施例之第一子絕緣層212的材質可選用與第二子絕緣層214不同的材質，再搭配適當之蝕刻劑，使得在形成凹槽U之蝕刻過程中，第一子絕緣層212可做為蝕刻中止層。然而，本發明不以此為限，在其他實施例中，亦可以不用配置第一子絕緣層212。Next, the second sub-insulating layer 214 and the third sub-insulating layer 218 are etched to form the recess U, and a portion of the first sub-insulating layer 212 is exposed, wherein the recess has a depth D U of 50 nm to 2000 nm. In the present embodiment, the way of forming the recess U is, for example, etching a wavy pattern by dry etching or wet etching. Of course, the number and shape of the grooves are not particularly limited. In this embodiment, the first sub-insulating layer 212 is left between the area where the capacitor is to be laid out and the substrate 210 to prevent the materials above and below the first sub-insulating layer 212 from interfering with each other. Specifically, for the convenience of the process, the material of the first sub-insulating layer 212 of the embodiment may be different from the material of the second sub-insulating layer 214, and then matched with an appropriate etchant, so as to be in the etching process for forming the recess U. The first sub-insulating layer 212 can serve as an etch stop layer. However, the present invention is not limited thereto. In other embodiments, the first sub-insulating layer 212 may not be disposed.
請參照圖2D，於第一絕緣層220上形成多條第一訊號線(未繪示)、多個下電極224、多條共用線(未繪示)以及閘極222。各個下電極224的一部分位於至少一個凹槽U中。在本實施例中，第一訊號線、下電極224、共用線以及閘極222的材質可為金屬、合金或金屬疊層，但本發明不以此為限。Referring to FIG. 2D, a plurality of first signal lines (not shown), a plurality of lower electrodes 224, a plurality of common lines (not shown), and a gate 222 are formed on the first insulating layer 220. A portion of each of the lower electrodes 224 is located in at least one of the grooves U. In this embodiment, the material of the first signal line, the lower electrode 224, the common line, and the gate 222 may be a metal, an alloy, or a metal laminate, but the invention is not limited thereto.
請參照圖2E，形成一第二絕緣層230，以覆蓋第一絕緣層220、第一訊號線、下電極224、共用線以及閘極222。接著，形成接觸窗開口W1，此接觸窗開口W1貫穿第二絕緣層230以及第三子絕緣層218，並暴露出部份源極摻雜區216b以及汲極摻雜區216c。在本實施例中，形成接觸窗開口W1的方法例如是蝕刻，但本發明不以此為限。Referring to FIG. 2E, a second insulating layer 230 is formed to cover the first insulating layer 220, the first signal line, the lower electrode 224, the common line, and the gate 222. Next, a contact opening W1 is formed. The contact opening W1 penetrates through the second insulating layer 230 and the third sub-insulating layer 218, and exposes a portion of the source doping region 216b and the drain doping region 216c. In the present embodiment, the method of forming the contact opening W1 is, for example, etching, but the invention is not limited thereto.
請參照圖2F，於第二絕緣層230上形成多條第二訊號線(未繪示)、多個上電極244、源極242b以及汲極242c，其中源極242b以及汲極242c分別透過接觸窗開口W1與源極摻雜區216b以及汲極摻雜區216c電性連接。此時，多個主動元件240製作完成。在本實施例中，主動元件240部分埋置於第一絕緣層220中，且第二絕緣層230位於主動元件240的閘極222與源極242b以及汲極242c之間。在此，源極242b以及汲極242c被共同定義為源汲極。此外，上電極244與下電極224透過第二絕緣層230對應地耦合為多個電容C1。電容C1之上電極244相對基板210之表面S具有起伏。在本實施例中，電容C1之上電極244垂直於表面S的剖面呈波浪狀。此外，電容C1之上電極244相對表面S的最大高低差D為50奈米至2000奈米。Referring to FIG. 2F, a plurality of second signal lines (not shown), a plurality of upper electrodes 244, a source 242b, and a drain 242c are formed on the second insulating layer 230, wherein the source 242b and the drain 242c are respectively in contact with each other. The window opening W1 is electrically connected to the source doping region 216b and the drain doping region 216c. At this time, a plurality of active elements 240 are completed. In the present embodiment, the active device 240 is partially buried in the first insulating layer 220, and the second insulating layer 230 is located between the gate 222 and the source 242b of the active device 240 and the drain 242c. Here, the source 242b and the drain 242c are collectively defined as a source drain. In addition, the upper electrode 244 and the lower electrode 224 are correspondingly coupled to the plurality of capacitors C1 through the second insulating layer 230. The upper electrode 244 of the capacitor C1 has an undulation with respect to the surface S of the substrate 210. In the present embodiment, the cross section of the upper surface 244 of the capacitor C1 perpendicular to the surface S is wavy. In addition, the maximum height difference D between the electrode 244 and the surface S above the capacitor C1 is 50 nm to 2000 nm.
接著，形成一第三絕緣層250，以覆蓋第二絕緣層230、第二訊號線與上電極244，並可選擇性地將電容C1的波浪狀結構填平。在本實施例中，第三絕緣層250的材質例如是有機光阻(Organic photoresist)。此外，第三絕緣層250具有接觸窗開口W2。在本實施例中，形成接觸窗開口W2的方法例如是蝕刻，但本發明不以此為限。Next, a third insulating layer 250 is formed to cover the second insulating layer 230, the second signal line and the upper electrode 244, and can selectively fill the wavy structure of the capacitor C1. In this embodiment, the material of the third insulating layer 250 is, for example, an organic photoresist. Further, the third insulating layer 250 has a contact opening W2. In the present embodiment, the method of forming the contact opening W2 is, for example, etching, but the invention is not limited thereto.
請參照圖2G，於第三絕緣層250上形成多個畫素電極260，且畫素電極260通過接觸窗開口W2電性連接對應的主動元件240的汲極242c。至此，畫素陣列基板200即被完成。Referring to FIG. 2G, a plurality of pixel electrodes 260 are formed on the third insulating layer 250, and the pixel electrodes 260 are electrically connected to the drain 242c of the corresponding active device 240 through the contact window opening W2. So far, the pixel array substrate 200 is completed.
接下來將以此畫素陣列基板200之上視圖做進一步的描述。圖3為圖2G之畫素陣列基板的上視示意圖，且沿圖3中A-A’剖線之剖面為圖2G。Next, the above view of the pixel array substrate 200 will be further described. 3 is a top plan view of the pixel array substrate of FIG. 2G, and the cross section taken along the line A-A' in FIG. 3 is FIG. 2G.
請參照圖3與圖2G，本實施例之畫素陣列基板200包括具有一表面S之基板210以及配置基板210上之多條掃描線226、多條資料線246、多條共用線228、多個電容C1、多個主動元件240與多個畫素電極260。其中每條共用線228耦接於多個電容C1，且各條共用線228連接多個下電極224。此外，閘極222於基板210的正投影(未繪示)與通道216a於基板210的正投影(未繪示)重疊。另外，每一畫素電極260分別透過不同的主動元件240與對應之掃描線226及資料線246電性連接。在本實施例中，從垂直表面S的方向觀之，各電容C1的上電極244具有互相平行的多條凹陷區A1。Referring to FIG. 3 and FIG. 2G, the pixel array substrate 200 of the present embodiment includes a substrate 210 having a surface S, a plurality of scanning lines 226 disposed on the substrate 210, a plurality of data lines 246, and a plurality of common lines 228 and more. A capacitor C1, a plurality of active elements 240 and a plurality of pixel electrodes 260. Each of the common lines 228 is coupled to the plurality of capacitors C1, and each of the common lines 228 is coupled to the plurality of lower electrodes 224. In addition, an orthographic projection (not shown) of the gate 222 on the substrate 210 overlaps with an orthographic projection (not shown) of the channel 216a on the substrate 210. In addition, each of the pixel electrodes 260 is electrically connected to the corresponding scan line 226 and the data line 246 through different active elements 240. In the present embodiment, the upper electrode 244 of each capacitor C1 has a plurality of recessed regions A1 which are parallel to each other as viewed from the direction of the vertical surface S.
值得注意的是，本實施例之畫素陣列基板200利用互相平行的多條凹陷區A1增加電容C1垂直於基板210方向上的表面積，進而增加電荷儲存量。因此，本實施例之畫素陣列基板200可在相同的開口率下提升電荷儲存量。此外，本實施例之畫素陣列基板200亦可在相同之電荷儲存量下減少電容C1在基板210上所佔的面積，使畫素尺寸微縮，提高顯示器的解析度。It should be noted that the pixel array substrate 200 of the present embodiment increases the surface area of the capacitor C1 perpendicular to the substrate 210 by using a plurality of recessed regions A1 parallel to each other, thereby increasing the charge storage amount. Therefore, the pixel array substrate 200 of the present embodiment can increase the charge storage amount at the same aperture ratio. In addition, the pixel array substrate 200 of the embodiment can also reduce the area occupied by the capacitor C1 on the substrate 210 under the same charge storage amount, so that the pixel size is reduced, and the resolution of the display is improved.
另外，電容C1的上電極244除了可具有上述互相平行的多條凹陷區A1外，在其他實施例中，亦可以多個點狀凹陷區取代條狀凹陷區A1。圖4為本發明另一實施例之畫素陣列基板的上視示意圖。請參照圖4，本實施例之畫素陣列基板400與圖3中之畫素陣列基板300具有相似的結構，且相似的符號代表相似的構件且具有相似的作用，故不再贅述。惟二者差異處在於本實施例之畫素陣列基板400之電容C2的上電極244’具有多個點狀凹陷區A2。此外，多個點狀凹陷區A2亦具有上述互相平行的多條凹陷區A1的功能。舉例而言，多個點狀凹陷區A2可增加電容C2垂直於基板210方向上的表面積，進而增加電荷儲存量。此外，多個點狀凹陷區A2亦可在相同之電荷儲存量下減少電容C2在基板210上所佔的面積，使畫素尺寸微縮，提高顯示器的解析度。In addition, the upper electrode 244 of the capacitor C1 may have a plurality of dot-shaped recessed regions A1 instead of the plurality of dot-shaped recessed regions A1 in addition to the plurality of recessed regions A1 which are parallel to each other. 4 is a top plan view of a pixel array substrate according to another embodiment of the present invention. Referring to FIG. 4, the pixel array substrate 400 of the present embodiment has a similar structure to the pixel array substrate 300 of FIG. 3, and similar symbols represent similar components and have similar functions, and thus will not be described again. The difference between the two is that the upper electrode 244' of the capacitor C2 of the pixel array substrate 400 of the present embodiment has a plurality of dot-shaped recessed regions A2. Further, the plurality of dot-shaped recessed regions A2 also have the functions of the plurality of recessed regions A1 which are parallel to each other as described above. For example, the plurality of dot-shaped recessed regions A2 may increase the surface area of the capacitor C2 perpendicular to the direction of the substrate 210, thereby increasing the amount of charge storage. In addition, the plurality of dot-shaped recessed regions A2 can also reduce the area occupied by the capacitor C2 on the substrate 210 under the same charge storage amount, so that the pixel size is reduced, and the resolution of the display is improved.
此外，本發明之畫素陣列基板除了可具有上述低溫多晶矽之主動元件外，在其他實施例中，本發明之畫素陣列基板亦可具有非晶矽之主動元件。以下將以圖5A至圖5F、圖6與圖7做詳細的描述。In addition, the pixel array substrate of the present invention may have an amorphous active element in addition to the active element of the low temperature polysilicon described above. In other embodiments, the pixel array substrate of the present invention may also have an amorphous active element. The details will be described below with reference to FIGS. 5A to 5F, FIG. 6, and FIG.
圖5A至圖5F為本發明另一實施例之畫素陣列基板的製作流程剖面示意圖。5A to 5F are schematic cross-sectional views showing a process of fabricating a pixel array substrate according to another embodiment of the present invention.
請參照圖5A，於一基板510之一表面S’上形成一第一絕緣層520。接著，蝕刻第一絕緣層520以形成凹槽U’，並暴露出部分基板510，其中凹槽的深度DU’為50奈米至2000奈米。在本實施例中，形成凹槽U的方式例如是藉由乾蝕刻或是濕蝕刻來蝕刻出類似波浪狀的圖形。當然，凹槽的數量以及形狀都無特殊限制。Referring to FIG. 5A, a first insulating layer 520 is formed on one surface S' of a substrate 510. Next, the first insulating layer 520 is etched to form the recess U', and a portion of the substrate 510 is exposed, wherein the recess has a depth D U' of 50 nm to 2000 nm. In the present embodiment, the groove U is formed by, for example, etching a wavy pattern by dry etching or wet etching. Of course, the number and shape of the grooves are not particularly limited.
請參照圖5B，於第一絕緣層520上形成多條第一訊號線(未繪示)、多個下電極524、多條共電線(未繪示)以及閘極522。各個下電極524的一部分位於至少一個凹槽U’中。在本實施例中，第一訊號線、下電極524、共用線以及閘極522的材質可為金屬、合金或金屬疊層，但本發明不以此為限。Referring to FIG. 5B, a plurality of first signal lines (not shown), a plurality of lower electrodes 524, a plurality of common wires (not shown), and a gate 522 are formed on the first insulating layer 520. A portion of each of the lower electrodes 524 is located in at least one of the grooves U'. In this embodiment, the material of the first signal line, the lower electrode 524, the common line, and the gate 522 may be a metal, an alloy, or a metal laminate, but the invention is not limited thereto.
請參照圖5C，相繼形成一第二絕緣層530、一通道516以及一歐姆接觸圖案518於第一絕緣層520上，且位於閘極522上方。Referring to FIG. 5C, a second insulating layer 530, a channel 516, and an ohmic contact pattern 518 are formed on the first insulating layer 520 and above the gate 522.
請參照圖5D，於第二絕緣層530以及歐姆接觸圖案518上相繼形成多條第二訊號線(未繪示)、多個上電極544、源極542b以及汲極542c。此時，多個主動元件540製作完成。在本實施例中，主動元件540為底閘極結構，但本發明不以此為限。在其他實施例中，主動元件亦可以為頂閘極的結構，亦或任何熟悉此技藝者可對此結構稍做更動，故本發明並不限定主動元件之結構。在本實施例中，主動元件540全部配置於第一絕緣層520上，且該第二絕緣層530位於主動元件540的閘極522與源極542b以及汲極542c之間。在此，源極542b以及汲極542c被共同定義為源汲極。此外，上電極544與下電極524透過第二絕緣層530對應地耦合為多個電容C3，其中電容C3之上電極544相對基板510之表面S’具有起伏。在本實施例中，電容C3之上電極544垂直於表面S’的剖面呈波浪狀。此外，電容C3之上電極544相對表面S’的最大高低差D’為50奈米至2000奈米。Referring to FIG. 5D, a plurality of second signal lines (not shown), a plurality of upper electrodes 544, a source 542b, and a drain 542c are sequentially formed on the second insulating layer 530 and the ohmic contact pattern 518. At this time, a plurality of active elements 540 are completed. In this embodiment, the active component 540 is a bottom gate structure, but the invention is not limited thereto. In other embodiments, the active component may also be a top gate structure, or any one skilled in the art may modify the structure slightly. Therefore, the present invention does not limit the structure of the active component. In this embodiment, the active device 540 is all disposed on the first insulating layer 520, and the second insulating layer 530 is located between the gate 522 and the source 542b of the active device 540 and the drain 542c. Here, the source 542b and the drain 542c are collectively defined as a source drain. In addition, the upper electrode 544 and the lower electrode 524 are correspondingly coupled to the plurality of capacitors C3 through the second insulating layer 530, wherein the upper surface 544 of the capacitor C3 has an undulation relative to the surface S' of the substrate 510. In the present embodiment, the cross section of the upper surface of the capacitor C3 perpendicular to the surface S' is wavy. Further, the maximum height difference D' of the electrode 544 on the upper surface S' of the capacitor C3 is from 50 nm to 2,000 nm.
請參照圖5E，形成一第三絕緣層550，以覆蓋第二絕緣層530、第二訊號線與上電極544，並可選擇性地將電容C3的波浪狀結構填平。在本實施例中，第三絕緣層550的材質例如是有機光阻。此外，第三絕緣層550具有多個接觸窗開口W3。在本實施例中，形成接觸窗開口W3的方法例如是蝕刻或雷射剝除，但本發明不以此為限。Referring to FIG. 5E, a third insulating layer 550 is formed to cover the second insulating layer 530, the second signal line and the upper electrode 544, and selectively fill the wavy structure of the capacitor C3. In this embodiment, the material of the third insulating layer 550 is, for example, an organic photoresist. Further, the third insulating layer 550 has a plurality of contact opening W3. In the present embodiment, the method of forming the contact opening W3 is, for example, etching or laser stripping, but the invention is not limited thereto.
請參照圖5F，於第三絕緣層550上形成多個畫素電極560，且畫素電極560通過接觸窗開口W3電性連接對應的主動元件540的汲極542c。至此，畫素陣列基板500即被完成。Referring to FIG. 5F, a plurality of pixel electrodes 560 are formed on the third insulating layer 550, and the pixel electrodes 560 are electrically connected to the drains 542c of the corresponding active devices 540 through the contact window openings W3. At this point, the pixel array substrate 500 is completed.
接下來將以此畫素陣列基板500之上視圖做進一步的描述。圖6為圖5F之畫素陣列基板的上視示意圖，且沿圖6中A-A’剖線之剖面為圖5F。Next, the above view of the pixel array substrate 500 will be further described. Fig. 6 is a top plan view of the pixel array substrate of Fig. 5F, and the cross section taken along the line A-A' in Fig. 6 is Fig. 5F.
請參照圖6與圖5F，本實施例之畫素陣列基板500包括具有一表面S’之基板510以及配置基板510上之多條掃描線526、多條資料線546、多條共用線528、多個電容C3、多個主動元件540與多個畫素電極560。其中每條共用線528耦接於多個電容C3，且各條共用線528連接多個下電極524。此外，閘極522於基板510的正投影(未繪示)與通道516於基板510的正投影(未繪示)重疊。另外，每一畫素電極560分別透過不同的主動元件540與對應之掃描線526及資料線546電性連接。在本實施例中，從垂直表面S’的方向觀之，各電容C3的上電極544具有互相平行的多條凹陷區A3。Referring to FIG. 6 and FIG. 5F, the pixel array substrate 500 of the present embodiment includes a substrate 510 having a surface S′ and a plurality of scan lines 526 disposed on the substrate 510 , a plurality of data lines 546 , and a plurality of common lines 528 . A plurality of capacitors C3, a plurality of active elements 540 and a plurality of pixel electrodes 560. Each of the common lines 528 is coupled to the plurality of capacitors C3, and each of the common lines 528 is connected to the plurality of lower electrodes 524. In addition, an orthographic projection (not shown) of the gate 522 on the substrate 510 overlaps with an orthographic projection (not shown) of the channel 516 on the substrate 510. In addition, each of the pixel electrodes 560 is electrically connected to the corresponding scan line 526 and the data line 546 through different active elements 540. In the present embodiment, the upper electrode 544 of each capacitor C3 has a plurality of recessed regions A3 which are parallel to each other as viewed from the direction of the vertical surface S'.
值得注意的是，本實施例之畫素陣列基板500具有與圖3中之畫素陣列基板200相似的功能。舉例而言，畫素陣列基板500利用互相平行的多條凹陷區A3增加電容C3垂直於基板510方向上的表面積，進而增加電荷儲存量。因此，本實施例之畫素陣列基板500可在相同的開口率下提升電荷儲存量，或是在相同之電荷儲存量下減少電容C3在基板510上所佔的面積。換言之，本實施例之畫素陣列基板500在維持相同的電荷儲存量下，可藉由減少電容C3在基板510上所佔的面積，使畫素尺寸微縮，進而提高顯示器的解析度。It is to be noted that the pixel array substrate 500 of the present embodiment has a function similar to that of the pixel array substrate 200 of FIG. For example, the pixel array substrate 500 increases the surface area of the capacitor C3 perpendicular to the substrate 510 by using a plurality of recessed regions A3 parallel to each other, thereby increasing the charge storage amount. Therefore, the pixel array substrate 500 of the present embodiment can increase the charge storage amount at the same aperture ratio, or reduce the area occupied by the capacitor C3 on the substrate 510 at the same charge storage amount. In other words, the pixel array substrate 500 of the present embodiment can reduce the pixel size by reducing the area occupied by the capacitor C3 on the substrate 510 while maintaining the same charge storage amount, thereby improving the resolution of the display.
另外，電容C3的上電極544除了可具有上述互相平行的多條凹陷區A3外，在其他實施例中，亦可以多個點狀凹陷區取代條狀凹陷區A3。圖7為本發明另一實施例之畫素陣列基板的上視示意圖。請參照圖7，本實施例之畫素陣列基板700與圖6中之畫素陣列基板500具有相似的結構，且相似的符號具代表相似的構件且具有相似的作用，故不再贅述。惟二者差異處在於本實施例之畫素陣列基板700之電容C4的上電極544’具有多個點狀凹陷區A4。此外，多個點狀凹陷區A4亦具有上述互相平行的多條凹陷區A3的功能。舉例而言，多個點狀凹陷區A2可增加電容C2垂直於基板210方向上的表面積，進而增加電荷儲存量。此外，多個點狀凹陷區A2亦可在相同之電荷儲存量下減少電容C2在基板210上所佔的面積，使畫素尺寸微縮，提高顯示器的解析度。In addition, the upper electrode 544 of the capacitor C3 may have a plurality of dot-shaped recessed regions A3 instead of the plurality of recessed regions A3. FIG. 7 is a top plan view of a pixel array substrate according to another embodiment of the present invention. Referring to FIG. 7, the pixel array substrate 700 of the present embodiment has a similar structure to the pixel array substrate 500 of FIG. 6, and similar symbols have similar functions and have similar functions, and thus will not be described again. The difference between the two is that the upper electrode 544' of the capacitor C4 of the pixel array substrate 700 of the present embodiment has a plurality of dot-shaped recessed regions A4. Further, the plurality of dot-shaped recessed regions A4 also have the function of the plurality of recessed regions A3 which are parallel to each other as described above. For example, the plurality of dot-shaped recessed regions A2 may increase the surface area of the capacitor C2 perpendicular to the direction of the substrate 210, thereby increasing the amount of charge storage. In addition, the plurality of dot-shaped recessed regions A2 can also reduce the area occupied by the capacitor C2 on the substrate 210 under the same charge storage amount, so that the pixel size is reduced, and the resolution of the display is improved.
綜上所述，在本發明之畫素陣列基板中，增加了電容在垂直於基板的方向上的面積，進而增加電荷儲存量。因此，在高解析度的需求使得畫素尺寸微縮的情況下，可以不用犧牲畫素陣列基板的開口率，且在減少電容在基板上所佔的面積下達到優良的電荷儲存量。換言之，本發明實施例之畫素陣列基板在相同的畫素尺寸下，可增加開口率，進而提升顯示器亮度。或是在相同顯示器之亮度下，因為開口率的提升而可減少背光亮度。另一方面，在維持相同的電荷儲存量下，可減少電容在基板上所佔的面積，使畫素尺寸微縮，提高顯示器的解析度，進而適用於需要較大電荷儲存量之顯示器或是需要較多主動元件之顯示器，例如是電子紙或是有機發光二極體等顯示器。In summary, in the pixel array substrate of the present invention, the area of the capacitance in the direction perpendicular to the substrate is increased, thereby increasing the charge storage amount. Therefore, in the case where the demand for high resolution makes the pixel size shrink, it is possible to achieve an excellent charge storage amount without sacrificing the aperture ratio of the pixel array substrate and reducing the area occupied by the capacitance on the substrate. In other words, the pixel array substrate of the embodiment of the present invention can increase the aperture ratio at the same pixel size, thereby improving the brightness of the display. Or under the brightness of the same display, the brightness of the backlight can be reduced because of the increase in aperture ratio. On the other hand, while maintaining the same charge storage, the area occupied by the capacitor on the substrate can be reduced, the pixel size can be reduced, the resolution of the display can be improved, and the display can be applied to a display requiring a large charge storage capacity or A display with more active components, such as an electronic paper or an organic light emitting diode.
雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
110、210、510．．．基板110, 210, 510. . . Substrate
112．．．第一電極112. . . First electrode
116．．．第二電極116. . . Second electrode
114．．．絕緣層114. . . Insulation
200、400、500、700．．．畫素陣列基板200, 400, 500, 700. . . Pixel array substrate
212．．．第一子絕緣層212. . . First sub-insulation
214．．．第二子絕緣層214. . . Second sub-insulation
216a、516．．．通道216a, 516. . . aisle
216b．．．源極摻雜區216b. . . Source doping region
216c．．．汲極摻雜區216c. . . Bipolar doping zone
218．．．第三子絕緣層218. . . Third sub-insulation
220、520．．．第一絕緣層220, 520. . . First insulating layer
222、522．．．閘極222, 522. . . Gate
224、524．．．下電極224, 524. . . Lower electrode
226、526．．．掃描線226, 526. . . Scanning line
228、528．．．共用線228, 528. . . Shared line
230、530．．．第二絕緣層230, 530. . . Second insulating layer
240、540．．．主動元件240, 540. . . Active component
242b、542b．．．源極242b, 542b. . . Source
242c、542c．．．汲極242c, 542c. . . Bungee
244、244’、544、544’．．．上電極244, 244', 544, 544'. . . Upper electrode
246、546．．．資料線246, 546. . . Data line
250、550．．．第三絕緣層250, 550. . . Third insulating layer
260、560．．．畫素電極260, 560. . . Pixel electrode
518．．．歐姆接觸圖案518. . . Ohmic contact pattern
S、S’．．．表面S, S’. . . surface
U、U’．．．凹槽U, U’. . . Groove
DU、DU’．．．深度D U , D U' . . . depth
W1、W2、W3．．．開口W1, W2, W3. . . Opening
C1、C2、C3、C4．．．電容C1, C2, C3, C4. . . capacitance
D、D’．．．最大高低差D, D’. . . Maximum height difference
A-A’．．．剖線A-A’. . . Section line
A1、A2、A3、A4．．．凹陷區A1, A2, A3, A4. . . Sag area
圖1為習知技術之平面式電容結構的示意圖。1 is a schematic diagram of a planar capacitor structure of the prior art.
圖2A至圖2G為本發明一實施例之畫素陣列基板的製作流程上視示意圖。2A to 2G are schematic top views showing a manufacturing process of a pixel array substrate according to an embodiment of the present invention.
圖3為本發明一實施例之畫素陣列基板的上視示意圖。3 is a top plan view of a pixel array substrate according to an embodiment of the invention.
圖4為本發明另一實施例之畫素陣列基板的上視示意圖。4 is a top plan view of a pixel array substrate according to another embodiment of the present invention.
圖5A至圖5F為本發明另一實施例之畫素陣列基板的製作流程上視示意圖。5A to 5F are schematic top views showing a manufacturing process of a pixel array substrate according to another embodiment of the present invention.
圖6為本發明一實施例之畫素陣列基板的上視示意圖。FIG. 6 is a top plan view of a pixel array substrate according to an embodiment of the invention.
圖7為本發明另一實施例之畫素陣列基板的上視示意圖。FIG. 7 is a top plan view of a pixel array substrate according to another embodiment of the present invention.
200．．．畫素陣列基板200. . . Pixel array substrate
210．．．基板210. . . Substrate
212．．．第一子絕緣層212. . . First sub-insulation
214．．．第二子絕緣層214. . . Second sub-insulation
216a．．．通道216a. . . aisle
216b．．．源極摻雜區216b. . . Source doping region
216c．．．汲極摻雜區216c. . . Bipolar doping zone
218．．．第三子絕緣層218. . . Third sub-insulation
220．．．第一絕緣層220. . . First insulating layer
222．．．閘極222. . . Gate
224．．．下電極224. . . Lower electrode
230．．．第二絕緣層230. . . Second insulating layer
240．．．主動元件240. . . Active component
242b．．．源極242b. . . Source
242c．．．汲極242c. . . Bungee
244．．．上電極244. . . Upper electrode
250．．．第三絕緣層250. . . Third insulating layer
260．．．畫素電極260. . . Pixel electrode
S．．．表面S. . . surface
U．．．凹槽U. . . Groove
DU．．．深度D U . . . depth
W1、W2．．．開口W1, W2. . . Opening
C1．．．電容C1. . . capacitance
D．．．最大高低差D. . . Maximum height difference
Claims (14)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100149591A TWI460840B (en) | 2011-12-29 | 2011-12-29 | Pixel array substrate |
| CN201210099730.2A CN102623451B (en) | 2011-12-29 | 2012-04-06 | Pixel array substrate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100149591A TWI460840B (en) | 2011-12-29 | 2011-12-29 | Pixel array substrate |
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| TW201327757A true TW201327757A (en) | 2013-07-01 |
| TWI460840B TWI460840B (en) | 2014-11-11 |
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| CN104280160B (en) * | 2013-07-03 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Pressure sensor and forming method thereof |
| TWI595299B (en) * | 2014-01-23 | 2017-08-11 | 元太科技工業股份有限公司 | Pixel array |
| KR102304725B1 (en) * | 2014-10-16 | 2021-09-27 | 삼성디스플레이 주식회사 | Thin film transistor array substrate, method of manufacturing thereof and organic light-emitting display including the same |
| CN105226046A (en) * | 2015-10-13 | 2016-01-06 | 格科微电子（上海）有限公司 | Metal-insulator-metal capacitor and preparation method thereof |
| CN105304609B (en) * | 2015-10-13 | 2019-12-17 | 格科微电子（上海）有限公司 | Metal layer-insulating layer-metal layer capacitor and manufacturing method thereof |
| CN106298803A (en) * | 2016-08-18 | 2017-01-04 | 深圳市华星光电技术有限公司 | Array base palte and preparation method thereof, display panels |
| CN108806572A (en) * | 2017-05-05 | 2018-11-13 | 元太科技工业股份有限公司 | Dot structure |
| CN108447874B (en) * | 2018-03-22 | 2019-10-29 | 绵阳京东方光电科技有限公司 | Array substrate and its manufacturing method, display panel, electronic device |
| CN110071163B (en) * | 2019-05-06 | 2021-07-06 | 深圳市华星光电半导体显示技术有限公司 | Organic light emitting display panel |
| CN110718556A (en) * | 2019-08-29 | 2020-01-21 | 福建华佳彩有限公司 | Flexible array substrate and manufacturing method |
| CN110690256B (en) * | 2019-08-29 | 2023-02-03 | 福建华佳彩有限公司 | Flexible TFT substrate and manufacturing method thereof |
| CN110690257A (en) * | 2019-08-29 | 2020-01-14 | 福建华佳彩有限公司 | TFT array substrate and manufacturing method thereof |
| CN111129028A (en) * | 2019-12-12 | 2020-05-08 | 福建华佳彩有限公司 | Array substrate and manufacturing method thereof |
| CN113690253A (en) * | 2021-08-13 | 2021-11-23 | Tcl华星光电技术有限公司 | Array substrate, manufacturing method of array substrate and display panel |
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| KR100760142B1 (en) * | 2005-07-27 | 2007-09-18 | 매그나칩 반도체 유한회사 | Stacked pixel for high resolution cmos image sensors |
| CN101207140B (en) * | 2007-04-24 | 2010-06-02 | 友达光电股份有限公司 | Array substrate and manufacturing method thereof |
| TWI348765B (en) * | 2007-08-29 | 2011-09-11 | Au Optronics Corp | Pixel structure and fabricating method for thereof |
| CN100530570C (en) * | 2007-10-09 | 2009-08-19 | 友达光电股份有限公司 | Indicator element and manufacturing method therefor |
| TWI360708B (en) * | 2007-12-17 | 2012-03-21 | Au Optronics Corp | Pixel structure, display panel, elecro-optical app |
| CN100521190C (en) * | 2007-12-27 | 2009-07-29 | 友达光电（苏州）有限公司 | Pixel structure having concave-convex line structures and method for making the same |
| US7948018B2 (en) * | 2008-04-24 | 2011-05-24 | Omnivision Technologies, Inc. | Multilayer image sensor structure for reducing crosstalk |
| CN102023428B (en) * | 2009-09-23 | 2013-05-08 | 北京京东方光电科技有限公司 | TFT-LCD array substrate and method for manufacturing the same |
| CN102156370A (en) * | 2010-11-22 | 2011-08-17 | 友达光电股份有限公司 | Pixel array substrate and display panel |
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| CN102623451A (en) | 2012-08-01 |
| CN102623451B (en) | 2015-02-25 |
| TWI460840B (en) | 2014-11-11 |
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