CN102610537B - Method for low-temperature solid bonding of semiconductor device - Google Patents
Method for low-temperature solid bonding of semiconductor device Download PDFInfo
- Publication number
- CN102610537B CN102610537B CN201210086084.6A CN201210086084A CN102610537B CN 102610537 B CN102610537 B CN 102610537B CN 201210086084 A CN201210086084 A CN 201210086084A CN 102610537 B CN102610537 B CN 102610537B
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- Prior art keywords
- micropin
- semiconductor device
- bonding
- copper
- low temperature
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8336—Bonding interfaces of the semiconductor or solid state body
- H01L2224/83365—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83897—Mechanical interlocking, e.g. anchoring, hook and loop-type fastening or the like
Abstract
The invention discloses a method for the low-temperature solid bonding of a semiconductor device. The method comprises the following steps: 1) selecting at least two elements to be bonded of electric interconnection pads which are matched with each other; 2), forming copper microneedle cone groups on a plurality of pads of one element to be bonded; 3) forming salient points with at least the surfaces provided with low-hardness second metal points on a plurality of pads of the other element to be bonded; 4) contacting the salient points with the copper microneedle cone groups, heating the contact parts of the salient points and the copper microneedle cone groups to be a first temperature, and applying bonding pressure so as to electrically inter connect and bond the salient points and the copper microneedle cone groups. Compared with the prior art, the method has the advantages that in the technique process, the temperature does not need to be heated to be higher than the melting point of soldering flux so as to melt the soldering flux, so that thermal damage to the device can be avoided, and the interconnection density and the reliability of the product can be improved by the solid bonding, the interface reaction is controllable, and organic matters such as scaling powder and the like are not needed, so that the technique process is simplified.
Description
Technical field
The present invention relates to semiconductor die package field, particularly a kind of method of semiconductor device low temperature solid-state bonding.
Background technology
The electrical interconnection technology of semiconductor die package is the core technology of encapsulation, the innovation of electrical interconnection technology is the key of microelectric technique development, traditional melting bonding makes the metal molten at bonding point place soak bonding point both sides by the control of temperature, bonding point solidification after cooling, thus obtain good welding.The melting bonding technologies such as traditional reflow welding need more than heating temperatures to solder melt point, and high temperature environment can produce the impact of very severe on some chip and substrate, greatly reduce the reliability of product.The plumbous salient point of the height used till today in the Flip Chip Bond Technique of chip to base plate for packaging needs the lead used environmental danger, and the lead-free solder substituted there is no the welding temperature that method reaches identical or lower with it.The method of fusion welding needs the crossover phenomenon preventing from occurring between solder joint simultaneously.
In melting bonding, in order to obtain desirable bond strength, often need to use the organic substances such as scaling powder.Scaling powder needs to be added in combined at least one on the surface, and scaling powder comprises matchmaker's liquid and activator.After welding completes, need to remove solder flux or flux residue, generally include and use solvent clean packaging part, or through baking process, with the solvent of volatile residue or lower boiling solder flux or flux residue.The using and remove residue and will expend certain production time of scaling powder, reduce production efficiency, and when chip and chip chamber, or time space between chip and substrate is more and more less, flux residue is more difficult to be removed completely, and then brings impact to product reliability.
Seek the trend that more and more lower welding temperature has been chip interconnects technical development.Existing lot of documents and patent describe the chip of non-melt state realization to substrate or chip to the interconnection process of chip-stack.Comprising the monometallic or alloy, the multiple technologies such as mechanical means embedding metal derby or metal salient point, active reaction layer, nano particle low-temperature sintering etc. that utilize low melting point.Generally speaking, solid-state electrical interconnection can significantly improve interconnection density, without the need to scaling powder, and can eliminate the excessive interfacial reaction in melting process, and the reduction of technological temperature makes technological process and production cost also be reduced.
The solid-state bonding of copper-copper has multiple report, surface-activated bond (SAB) technology is the key point of copper-copper bonding, copper surface for realizing surface-activated bond general through meticulous chemico-mechanical polishing to reach nanoscale evenness, the approach obtaining overactive metal surface comprises by ar atmo, ion or plasma treatment.After oxide on surface and pollutant are eliminated, the chip or the crystal column surface that complete activation need vacuum protection to control the speed be again oxidized, and complete Direct Bonding under higher vacuum degree.Comprise that copper-copper is solid-state to be bonded in the interior a series of processing technologys of high-flatness metal-metal characteristics of Direct Wafer Bonded to wafer based on surface active and to have quite high requirement, and be often used for wafer level interconnection.
Summary of the invention
The object of the invention is a kind of method providing semiconductor device low temperature solid-state bonding, need more than heating temperatures to solder melt point to solve fusion bonding method of the prior art, fire damage can be produced like this to device, and in fusion weld, sprawling of solder makes solder be difficult to remove completely, and there are the technical matters of excessive interfacial reaction.
The object of the invention is achieved through the following technical solutions:
A method for semiconductor device low temperature solid-state bonding, comprises the following steps:
1) at least two elements to be bonded of the electrical interconnection pad with coupling are mutually selected;
2) on multiple pads of an element to be bonded, form copper micropin cone group;
3) on multiple pads of another element to be bonded, form at least surface be provided with the salient point of soft second metal level;
4) described salient point is bored group with described copper micropin to mate, and make described salient point bore group with described copper micropin to contact, the contact portion that described salient point and described copper micropin bore group is heated to the first temperature, applies bonding pressure and make described salient point and described copper micropin bore group's electrical interconnection bonding.
Further, described copper micropin cone group is formed in bond pad surface by chemical deposition, electrodeposition process or vapour deposition process.
Further, the height of described copper micropin cone group is 1 μm-5 μm.Further, step 2) also comprise: on described copper micropin cone group surface, antioxidation coating is set.
Further, described antioxidation coating is arranged on described copper micropin cone group surface by electrodeposition process or vapour deposition process.
Further, described antioxidation coating comprises metal simple-substance or the alloy of Au, Pt, Ag or Pd.
Further, the thickness of described antioxidation coating is 5nm-50nm.
Further, described bonding pressure is 1-30 MPa.
Further, the time applying bonding pressure in step 4) is 10 s-20 min.
Further, the material of described second metal level comprises indium, tin, indium alloy or ashbury metal.
Further, described second metal level is arranged on described bump surface by electrodeposition process, chemical deposition, vapour deposition process or coating process.
Further, described first temperature is lower than the fusing point of described second metal level.
Further, the micropin cone height on same pad is basically identical.
Compared with prior art, technical process of the present invention does not need solder fusing, can avoid producing fire damage to device, and solid-state bonding can improve interconnection density and product reliability, interfacial reaction is controlled, thus simplifies technological process without the need to organic substances such as scaling powders.
Accompanying drawing explanation
Fig. 1 is copper micropin of the present invention cone group and salient point cutaway view before bonding.
Embodiment
Below in conjunction with embodiment, describe the present invention in detail.
Refer to Fig. 1, the method for semiconductor device low temperature solid-state bonding of the present invention, comprises the following steps:
1) at least two elements to be bonded of the electrical interconnection pad with coupling are mutually selected;
2) on multiple pads of an element to be bonded, form copper micropin cone group 110;
3) on multiple pads of another element to be bonded, form at least surface be provided with the salient point 130 of soft second metal level;
4) salient point and copper micropin are bored group to mate, and make salient point and copper micropin bore group to contact, the contact portion that salient point and copper micropin bore group is heated to the first temperature, apply bonding pressure and make salient point and copper micropin bore group's electrical interconnection bonding.Wherein, step 2) adjustable with the order of step 3).
Further, copper micropin cone group is formed in bond pad surface by chemical deposition, electrodeposition process or vapour deposition process.The height of copper micropin cone group is 1 μm-5 μm.The size of copper pin cone of the present invention is larger, can reduce the requirement of the surface smoothness to salient point.Copper micropin cone height of the present invention is controlled, uses different parameters can obtain different height, and micropin cone height on same pad is basically identical.
Further, also antioxidation coating 120 can be set on copper micropin cone group surface.Antioxidation coating 120 is arranged on copper micropin cone group 110 surface by electrodeposition process or vapour deposition process.Antioxidation coating comprises metal simple-substance or the alloy of Au, Pt, Ag or Pd.The thickness of antioxidation coating is 5nm-50nm, and antioxidation coating does not change the surface topography of pin cone.
Further, bonding pressure can be 1-30 MPa, and the size of bonding pressure is determined by bonding temperature.
Further, the time applying bonding pressure in step 4) is 10 s-20 min.The size applying the material of time by the second metal level of bonding pressure, the first temperature and bonding pressure determines.
Further, the material of the second metal level comprises indium, tin, indium alloy or ashbury metal.Second metal level is arranged on bump surface by electrodeposition process, chemical deposition, vapour deposition process or coating process.
Further, the first temperature is lower than the fusing point of the second metal level.The selection of the first temperature is determined by the material of the second metal level and the size of bonding pressure.First temperature can selecting lower than in the scope of fusing point 5-100 DEG C of the second metal level.
Embodiment 1
bare chip with I/O pad is formed by the technique such as standard photolithography patterning, sputtering sedimentation and electrochemical deposition the Sn layer of the lower metal layer (UBM) of salient point, copper pillar bump, Ni barrier layer and bump surface, and typical copper pillar bump is of a size of diameter 60 μm, height 40 μm.Typical Ni barrier layer thickness is about 1 μm.Typical Sn layer thickness is 3-5 μm, and difference in height is less than 0.5 μm.Prepare copper micropin cone group and surface anti-oxidation Au layer at the welding disking area of upside-down mounting substrate by chemical deposition or electrochemical deposition, pin cone height can be 1 μm-5 μm, in this example, pin cone height about 5 μm, Au thickness can be 5nm-50nm, in this example, and Au thickness about 10 nm.The Au coating of this thickness can not have an impact to pin taper looks.The chip and substrate face opposite that remove bump surface oxide layer with pickling to be fixed on flip-chip bonder and to aim at, the bonding temperature of rapid temperature increases to 190 DEG C, and applied the equivalent static pressure of 1-30 MPa by bonder simultaneously, in this example, equivalence static pressure is 10 Mpa, keeps 10 s-20 min, in this example, retention time is 3min, completes bonding.In the process of bonding, copper micropin bore spine enters Sn block, and Sn layer at high temperature hardness significantly declines, creep rate is accelerated, and becomes to inlay with pin taper by plastic deformation, forms mechanical bond, and copper micropin cone is very fast with Sn block interfacial reaction, can form enough interfacial reactions.
Embodiment 2
In front with I/O pad, the back side with the lower metal layer (UBM) and the Sn layer that are formed salient point by interconnecting silicon through holes (TSV) to the bare chip front I/O pad of device side, typical Sn layer thickness is 2-5 μm, and difference in height is less than 0.5 μm.Chip has been thinned to less than 100 μm usually, polishes overleaf and exposed TSV fills metal surface prepares copper micropin cone group and surface anti-oxidation layer gold, pin cone height about 3-5 μm, Au thickness about 10 nm.After using plasma to remove surface oxide layer and contamination particle, two panels or multi-disc preparation are had that the silicon chip of this structure is stacking to be fixed in bonder, be warming up to the bonding temperature of 190 DEG C, and applied the equivalent static pressure of 10 MPa by bonder simultaneously, keep 3min to complete stacking bonding.
Embodiment 3
On the surface-pasted welding disking area metal derby of ball grid array (BGA) type, copper micropin cone layer and surface anti-oxidation Au layer is prepared, pin cone height about 3-5 μm, golden thickness about 10 nm at printed substrate (PCB).Pickling processes is carried out to remove solder ball surface oxide layer by being implanted with the BGA package body of size at 300-800 μm of Sn alloys welding balls, and aim at bonder internal fixtion with PCB, be warming up to the bonding temperature of 190 DEG C, and applied the equivalent static pressure of 10 MPa by bonder simultaneously, keep 3min to complete stacking bonding.
Wherein, stud bump material can be the Ni of electro-deposition and be not limited to copper, and the Sn layer of bump surface then can select the soft metals such as In, or other have the alloy compared with soft.For chip to the flip-chip interconnection of substrate and multi-chip stacking perpendicular interconnection, the position of salient point side and pin cone flank can exchange.Can not use thermocompression bonding machine, and use miscellaneous equipment to realize the content of the claims in the present invention, be easy to do to one skilled in the art.Equally, the order of the cooperation of temperature requirement and pressure in bonding process, also can adjust according to the needs of practical operation.
The present invention is directed to the development trend of the densification of future microelectronics product and multifunction, a new bonding interconnecting method is proposed, its key point is the application of copper micropin cone, because copper micropin wimble structure has the feature such as special pointed structures and array form, and there is many new functional characteristics, and can be applied in Electronic Packaging industry.Under the present invention utilizes it and higher temperature, significantly softening solid-state lead-free solder salient point obtains good mechanical snap, and huge surface area can promote the counterdiffusion of combination interface thus improve adhesion etc.The method be also advantageous in that copper micropin cone size is very large, most high energy reaches 5 microns, so just greatly can reduce the requirement of para-linkage bump surface evenness and the required precision of bonding apparatus.In addition interfacial reaction ratio is very fast in a heated condition for copper micropin cone and the solder bump based on Sn, can produce enough interfacial reactions at short notice thus form effective bonding, being easy to realize industrial applications.The verified a lot of preparation method of research comprising applicant can obtain the copper micropin cone of application claims, such as chemical deposition, by adding special additive in plating solution, thus control crystal by the orientation preferentially vertical with substrate growth, and the size of pin taper crystalline substance is controlled by adjustment chemical deposition parameters, form the controlled pin cone array structure of 1 micron to 5 microns at material surface.
Technical process of the present invention do not need by more than heating temperatures to solder melt point to make solder fusing, can avoid producing fire damage to device, and solid-state bonding can improve interconnection density and product reliability, interfacial reaction is controlled, thus simplifies technological process without the need to organic substances such as scaling powders.
Be only several specific embodiments of the application above, but the application is not limited thereto, the changes that any person skilled in the art can think of, all should drops in the protection range of the application.
Claims (12)
1. a method for semiconductor device low temperature solid-state bonding, is characterized in that, is made up of following steps:
1) at least two elements to be bonded of the electrical interconnection pad with coupling are mutually selected;
2) on multiple pads of an element to be bonded, form copper micropin cone group;
3) on multiple pads of another element to be bonded, form at least surface be provided with the salient point of soft second metal level;
4) described salient point is bored group with described copper micropin to mate, and make described salient point bore group with described copper micropin to contact, the contact portion that described salient point and described copper micropin bore group is heated to the first temperature, applying bonding pressure makes described salient point and described copper micropin bore group's electrical interconnection bonding, wherein, described first temperature is lower than the fusing point of described second metal level.
2. the method for a kind of semiconductor device low temperature solid-state bonding as claimed in claim 1, is characterized in that, described copper micropin cone group is formed in bond pad surface by chemical deposition, electrodeposition process or vapour deposition process.
3. the method for a kind of semiconductor device low temperature solid-state bonding as claimed in claim 1, is characterized in that, the height of described copper micropin cone group is 1 μm-5 μm.
4. the method for a kind of semiconductor device low temperature solid-state bonding as claimed in claim 1, is characterized in that, step 2) also comprise: on described copper micropin cone group surface, antioxidation coating is set.
5. the method for a kind of semiconductor device low temperature solid-state bonding as claimed in claim 4, is characterized in that, described antioxidation coating is arranged on described copper micropin cone group surface by electrodeposition process or vapour deposition process.
6. the method for a kind of semiconductor device low temperature solid-state bonding as claimed in claim 4, it is characterized in that, described antioxidation coating comprises metal simple-substance or the alloy of Au, Pt, Ag or Pd.
7. the method for a kind of semiconductor device low temperature solid-state bonding as claimed in claim 4, is characterized in that, the thickness of described antioxidation coating is 5nm-50nm.
8. the method for a kind of semiconductor device low temperature solid-state bonding as claimed in claim 1, it is characterized in that, described bonding pressure is 1-30MPa.
9. the method for a kind of semiconductor device low temperature solid-state bonding as claimed in claim 1, is characterized in that, the time applying bonding pressure in step 4) is 10s-20min.
10. the method for a kind of semiconductor device low temperature solid-state bonding as claimed in claim 1, it is characterized in that, the material of described second metal level comprises indium, tin, indium alloy or ashbury metal.
The method of 11. a kind of semiconductor device low temperature solid-state bondings as claimed in claim 1, it is characterized in that, described second metal level is arranged on described bump surface by electrodeposition process, chemical deposition, vapour deposition process or coating process.
The method of 12. a kind of semiconductor device low temperature solid-state bondings as claimed in claim 3, it is characterized in that, the micropin cone height on same pad is basically identical.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210086084.6A CN102610537B (en) | 2012-03-28 | 2012-03-28 | Method for low-temperature solid bonding of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210086084.6A CN102610537B (en) | 2012-03-28 | 2012-03-28 | Method for low-temperature solid bonding of semiconductor device |
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| CN102610537A CN102610537A (en) | 2012-07-25 |
| CN102610537B true CN102610537B (en) | 2015-03-11 |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104112681A (en) * | 2014-07-03 | 2014-10-22 | 上海交通大学 | Solid-state ultrasonic bonding method based on copper microneedle cone |
| CN104112707B (en) * | 2014-07-03 | 2018-07-03 | 上海交通大学 | A kind of solid ultrasonic bonding method based on nickel and copper micropin cone foreign structure |
| CN104112684A (en) * | 2014-07-03 | 2014-10-22 | 上海交通大学 | Solid ultrasonic bonding method based on nickel micro cones |
| CN104112683A (en) * | 2014-07-03 | 2014-10-22 | 上海交通大学 | Solid ultrasonic bonding method based on homogeneous structures of copper micro cones |
| CN105679683B (en) * | 2016-01-15 | 2019-01-15 | 华中科技大学 | A kind of copper and tin copper bonding technology and structure based on copper nanometer rods |
| CN109346401B (en) * | 2018-10-18 | 2021-03-26 | 苏州美图半导体技术有限公司 | Method for improving gold-gold hot-pressing bonding strength in silicon surface nano forest |
| EP4005357A1 (en) * | 2019-07-22 | 2022-06-01 | Technische Hochschule Aschaffenburg | Electrical connection pad with enhanced solderability and corresponding method for laser treating an electrical connection pad |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6204089B1 (en) * | 1999-05-14 | 2001-03-20 | Industrial Technology Research Institute | Method for forming flip chip package utilizing cone shaped bumps |
| JP2002313995A (en) * | 2001-04-19 | 2002-10-25 | Mitsubishi Electric Corp | Land grid array semiconductor device and its mounting method |
| US7674651B2 (en) * | 2006-12-26 | 2010-03-09 | International Business Machines Corporation | Mounting method for semiconductor parts on circuit substrate |
| CN102169845B (en) * | 2011-02-22 | 2013-08-14 | 中国科学院微电子研究所 | Multi-layer mixed synchronization bonding structure and method for three-dimensional packaging |
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