CN102608579A - SAR (synthetic aperture radar) data receiving and processing system and method - Google Patents

Abstract

The invention discloses a SAR data receiving and processing system and method, which are implemented on an FPGA chip; it includes a format decompression processing module, a compressed code stream buffer unit, an 8-way decompression processing module, a ping-pong buffer module and an interface buffer unit; wherein each The road decompression processing module includes a serial/parallel unit, a decompression unit, and a serial-parallel unit; write the frame compressed data into the compressed code stream buffer unit in the main course of a SAR data frame, and write the compressed code stream buffer unit in the current SAR data frame Read the compressed data from the compressed code stream buffer unit in the inverse process, and then process the frame data through the 8-way decompression processing module, and splicing it into a frame recovery data through the ping-pong buffer module; in the inverse process of the next SAR data frame Processing of the next SAR data frame. The invention can rationally utilize hardware resources and has strong real-time performance.

Description

A system and method for receiving and processing SAR data

technical field

The invention relates to a system and method for receiving and processing SAR data.

Background technique

Synthetic aperture radar is a scientific instrument with all-weather and all-weather imaging capabilities. How to fully and effectively apply this instrument in spaceborne remote sensing applications has attracted more and more attention from all over the world.

The real-time and high-efficiency SAR (Synthetic Aperture Radar) raw data sending and receiving processor is a key extension in the modern spaceborne SAR system. These include technologies such as SAR data compression, packetization and formatting, unpacking and decompression, and decompression. Because the SAR system has a large mapping bandwidth and system dynamic range, its echo signal sampling, storage and transmission have a considerable amount of data and data rate. The data transmission capability provided by the digital transmission system often cannot meet the requirements for real-time data transmission, resulting in a high data transmission bottleneck from the satellite to the ground, which has become a key problem that must be solved in the development of spaceborne synthetic aperture radar.

The SAR data receiving processor is one of the key extensions in the data transmission system. In the digital transmission system, because the receiving process is the recovery process of data, the real-time performance is not strong, and it specifically includes two parts: data deformatting and decompression. In order to improve the real-time performance of the system, the multi-channel data decompression process is generally carried out in parallel after the deformatting. Since the original SAR data can be approximated as a zero-mean Gaussian distribution with unknown variance, the entire SAR data set can be divided into several small blocks along the azimuth and distance directions, and each small block of data can be considered as a zero-mean Gaussian distribution with steady-state characteristics , and its distribution can be uniquely determined by its root mean square σ. The commonly used SAR data compression algorithm is to divide a frame of SAR data into small blocks of 32x 32, and then compress them in these small blocks. Different SAR flight calibration modes, the frame data width varies, up to 96000*32 , for I, Q two-way, that is to decompress 6000 32*32 compressed small blocks of data. If a full-parallel solution is adopted, it is simple to control the timing, but if it is implemented on a single FPGA chip, the resources are far from enough. If a serial solution is adopted, the real-time performance will be poor.

Contents of the invention

The technical problem to be solved by the present invention is to provide a real-time and high-speed SAR data receiving and processing system and method that can rationally utilize hardware resources in view of the deficiencies of the prior art.

The present invention includes following technical solutions:

A SAR data receiving and processing system, the SAR data receiving and processing system is implemented on an FPGA chip; including a format decompression processing module, a compressed code stream buffer unit, an 8-way decompression processing module, a ping-pong buffer module and an interface buffer unit; wherein Each decompression processing module includes a serial/parallel unit, a decompression unit, and a serial-parallel unit; the deformat processing module is used to extract the format frame header and the compressed code stream with the compressed frame header from the received format frame, and compress The code stream is written into the compressed code stream buffer unit, and the compressed code stream is divided into 8 paths of mean value data and block compressed data by controlling the read operation of the compressed code stream buffer unit; each path of decompression processing module receives corresponding mean value data and block compressed data; The serial-parallel/parallel-serial unit performs serial-parallel and parallel-serial conversion processing on the block compressed data; the decompression unit decompresses the converted compressed data and the delayed average data according to the decompression processing algorithm to obtain small block recovery data ; The serial-to-parallel unit performs serial-to-parallel conversion on the recovered data, and writes it into the ping-pong buffer module; operation, and continuously send the restored data to the interface cache unit.

Write the frame compressed data into the compressed code stream buffer unit in the forward process of a SAR data frame, read the compressed data from the compressed code stream buffer unit in the reverse process of the current SAR data frame, and then decompress it through 8 channels The processing module processes the data of the frame, and splicing it into one frame to recover data through the ping-pong buffer module; the processing of the next SAR data frame is carried out in the reverse process of the next SAR data frame.

The decompression processing algorithm adopts a 3-bit block adaptive quantization algorithm.

Compared with the prior art, the present invention has the following advantages:

Due to the limitation of hardware resources and scale, for different school flight modes, there are 192 to 6000 32*32 small pieces of SAR data to be decompressed, which is impossible to realize in one XC5VSX95T chip. If these small blocks are decompressed serially, the real-time performance cannot be satisfied at all. The present invention chooses 8-way decompression parallel processing, which is a compromise between the above-mentioned full parallel and full serial processing, can rationally utilize hardware resources, and has strong real-time performance.

Description of drawings

Fig. 1 is a block diagram of the SAR data receiving and processing system of the present invention;

Fig. 2 is the SAR data output timing diagram of the present invention;

Fig. 3 is a splicing block diagram of SAR recovery data;

Figure 4 is a schematic diagram of SRAM read and write data;

FIG. 5 is a sequence diagram of SAR data receiving processing in the present invention.

Detailed ways

The present invention will be further introduced below in conjunction with the accompanying drawings.

The key module in the processing of SAR data transmission and reception is the algorithm design of SAR data compression and decompression. The analysis shows that both the real and imaginary parts of the SAR echo signal can be approximated as a zero-mean Gaussian distribution with unknown variance, and the echo signal power is a slow-varying function of distance and pulse, so making full use of this SAR echo signal Statistical properties, the entire echo data set can be divided into several small blocks along the azimuth and distance, so that each small block of data can be considered as a zero-mean Gaussian distribution with steady-state characteristics, and its distribution can be uniquely determined by its root mean square σ . The selection of the block size should follow the following principles: the block must be small enough to ensure that the σ of the SAR data in each small block is constant, and at the same time, the block must be large enough to ensure that the σ of each block can be effectively estimated. The specific block size should be determined according to the relevant system parameters. The present invention selects a 32*32 block as a compression processing block, and uses a 3-bit block self-adaptive quantization algorithm to perform data compression and decompression.

The principle implementation steps of the compression algorithm are as follows: (1) divide the original data into several small blocks, and estimate the sample standard deviation in this small block; (2) use this standard deviation to normalize the data in the block, so that it conforms to the mean zero, the standard Gaussian distribution with a variance of 1; (3) Based on the (0, 1) Gaussian distribution, pre-calculate the decision level and quantization level; (4) compare the normalized data with the decision level to get Quantized codewords. For details, please refer to the following documents: Cui Wei et al., FPGA Realization of 3bit Block Adaptive Quantization Algorithm, Journal of Beijing Institute of Technology, Vol.25, No.2, Feb.2005. The above compression algorithm compresses 8-bit data into 3 bits in each 32*32 small block. For a 32*32 small block, the data volume after compression is (32*32)*3/8=384 bytes.

The decompression algorithm implementation steps in the corresponding receiving process are as follows: (1) receive the compressed code stream data, separate the code stream data and mean data of each data block; (2) search for the corresponding output quantization level according to the code stream data; (3 ) Calculating the average value data and the output quantization level to obtain the restored data; (4) Splicing the restored small blocks of data to form a frame of restored SAR data. In addition, the above decompression algorithm can also use variance data instead of mean data for processing.

The SAR data receiving and processing system of the present invention is shown in Figure 1, and it is realized on one FPGA chip XC5VSX95T, and function includes data deformatting, decompression, data splicing and interface communication with DSP etc. Since the received AOS (Advanced On Orbit System) format frame with a frame length of 1024 bytes must first be deformatted to extract valid data with a compressed frame header, and then perform decompression processing according to the implementation steps of the decompression algorithm , and finally splice the restored data and send it to the back-end SAR imaging DSP module.

For one frame of original data, it is divided into 32x32 small blocks for compression during the satellite transmission process, and the reverse journey time of one frame of data transmission is relatively long. Taking advantage of this feature, after timing analysis and calculation, considering the resource utilization rate of the FPGA chip, select 8 32x 32 small block parallel decompression schemes for processing, and finally splicing the restored data of the small blocks to form a frame of data Cache into the SRAM, through the ping-pong operation of the SRAM, continuously send the recovered data to the interface cache with the SAR imaging DSP module for subsequent SAR imaging processing. The SAR data receiving and processing system and the SAR imaging DSP module communicate with each other by allocating buffer units in the FPGA, controlling the read and write handshake signals of the buffer units, and using EMIFA. The specific hardware implementation block diagram is shown in Figure 1.

Firstly, it receives the input clock sent by the satellite and the 8bit parallel compressed packaged data, and the deformat processing module performs frame synchronization processing on the data twice. The first time is to extract the frame header of AOS format, and the second time is to extract the compressed frame header. Since compression coding is to pack a frame of compressed code stream data into AOS frame format output with a length of 1024 bytes, for a frame of SAR compressed code stream data, it will be packed into hundreds or even thousands of AOS format frames, and these frames have fixed Frame header data 1ACFFC1D and format, when the frame header data is detected, it is considered to be effective compressed code stream data and received, and finally these data are continuously passed to the next function module. After the format frame of 1024 bytes is parsed into valid compressed code stream data by the deformat processing module, and whether there is compressed frame header data in these data, if there is, it is considered as the beginning of a frame of valid code stream data, And continuously receive this frame of data and store it in the internal FIFO, that is, the compressed code stream buffer unit. Considering the input requirements of the 8-way parallel decompression processing module at the back end, when reading data from the FIFO, only 8 times the amount of data is read each time, and the 8-way effective block compressed data and average data are separated by a counter, and output to the solution In the compression processing module. The specific method is as follows: FIFO has a read-write enable port, and the write enable is always valid from the time of receiving a frame of code stream data to the arrival of the next frame of data. After writing a frame of data, the data reading begins. For the present invention, the data is read out from the compressed code stream buffer unit with 8 times the input clock at a time, and the counter counts. Since the code stream data is stored according to the average value of one byte first, and then a 32*32 small block of compressed data is stored continuously, when the counter is equal to 1, the average value data of the first small block is read out, and when it is equal to 2 to 385, Just read the compressed data of this small block, and send the average value data and code stream data of this block to the first decompression processing module; when the counter is equal to 386, read the average value data of the second small block; it is equal to 387 to At 770, read the compressed data of the second small block and send it to the second decompression unit, and so on, separate the compressed data and average data of the 8-channel block, and output them to the decompression processing module.

The 8-way block compressed data and average value data are respectively sent to 8 independent decompression processing modules, and these 8 decompression processing modules have the same function. The decompression processing module includes a serial/parallel unit, a decompression unit and a serial/parallel unit; the serial/parallel unit performs serial/parallel processing on the compressed data, including 8bit parallel into 48bit, 48bit into 3bit; decompression The unit processes the 3-bit compressed data and the delayed average data according to the implementation steps (2) and (3) in the above-mentioned decompression processing algorithm. After the processing is completed, the restored data is 8bit. In order to save processing time, the serial-parallel unit performs serial-parallel conversion on the 8-way 8-bit restored data, and finally, merges them into 2-way 32bit data (32bit data is the data required by the back-end DSP imaging unit format) output to the back-end ping-pong cache module.

FPGA completes the data processing in one clock beat. Because the compression unit on the star splices every 3-bit compressed data into 8 bits for data transmission, so the decompression module of the SAR data receiving and processing system of the present invention must restore the 8-bit data to 3-bit data and send it to the decompression unit. The clock of a digital circuit must be an integer. To restore 8-bit data to 3-bit data, you must take the common divisor of 3 and 8, such as 24, 48, etc. For the serial-to-parallel conversion function, it is equivalent to divide the input clock by 6, that is, shift the 8-bit data into 48 bits, and output it under the frequency-divided clock, the hardware is feasible; To output 3 bits from 48 bits under the beat, 16 shift registers are required to string 3-bit data output.

The ping-pong buffer module includes two SRAMs: SRAM1 and SRAM2. The function of the ping-pong buffer module is to stitch the recovered data into a frame of data and store them in the SRAM in a ping-pong manner. After decompression, the 32*32 data of each block synchronous process are arranged from left to right and from top to bottom in the actual SAR two-dimensional data position as shown in Figure 3 below. Among them, according to different flight calibration modes, Ns The range is 3072-96000. Therefore, it is necessary to stitch each of the eight parallel decompressed blocks into one frame of data from left to right as shown in FIG. 3 . Specifically, it is to control the read-write enable and read-write address of the SRAM, write the recovery data into the SRAM in sequence, and generate the read-out address in C language according to the position of the pixel in the image shown in Figure 3, and then these Small pieces of restored data are spliced into a frame of data, and output to the interface cache unit at high speed. FIG. 4 is a schematic diagram of read and write operations of restored data in the SRAM. Write data is written in the order defined by the frame format of the compressed code stream, that is, I1, Q1, I2, Q2, ... INs/32, QNs/32, and I1 (0-1023) in the illustration represents I1 The storage address of block data in SRAM is from 0 to 1023, Q1 (1024-2047) means that the storage address of Q1 block data in SRAM is from 1024 to 2047, and so on. When reading, all the data of the I channel is read first, and then the data of the Q channel is read out, that is, the read data is in accordance with I1, I2,..., INs/32, Q1, Q2,..., QNs/ 32.

According to the hardware implementation method in FIG. 1 , the timing diagram output by the SAR data receiving and processing system of the present invention is shown in FIG. 2 . Among them, the high level of the frame synchronization signal corresponds to valid data, which is the forward process of the frame; the low level corresponds to invalid data, which is the backward process of the frame. According to the different application modes of SAR data, the forward stroke of the frame varies from 3072 to 96000 clocks, and the backward stroke of the frame is variable. Each frame contains one block synchronization signal of I or Q channel within the normal range, and the number of block synchronization signals changes from 3072/32=96 to 96000/32=3000, among which the high level of the block synchronization signal corresponds to 32*32 valid data, low level corresponds to invalid data. The auxiliary data enable is aligned with the rising edge of the frame synchronization signal, which can be delayed, and the enable high level corresponds to the effective auxiliary data, a total of 90 clocks.

The existing receiving and processing system writes the frame 1 compressed data in the frame synchronization signal process, generally after the rising edge of the next frame synchronization signal, that is, completes the frame 1 reception within the period of writing the frame 2 compressed data Processing, the delay is very large, and the real-time performance is poor. Considering the timing sequence of SAR data transmission, since the retrace time of one frame of data is relatively long, this feature can be fully utilized. The frame is processed within the frame, and the receiving process of the next frame is performed within the next frame retracement. The specific implementation process is to write the compressed code stream data of frame 1 into the compressed code stream buffer unit during the forward travel time of frame 1, and read the compressed code stream data of frame 1 from the compressed code stream buffer unit during the reverse travel time of frame 1 The data is processed together, and the processing result is written into SRAM1; during the forward time of frame 2, the compressed code stream data of frame 2 is written into the compressed code stream buffer unit, and the compressed data of frame 2 is read out during the reverse travel time of frame 2 And process it, write the processing result into SRAM2, and read out frame 1 recovery data from SRAM1 at the same time; write frame 3 compressed stream data into the compressed data cache during frame 3 forward time, and write frame 3 compressed code stream data into compressed data cache during frame 3 reverse Inside, read the compressed data of frame 3 and process it, write the result into SRAM1, and read the restored data of frame 2 from SRAM2 at the same time, SRAM1 and SRAM2 continuously send the restored data of each frame to the interface cache unit according to this ping-pong interaction mode middle. During the read and write operations of the SRAM, an 8-times high-speed clock is used for writing the clock, and the input clock is used for reading the clock, and finally the restored data is sent to the interface cache unit in real time and continuously.

The communication interface between the SAR data receiving and processing system of the present invention and the DSP imaging module is realized by using FIFO buffer (interface buffer unit) in FPGA. FPGA and DSP jointly control the read and write enable of FIFO. If the data on the FPGA port is ready, a read instruction is issued, and the DSP takes the data; if the DSP has processed the data, a write instruction is issued, and the FPGA sends the data. The EMIFA method for interactive communication.

Parts not described in detail in the present invention belong to the common knowledge of those skilled in the art.

Claims (3)

1. A SAR data receiving and processing system is characterized in that: said SAR data receiving and processing system is realized on a slice of FPGA chip; Comprises solution format processing module, compressed stream buffer unit, 8 road decompression processing modules, ping-pong buffer module and an interface cache unit; wherein each decompression processing module includes a serial/parallel unit, a decompression unit and a serial unit; The deformat processing module is used to extract the format frame header and the compressed code stream with the compressed frame header from the received format frame, and write the compressed code stream into the compressed code stream buffer unit, and compress the code stream by controlling the read operation of the compressed code stream buffer unit. The code stream is divided into 8-way average data and block compressed data; Each decompression processing module receives the corresponding average value data and block compressed data; the serial/parallel/parallel unit performs serial and parallel conversion processing on the block compressed data; the decompression unit converts the converted compressed data and the delayed processed The average value data is decompressed according to the decompression processing algorithm to obtain the restored data of the small block; the serial-parallel unit performs serial-parallel conversion on the restored data, and writes it into the ping-pong cache module; The ping-pong cache module splices the recovery data of small blocks to form a frame of data and caches it in the SRAM. Through the ping-pong operation of the SRAM, the recovery data is continuously sent to the interface cache unit. 2. The method for receiving and processing SAR data by adopting the SAR data receiving and processing system as claimed in claim 1 is characterized in that: the frame compressed data is written into the compressed code stream buffer unit in the normal course of a SAR data frame, Read the compressed data from the compressed code stream buffer unit in the inverse process of the current SAR data frame, and then process the frame data through the 8-way decompression processing module, and splicing it into a frame recovery data through the ping-pong buffer module; in the next SAR data frame The processing of the next SAR data frame is carried out in the inverse process. 3. The method according to claim 2, characterized in that: said decompression processing algorithm adopts a 3-bit block adaptive quantization algorithm.

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