CN102608579A - SAR (synthetic aperture radar) data receiving and processing system and method - Google Patents
SAR (synthetic aperture radar) data receiving and processing system and method Download PDFInfo
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Abstract
The invention discloses an SAR (synthetic aperture radar) data receiving and processing system and method. The system and the method are realized on an FPGA (field programmable gate array) chip. The system comprises a format analysis processing module, a compressed code stream cache unit, 8 decompression processing modules, a ping-pong cache module and an interface cache unit, wherein each decompression processing module comprises a series-parallel/parallel-series unit, a decompression unit and a series-parallel unit. The method comprises the following steps of: in the trace of an SAR data frame, writing the compressed data of the frame into the compressed code stream cache unit; reading the compressed data from the compressed code stream cache unit in the return trace of the current SAR data frame; then processing the data of the frame by the 8 decompression processing modules, and splicing the data into a frame of recovery data through the ping-pong cache module; and processing the next SAR data frame in the return trace of the next SAR data frame. The system and method disclosed by the invention can reasonably utilize hardware resources, and have strong real-time performance.
Description
Technical field
The present invention relates to a kind of SAR Data Receiving disposal system and method.
Background technology
Synthetic-aperture radar is a kind of scientific instrument with round-the-clock, round-the-clock imaging capability, and how abundant this instrument of effective application in space remote sensing is used more and more obtains the attention of countries in the world.
It is the extension set of a key in the modern Spaceborne SAR System that the SAR of real-time high-efficiency (synthetic-aperture radar) raw data is sent receiving processor.Comprising SAR data compression, subpackage draw squares formula, unpack technology such as form and decompression.Because the SAR system has bigger mapping bandwidth and system dynamics scope, its echoed signal sampling, storage and transmission have sizable data volume and data transfer rate.The data transmission capabilities that number biography system is provided often can not satisfy the real-time Transmission requirement to data, causes satellite to become the key issue that development satellite-borne synthetic aperture radar institute must solution to the high data transmission bottleneck on ground.
The SAR data receiving processor is one of extension set crucial in the number biography system.In number biography system, because receive the recovery processing that processing is data, real-time is not strong, comprises that specifically data are separated form and two parts that decompress.In order to improve the real-time of system, generally be parallel decompression of carrying out multichannel data after separating form.Because the SAR raw data can be approximately the zero-mean Gaussian distribution with unknown variance; So can be divided into plurality of small blocks to whole SAR data set along the azran descriscent; Each little blocks of data can think to have the zero-mean Gaussian distribution of steady-state characteristic, and its distribution can be confirmed by its root mean square σ is unique.SAR data compression algorithm commonly used is the fritter that is divided into frame SAR data 32x 32; In these fritters, compress then, different SAR schools fly pattern, and its frame data fabric width changes; Be up to 96000*32; For I, the Q two-way, just will compression to 6000 32*32 after little blocks of data decompress.If adopt full parallel scheme, control timing is simple, but realizes that on the monolithic fpga chip resource is far from being enough.If the employing serial scheme, real-time can be very poor.
Summary of the invention
Technical matters to be solved by this invention is: the deficiency to prior art provides a kind of SAR Data Receiving disposal system and the method that can rationally utilize hardware resource, real time high-speed.
The present invention includes following technical scheme:
A kind of SAR Data Receiving disposal system, said SAR Data Receiving disposal system realizes on a slice fpga chip; Comprise and separate format analysis processing module, compressed bit stream buffer unit, 8 tunnel decompression modules, ping-pong buffer module and interface buffer unit; Wherein every road decompression module comprise string also/and string location, decompression unit and string and unit; Separate the compressed bit stream that the format analysis processing module is used for the format frame that receives is extracted form frame head and band compression frame head; And compressed bit stream write the compressed bit stream buffer unit, the read operation through control compressed bit stream buffer unit is divided into 8 tunnel mean data and piece packed data with compressed bit stream; Every road decompression module receives corresponding mean data and piece packed data; String also/and string location is gone here and there to the piece packed data and with and go here and there conversion process; Decompression unit after to conversion packed data and decompress according to the decompression algorithm through the mean data of delay process and to obtain the restore data of fritter; String and unit carry out serial to parallel conversion to restore data, and are written in the ping-pong buffer module; The ping-pong buffer module is spliced the restore data of fritter, is cached among the SRAM after forming frame data, and through the ping-pong operation to SRAM, continuous delivers to restore data in the interface buffer unit.
In the trace of a SAR Frame, this frame packed data is write said compressed bit stream buffer unit; In the flyback of current SAR Frame, read packed data from the compressed bit stream buffer unit; Through 8 tunnel decompression modules these frame data are handled then, be connected into a frame restore data through the ping-pong buffer module spliced; In the flyback of next SAR Frame, carry out the processing of next SAR Frame.
Said decompression algorithm use 3bit block adaptive quantization algorithm.
The present invention compared with prior art has following advantage:
Because the restriction of hardware resource and scale flies pattern for different schools, has the fritter SAR data of 192 to 6000 32*32 to decompress, this can not realize in a slice XC5VSX95T chip.If serial decompresses to these fritters, real-time can't satisfy at all.The present invention selects 8 tunnel decompression parallel processings, is the above-mentioned complete parallel compromise of handling with full serial, can rationally utilize hardware resource, and is real-time.
Description of drawings
Fig. 1 is a SAR Data Receiving disposal system block diagram of the present invention;
Fig. 2 is a SAR data output timing diagram of the present invention;
Fig. 3 is SAR restore data splicing block diagram;
Fig. 4 is the SRAM synoptic diagram that reads and writes data;
Fig. 5 is that SAR Data Receiving of the present invention is handled sequential chart.
Embodiment
Just combine accompanying drawing that the present invention is done further introduction below.
It is the compression and decompression algorithm design of SAR data that the SAR data are sent the key modules that receives in handling.Analysis shows; The real part of SAR echoed signal and imaginary part all can be approximately the zero-mean Gaussian distribution with unknown variance; And echoed signal power is the slowly varying function of distance and pulse, so make full use of this statistical property of SAR echoed signal, can be divided into plurality of small blocks to whole echo data collection along the azran descriscent; Thereby each little blocks of data can think to have the zero-mean Gaussian distribution of steady-state characteristic, and its distribution can be confirmed by its root mean square σ is unique.The selection of block size should be followed following principle: piece must be enough little constant with the σ that guarantees SAR data in each fritter, and piece again must be enough big to guarantee effectively to estimate the σ of each piece simultaneously.Concrete block size will be confirmed according to relevant systematic parameter.The present invention selects the piece of 32*32 as the processed compressed piece, and adopts 3bit block adaptive quantization algorithm to carry out the compression and decompression of data.
The principle performing step of compression algorithm is following: (1) is divided into plurality of small blocks with raw data, estimates the sample standard deviation in this fritter; (2) use this standard deviation with data normalization in the piece, making it to meet average is zero, and variance is 1 standard Gaussian distribution; (3) be the basis with (0,1) Gaussian distribution, calculated decision level and quantization level in advance; (4) code word after normalized data and decision level are relatively obtained quantizing.Specifically can be with reference to following document: rocky mound etc., the FPGA of 3bit block adaptive quantization algorithm realizes, Beijing Institute of Technology's journal, Vol.25, No.2, Feb.2005.Above-mentioned compression algorithm becomes 3bit with the data compression of 8bit in each 32*32 fritter, for a 32*32 fritter, having compressed the back data volume is (32*32) * 3/8=384 byte.
The decompression algorithm performing step was following during corresponding reception was handled: (1) receives the compressed bit stream data, separates each block code flow data and mean data; (2) search corresponding output quantization level according to bit stream data; (3) mean data and output are quantized level meter and calculate the data after being restored; (4) each the little blocks of data after will recovering splices, and forms a frame and recovers the SAR data.In addition, above-mentioned decompression algorithm also can replace mean data to handle with the variance data.
SAR Data Receiving disposal system of the present invention is as shown in Figure 1, and it realizes on a slice fpga chip XC5VSX95T, function comprise data separate form, decompression, data splicing and with interface communication of DSP etc.Because what receive is that frame length is AOS (senior to the rail system) format frame of 1024 bytes; At first must separate format analysis processing; Extract the valid data of band compression frame head; Carry out decompression according to the decompression algorithm performing step again, at last restore data is spliced, and deliver in the SAR imaging DSP module of rear end.
For a frame raw data, be divided into the 32x32 fritter in the satellite transmission processing procedure and compress, and the retrace interval of frame data transmission is long.Utilize this characteristics,, consider the resource utilization of fpga chip through time series analysis and calculating; Select the scheme of 8 32x 32 fritter parallel decompression to handle; Again the restore data of fritter is spliced at last, be cached among the SRAM after forming frame data, through ping-pong operation to SRAM; Continuous restore data is delivered to SAR imaging DSP module interface buffer memory in, supply follow-up SAR imaging processing.SAR Data Receiving disposal system and SAR imaging DSP module are through in FPGA, distributing buffer unit, control the read-write handshake of buffer unit, using the EMIFA mode to communicate.Concrete hardware realizes that block diagram is as shown in Figure 1.
At first receive the input clock and the parallelly compressed back of the 8bit packing data of satellite transmission, separate the format analysis processing module data are carried out frame synchronization process 2 times.For the first time being to extract AOS form frame head to handle, is for the second time to extract the compression frame head to handle.Because compressed encoding is the AOS frame format output that becomes a frame compressed bit stream packing data 1024 byte lengths; For frame SAR compressed bit stream data; Can be packaged into hundreds of even thousands of AOS format frame, these frames have fixing frame head data 1ACFFC1D and form, after detecting frame head data; Just think it is thereafter effective compressed bit stream data and reception, finally continuous passes to next functional module with these data.Separate after the format analysis processing module parses effective compressed bit stream data to the format frame of each 1024 byte; And detect whether the compression frame head data is arranged in these data; If have, just think the beginning of a frame effective code flow data, and these frame data under the continuous reception; Be stored among the inner FI FO, just the compressed bit stream buffer unit.Consider 8 tunnel parallel decompression processing modules input requirement of rear end, from FIFO, during sense data, only read 8 times data volume at every turn, and isolate 8 tunnel effective piece packed data and mean data, output in the decompression module with counter.Concrete grammar is following: FIFO has the read-write enable port, begins from receiving a frame bit stream data, in the arrival during this period of time of next frame data, writes and enables continuously effective.Write after the frame data, read data begins, and for the present invention, is exactly to use 8 times input clock from compressed bit stream buffer unit sense data, rolling counters forward at every turn.Because it is the average according to depositing a byte earlier that bit stream data is deposited; Deposit 32*32 fritter packed data more continuously;, just reads by counter the mean data of first fritter when equaling 1; Equal at 2 to 385 o'clock, just read the packed data of this fritter, and the mean data and the bit stream data of this piece are delivered in the first via decompression module; , reads by counter the mean data of second fritter when equaling 386; Equal at 387 to 770 o'clock, read the packed data of second fritter, and deliver in the second road decompression unit, and the like, isolate 8 road piece packed data and mean data, output in the decompression module.
8 road piece packed datas and mean data are delivered to 8 respectively independently in the decompression module, and these 8 decompression functions of modules are identical.The decompression module comprise string also/and string location, decompression unit and string and unit; String also/and string location packed data is gone here and there also/and string manipulation, comprise 8bit and become 48bit that 48bit conspires to create 3bit; Mean data after decompression unit is handled to this 3bit packed data with through delay is handled according to performing step (2) and (3) in the above-mentioned decompression algorithm.After finishing dealing with; Restore data is 8bit, and in order to practice thrift the processing time, string and unit carry out serial to parallel conversion to the restore data of this 8 road 8bit; At last, and become 2 road 32bit data (the 32bit data are data layouts of rear end DSP image-generating unit requirement) to output to the ping-pong buffer module of rear end.
FPGA is the processing of under timeticks one by one, accomplishing data.Because compression unit is to be spliced into 8bit to the packed data of every 3bit to carry out data transmission on the star, so must become this 8bit reduction of data the 3bit data to deliver in the decompression unit at the decompression module of SAR Data Receiving disposal system of the present invention.The clock of digital circuit must be an integer, become the 3bit data to the 8bit reduction of data, must get 3 and 8 common divisor, such as 24,48 etc.For string and translation function, be equivalent to and will carry out 6 frequency divisions input clock, just to the 8bit data shift and become 48bit, under the frequency division clock, to export, hardware is feasible; For and go here and there translation function, just need 16 times shift LD from 48bit output 3bit under the input clock beat, conspire to create the output of 3 Bit datas.
The ping-pong buffer module comprises two SRAM:SRAM1 and SRAM2, and the function of ping-pong buffer module is to be spliced into frame data to restore data, and table tennis is stored among the SRAM.Owing to decompress 32*32 data of the synchronous trace of each piece of back be illustrated in fig. 3 shown below in actual SAR 2-D data position according to from left to right, arrangement from top to bottom, wherein, fly pattern according to different schools, the scope of Ns is 3072-96000.Therefore several pieces after need handling per 8 parallel decompression from left to right are spliced into frame data according to shown in Figure 3.The read-write that specifically is control SRAM enables and read/write address; With writing among the SRAM of restore data order; According to the position of pixel shown in Figure 3 in image; Address when reading with the C language generation just can be spliced into the restore data of these fritters one frame data, outputing to and the interface buffer unit at a high speed.Fig. 4 is the read-write operation synoptic diagram of restore data in SRAM.Write data is to write according to the order that the compressed bit stream frame format defines; Be I1, Q1, I2, Q2 ... INs/32, QNs/32; It is from 0 to 1023 that I1 in the diagram (0-1023) represents the storage address of I1 blocks of data in SRAM; It is from 1024 to 2047 that Q1 (1024-2047) represents the storage address of Q1 blocks of data in SRAM, and the like.When reading, be the data of all reading earlier the I road, read the data on Q road again, promptly sense data according to I1, I2 ..., INs/32, Q1, Q2 ..., QNs/32.
According to the hardware implementation method of Fig. 1, the sequential chart of SAR Data Receiving disposal system output of the present invention is as shown in Figure 2.Wherein, the corresponding valid data of frame synchronizing signal high level are frame trace; The corresponding invalid data of low level is picture flyback.Frame trace is according to SAR data different application pattern, and from 3072 to 96000 clocks change, and picture flyback is variable.Comprise the block sync signal on one road I or Q road in each frame trace scope, the block sync signal number changes from 3072/32=96 to 96000/32=3000, wherein in the block sync signal, and corresponding 32*32 the valid data of high level, low level correspondence invalid data.Auxiliary data enables to align with the frame synchronizing signal rising edge, can delay, and enables high level corresponding effectively auxiliary data, totally 90 clocks.
Existing receiving processing system is after in frame synchronizing signal trace, writing incoming frame 1 packed data, generally is after next frame synchronizing signal rising edge arrives, and promptly accomplishes the reception processing of frame 1 during this period of time writing frame 2 packed datas, and time delay is very big, and real-time is very poor.Consider SAR data transmission sequential; Because the retrace interval of frame data is long; Can make full use of these characteristics, as shown in Figure 5, the present invention is after in frame trace, having write a frame packed data; In picture flyback, just this frame is handled, in next picture flyback, carried out the reception of next frame and handle.Specifically implementation procedure is, in frame 1 trace interval, frame 1 compressed bit stream data is write in the compressed bit stream buffer unit, in frame 1 retrace interval, reads frame 1 compressed bit stream data and processing from the compressed bit stream buffer unit, and result is write among the SRAM1; In frame 2 trace intervals, frame 2 compressed bit stream data are write in the compressed bit stream buffer unit, in frame 2 retrace intervals, read frame 2 packed datas and processing, result is write among the SRAM2, from SRAM1, read frame 1 restore data simultaneously; In frame 3 trace intervals; Frame 3 compressed bit stream data are write in the packed data buffer memory, in frame 3 retrace intervals, read frame 3 packed datas and processing; The result writes among the SRAM1; From SRAM2, read frame 2 restore data simultaneously, SRAM1 and SRAM2 are according to this table tennis interactive mode, and continuous delivers to every frame restore data in the interface buffer unit.In the read-write operation process of SRAM, write clock with 8 times of high speed clocks, read the same input clock of clock, finally real-time continuous delivers to into restore data in the interface buffer unit.
Communication interface in SAR Data Receiving disposal system of the present invention and the DSP image-forming module realizes through in FPGA, adopting FIFO buffer memory (interface buffer unit).The read-write that FPGA and DSP control FIFO jointly enables.If the data on the FPGA port are ready to, just send and read indication, DSP takes data away; If DSP has handled data, just send and write indication, FPGA sees data off, and both are through the read-write of control interface buffer unit, and the EMIFA mode of utilization DSP is carried out interactive communication.
The unspecified part of the present invention belongs to general knowledge as well known to those skilled in the art.
Claims (3)
1. SAR Data Receiving disposal system, it is characterized in that: said SAR Data Receiving disposal system realizes on a slice fpga chip; Comprise and separate format analysis processing module, compressed bit stream buffer unit, 8 tunnel decompression modules, ping-pong buffer module and interface buffer unit; Wherein every road decompression module comprise string also/and string location, decompression unit and string and unit;
Separate the compressed bit stream that the format analysis processing module is used for the format frame that receives is extracted form frame head and band compression frame head; And compressed bit stream write the compressed bit stream buffer unit, the read operation through control compressed bit stream buffer unit is divided into 8 tunnel mean data and piece packed data with compressed bit stream;
Every road decompression module receives corresponding mean data and piece packed data; String also/and string location is gone here and there to the piece packed data and with and go here and there conversion process; Decompression unit after to conversion packed data and decompress according to the decompression algorithm through the mean data of delay process and to obtain the restore data of fritter; String and unit carry out serial to parallel conversion to restore data, and are written in the ping-pong buffer module;
The ping-pong buffer module is spliced the restore data of fritter, is cached among the SRAM after forming frame data, and through the ping-pong operation to SRAM, continuous delivers to restore data in the interface buffer unit.
2. adopt the described SAR Data Receiving of claim 1 disposal system to carry out the method that the SAR Data Receiving is handled; It is characterized in that: in the trace of a SAR Frame, this frame packed data is write said compressed bit stream buffer unit; In the flyback of current SAR Frame, read packed data from the compressed bit stream buffer unit; Through 8 tunnel decompression modules these frame data are handled then, be connected into a frame restore data through the ping-pong buffer module spliced; In the flyback of next SAR Frame, carry out the processing of next SAR Frame.
3. method as claimed in claim 2, its spy is being: said decompression algorithm use 3bit block adaptive quantization algorithm.
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| CN103150703A (en) * | 2012-11-15 | 2013-06-12 | 长沙景嘉微电子股份有限公司 | Hardware implementation for frame storage data transfer module applied to image processing |
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| CN105426903A (en) * | 2015-10-27 | 2016-03-23 | 航天恒星科技有限公司 | Cloud determination method and system for remote sensing satellite images |
| CN108351406A (en) * | 2015-11-12 | 2018-07-31 | 德州仪器公司 | Buffer samples size for can be changed chirp radar controls |
| CN108351406B (en) * | 2015-11-12 | 2022-08-16 | 德州仪器公司 | Buffer sample size control for variable chirp radar |
| CN108038830A (en) * | 2017-12-18 | 2018-05-15 | 北京理工雷科电子信息技术有限公司 | Software cache technologies are used for the method for SAR image geometric correction |
| CN108038830B (en) * | 2017-12-18 | 2021-05-07 | 北京理工雷科电子信息技术有限公司 | Method for SAR image geometric correction by software cache technology |
| CN110018457A (en) * | 2019-04-11 | 2019-07-16 | 上海卫星工程研究所 | Satellite-borne SAR echo data frame head identifier detection function modularity |
| CN110018457B (en) * | 2019-04-11 | 2023-05-16 | 上海卫星工程研究所 | Method for designing satellite-borne SAR echo data frame header identifier detection functional module |
| CN114928433A (en) * | 2022-01-12 | 2022-08-19 | 中国电子科技集团公司第十研究所 | Low data overhead frame synchronizer |
| CN114928433B (en) * | 2022-01-12 | 2023-06-13 | 中国电子科技集团公司第十研究所 | Low data overhead frame synchronizer |
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