CN114928433B - Low data overhead frame synchronizer - Google Patents
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Abstract
The low-data-overhead frame synchronizer disclosed by the invention has the advantages of low data overhead and low implementation complexity. The invention is realized by the following technical scheme: the frame header detection module carries out frame synchronization code group identification and searching of the frame header according to the matching correlation of the searching fault tolerance threshold, identifies the starting moment of the digital information sequence, generates a data frame starting pulse aligned with first bit data in the data frame, and triggers a signal to start the data frame to be cached from the completion of the searching state to the checking state; the state transition control module generates a trigger pulse by utilizing the rising edge of the locking state indication signal, informs the data output control module, reads out frame data from the data cached by the data caching module, and fills in time code and other information according to specific protocol requirements; the frame synchronization pre-data packaging module adopts a ping-pong read-write operation mechanism to extract the cache data in the data cache module, and packages all data frames in a searching stage and a checking stage before establishing the frame synchronization state and sends the data frames to the upper computer software.
Description
Technical Field
The invention relates to a method for realizing a frame synchronizer, which is mainly used in the communication application fields related to telemetry, data transmission and the like, and is used for processing digital equipment with frame structure information, keeping synchronization when channel error is serious and reducing data overhead before synchronization.
Background
Synchronization is a very important issue in communication systems. The digital communication system includes carrier synchronization, bit synchronization and frame synchronization. Wherein the frame synchronization is mainly used for identifying the frame structure starting position of the receiving end data stream so as to know where the data stream with a specific structure starts, and further performing subsequent information processing based on the structure, such as descrambling, block decoding and the like. Synchronization provides a uniform time scale for communication systems, and is an important guarantee for reliable data transmission between systems. Because modern digital communication devices generally employ parallel technology, it is desirable to design a parallel frame synchronization system. In order to improve transmission efficiency, it is often necessary to combine several low-speed digital signals into one high-speed digital signal for transmission over a high-speed channel. The device that implements this function is called a digital multiplexing system. Frame synchronization is an important component in digital multiplexing systems. Theoretical and engineering practices have demonstrated: the technical performance of the frame synchronization system largely determines the technical performance of the entire digital multiplexing device. Digital multiplexing systems comprise two parts, a transmitting end and a receiving end, commonly referred to as multiplexers and demultiplexers. In order to obtain and maintain the phase relationship of the frame state of the tap relative to the frame state of the multiplexer so as to correctly implement the tap, the digital multiplexing system often inserts a frame synchronization code for synchronization while the transmitting end combines the low-speed digital signal into the high-speed signal; and at the receiving end, the tapping device detects the frame synchronization code in the digital signal at the transmitting end. Since the data stream is a digital information group consisting of several symbols. When the two communication parties carry out data stream transmission, the task of frame synchronization is to identify the starting and ending moments of the digital information group based on bit synchronization information, and generate a timing pulse sequence consistent with the starting and ending moments, namely a frame synchronization signal. It is thus seen that frame synchronization is typically achieved by the sender inserting frame synchronization headers (Attached Synchronization Marker, ASM) between the data blocks, and the receiver identifying these frame synchronization headers. For example, in the telemetry channel synchronization and channel coding standard of the spatial data Consultation Committee (CCSDS) (CCSDS 131.0-B-3), frame synchronization headers from 32 bits to 192 bits in length are recommended for block codes having different frame lengths and coding and decoding gains in order to achieve a frame synchronization function with excellent performance. Two important performance metrics that measure frame synchronization systems are average synchronization search Time (TASC) and average synchronization hold time. The existence of false alarm and false leakage causes the difference of different parallel frame synchronization systems in average synchronization search time. Since only one state machine is used for protection after synchronization, there is no difference in average synchronization hold time. The average sync search time of the frame sync system should be as small as possible. However, performance and area overhead are a pair of contradictions, and the area overhead of a system with good performance is relatively large.
The bit error rate of modern digital communication systems is generally relatively low.For example, the average error rate of the physical layer is specified to be 10 in the 10G Ethernet protocol -12 . However, signal fading, i.e., an increase in bit error rate, sometimes occurs in a communication system, and the signal fading often causes deterioration in the performance of a frame synchronization system. Some frame synchronization systems have good performance at low bit error rates, but suffer from dramatic degradation at high bit error rates, which should be avoided as much as possible.
Therefore, based on the principle of Maximum Likelihood (ML), a frame synchronization strategy with strong robustness necessarily needs to detect based on continuous multi-frame data. Classical frame synchronization strategies employ state transitions between states based on search state, check state, lock state, and loss of gait. The classical frame synchronization implementation method has the advantages and also has limitations in some specific scenes: for example, in the threshold snr condition, it is usually necessary to set a larger number of check frames to ensure that reliable frame synchronization is established, but this also results in an increase in the overhead of frame synchronization—the overhead required for establishing locking of the data frame before locking is not reported as valid information to the upper layer. This is not a problem in communication systems where the data transmission rate is high and the requirements for the effective data volume are not stringent, but when the data transmission rate is low (e.g. a code rate of 32bps in deep space exploration), the transmission time of one frame may reach 2 minutes or even longer, and such overhead becomes not negligible. Furthermore, if the application scenario requires the data amount of the effective data, the overhead may become intolerant, for example, in the critical stage of landing or track change of the detector in the measurement and control communication process, the data amount available on the ground is very small due to factors such as low data transmission rate and limited communication time, and the system needs as much effective data as possible to perform state judgment so as to assist decision.
Disclosure of Invention
Aiming at the defects existing in the prior art, the invention aims to provide the low-data-overhead frame synchronizer which has the advantages of small data overhead, good universality, low implementation complexity and settable synchronization establishment and maintenance time. A frame synchronization method compatible with existing conventional frame synchronizers.
To achieve the above object, the present invention provides a low data overhead frame synchronizer, comprising: according to the data flow, the frame head detection module, the state transfer control module, the data output control module, the data buffer memory module and the frame data packing module are connected in series in sequence, and the frame head detection module is characterized in that the frame head detection module carries out frame synchronization code group identification and searching according to the matching correlation of a search fault tolerance threshold, recognizes the starting moment of a digital information sequence, generates a data frame starting pulse aligned with first bit data in a data frame, and takes the starting pulse as a trigger signal for buffering data before the establishment of a frame synchronization state, and is used for enabling the data buffer memory module to start the buffering of the data frame from the completion of the search state to the check state; after the state transition control module is changed from the checking state to the locking state, a trigger pulse is generated by utilizing the rising edge of a locking state indication signal to inform the data output control module of reading out the data of the frame data stored in the data buffer module buffer, if the locking is not established and the searching state is restored, the buffer address is reset, when the state indication is the searching state, if the data starting pulse is obtained, the 1 st frame data is recorded from the address 0 of the buffer area, then each frame data is respectively stored from the starting address 2048 x 8 x (N-1) until all data frames in the checking state are stored, so as to ensure that invalid data before the frame head is searched next time and stored is covered; after receiving the frame synchronization locking pulse, the data output control module starts a reading flow, reads each frame of data stored in the data buffer module buffer according to the designated data clock beat from the initial address 2048 x 8 x (N-1), sends the frame of data to the frame packing module for packing, and after receiving the frame header pulse indication, the frame packing module stores the data in the data buffer module buffer area by utilizing the data clock and fills in time code and other information according to specific protocol requirements; the frame synchronization pre-data packaging module adopts a ping-pong read-write operation mechanism to extract cache data in the data cache module, and packages all data frames in a searching stage and a checking stage before establishing a frame synchronization state and sends the data frames to upper computer software, wherein N=1, 2 and 3 ….
Compared with the prior art, the invention has the following beneficial effects:
the invention aims to reduce data overhead while guaranteeing frame synchronization performance, and the frame header detection module, the state transition control module, the data output control module and the frame packing module are sequentially connected in series according to the data flow direction, so that the design logic is clear and concise, the synchronization establishment time, the synchronization keeping time and the out-of-step probability can be flexibly set, the invention can be completely compatible with the functional logic of the traditional frame synchronizer, excessive realization resources are not increased, and the hardware realization complexity is low. Has the advantages of flexible configuration and strong anti-interference capability. The pre-data frame storage function can be established by starting or closing frame synchronization under the control of an upper computer.
The invention adopts a frame head detection module to search a frame head according to a fault tolerance threshold, identifies the starting moment of a digital information sequence, and generates a frame starting pulse aligned with a first information bit in a data frame; the module calculates the Hamming distance between the current received data sequence and the preset frame synchronous word, compares the Hamming distance with the fault tolerance threshold and judges whether a frame head is searched; the frame synchronization code group pattern, the frame synchronization code group length and the fault tolerance threshold can be flexibly configured, can adapt to various variable frame structures and synchronization codes, and can adapt to single-frame and multi-frame structures.
The present invention employs a state transition control module to perform state machine control between a search state, a check state, a lock state, and a out-of-sync state, as shown in fig. 2. When a frame header meeting the fault tolerance threshold is searched, the frame header is transferred to a check state, the frame data is simultaneously sent to a packaging module and a data caching module by a data output control module, wherein the packaging module only processes the output data after the locking state, and the data caching module caches the data frame before the frame synchronization state is established (the period from the completion of the search state to the check state). After the check state is shifted, if the setup data frames are continuously detected, the lock state is shifted, and if 1 invalid data frame is detected, the search state is returned. The data frames in the checking state are also sent to the packaging module and the data caching module by the data output control module at the same time, and the packaging module does not process the data frames and the data caching module caches the data frames.
After the state transition control module is adopted to check that the state is changed into the locking state, a trigger pulse is generated by utilizing the rising edge of the locking indication signal to inform the data caching module, and data in the cache is read out and sent to the data packaging module before frame synchronization. The method can ensure that all effective data of a searching stage and a checking stage before frame synchronization state establishment are reserved on the premise of not changing a frame synchronization strategy, so that more effective data is provided, for example, in key stages such as detector landing or track change in the measurement and control communication process, the amount of data which can be received by the ground is extremely small due to factors such as low data transmission rate, limited communication time and the like, and therefore, the effective data before frame synchronization establishment can be provided, and more effective information is provided for decision making.
The invention comprehensively considers the false alarm probability related to the channel error code and the false alarm probability related to the Additional Synchronous Mark (ASM) code pattern, adopts a data output control module to start a reading flow after receiving the frame synchronous locking pulse, reads out the data in the buffer memory according to the appointed data bit clock beat, sends the N frame data in the checking state to a frame packing module for packing, and after the frame packing module receives the frame header pulse indication, the data is stored in a buffer memory area of a data buffer memory module by utilizing the data bit clock and the time code information is filled according to the specific protocol requirement. And after the synchronization is established, the synchronization can be maintained for a long time, so that the telemetry data is recorded continuously and reliably. These data frames are discarded as data overhead during the frame synchronization establishment during operation of the conventional frame synchronizer. In some application scenes, the data frames can provide timely and effective information for the measurement and control communication system, and have high value. Simulation and actual measurement results show that the comprehensive frame synchronization scheme can keep effective frame data before synchronization state establishment, and the frame synchronization performance is consistent with the basic frame synchronization scheme.
The invention adopts a ping-pong read-write operation mechanism of a data packaging module before frame synchronization, and reports the data frame before frame synchronization state establishment sent by a data buffer module to upper computer software according to a specified data format. The module works independently in parallel with the conventional frame synchronization packaging module, so that conventional frame synchronization establishment logic is not affected.
Drawings
FIG. 1 is a schematic diagram of the operation of a low data overhead frame synchronizer of the present invention;
FIG. 2 is a schematic diagram of a detection frame synchronization state transition principle of the frame header detection module of FIG. 1;
FIG. 3 is a timing diagram of the first frame reporting function operation;
FIG. 4 is a schematic diagram illustrating address allocation of the data cache module of FIG. 1.
Detailed Description
See fig. 1. In an exemplary preferred embodiment described below, a low data overhead frame synchronizer includes: according to the data flow, a frame head detection module, a state transfer control module, a data output control module, a data buffer module and a frame data packing module are sequentially connected in series. The frame header detection module carries out frame synchronization code group identification and searching of the frame header according to the matching correlation of the searching fault tolerance threshold, identifies the starting moment of the digital information sequence, generates a data frame starting pulse aligned with first bit data in the data frame, and takes the starting pulse as a trigger signal for caching data before the frame synchronization state is established, so that the data caching module starts the caching of the data frame from the completion of the searching state to the checking state; after the state transition control module is changed from the checking state to the locking state, a trigger pulse is generated by utilizing the rising edge of a locking state indication signal to inform the data output control module of reading out the data of the frame data stored in the data buffer module buffer, if the locking is not established and the searching state is restored, the buffer address is reset, when the state indication is the searching state, if the data starting pulse is obtained, the 1 st frame data is recorded from the address 0 of the buffer area, then each frame data is respectively stored from the starting address 2048 x 8 x (N-1) until all data frames in the checking state are stored, so as to ensure that invalid data before the frame head is searched next time and stored is covered; after receiving the frame synchronization locking pulse, the data output control module starts a reading flow, reads each frame of data stored in the data buffer module buffer according to the designated data clock beat from the initial address 2048 x 8 x (N-1), sends the frame of data to the frame packing module for packing, and after receiving the frame header pulse indication, the frame packing module stores the data in the data buffer module buffer area by utilizing the data clock and fills in time code and other information according to specific protocol requirements; the frame synchronization pre-data packaging module adopts a ping-pong read-write operation mechanism to extract cache data in the data cache module, and packages all data frames in a searching stage and a checking stage before establishing a frame synchronization state and sends the data frames to upper computer software, wherein N=1, 2 and 3 ….
The processing of the frame data before synchronization does not affect the conventional frame synchronization logic, and the output data stream of the data output control module is sent to a frame synchronization packaging flow and a frame synchronization data buffering and packaging two parallel independent processing flows.
See fig. 2. The frame head detection module searches the frame head in the received data sequence by taking the length of the frame synchronization code group as the length of a sliding window in a searching state, judges that the frame synchronization code group is found when the Hamming distance between the data sequence in the sliding window and the frame synchronization code group meets a preset fault tolerance threshold, and independently sets the fault tolerance threshold and the frame length as intervals to detect the frame synchronization code group in a checking state if one frame head is searched; the frame header detection module continuously detects setup frame headers in the checking state and then switches to the locking state, and if an invalid frame header which does not meet the fault tolerance threshold is detected midway, the search state is returned again. After the frame header detection module enters a locking state, continuously detecting the frame synchronization code group by taking the set frame length as an interval, if the valid frame synchronization code group is detected, continuously maintaining the locking state, otherwise entering a non-synchronous state, and if the invalid frame header is detected for the continuous hold-1 time in the non-synchronous state, entering the searching state, otherwise, returning to the locking state. In an alternative embodiment, the number of frame sync word decision fault tolerance bits in each state may be set, and the detection frame number setup and hold values may be set.
See fig. 3. The data output control module starts from searching to a first frame synchronous word according to a time sequence in a time sequence diagram of the first frame reporting function operation, aligns data of a first information bit in a frame header pulse and a data frame in the time sequence, and transmits the data to a post-processing module according to two branches, wherein the first branch is a branch transmitted to a frame packing module or formed by the post-processing module comprising decoding, descrambling and the like, the second branch is a branch special for processing data before a locking state, and when the module of the first branch processes, the data frame in the locking state is processed only by combining the current state of the state transition control module; and the second branch can buffer the data frames in the search state and the check state, and after the frame synchronization state is established, the data frames are packed and output by the frame packing module.
The data buffer module in the second branch mainly comprises a buffer space and control logic for writing/reading data into/from the buffer space. When the state indicates a search state, if a data start pulse is obtained, recording 1 st frame data from address 0 of a buffer area, storing each frame data from start address 2048 x 8 x (N-1) until all data frames in a check state are stored, starting a reading flow by a data output control module after receiving a frame synchronization locking pulse, reading each frame data in the buffer according to a designated data bit clock beat from start address 2048 x 8 x (N-1) respectively, and sending each frame data to a frame packing module for packing, wherein n=1, 2, and 3 …. If the lock is not established and the search state is restored, the write address is reset to ensure that the previous invalid data is covered when the next time the frame header is searched for storage.
After receiving the frame header pulse indication, the frame packing module stores data into an internal buffer area by utilizing a data clock, and fills time code and other information according to specific protocol requirements; the frame synchronization pre-data packaging module adopts a ping-pong read-write operation mechanism to package all data frames in a searching stage and a checking stage before the frame synchronization state is established and send the data frames to upper computer software for external transmission or disk storage. The upper computer is provided with a switch, and can flexibly start or close the data transmission or storage function before frame synchronization.
See fig. 4. The data buffer module divides the storage area according to the length of each row of 1 frame data, and allocates addresses according to the unit of 2048 bytes, namely 16384 bits, of the longest frame length, and the length can be adjusted according to actual requirements. Addressing during writing and reading operations on buffered data is facilitated in frame units.
The frame head detection module sets 0 and 1 with equal probability characteristics in the data stream, and if the position of the frame head is not the position of the frame head, the frame head detection module judges thatFalse alarm probability P of frame header A ：
Calculating frame synchronization false lock probability P of continuous a frames caused by false alarm WS ：
And then adjusting the judgment fault-tolerant bit number in each state and the state transition frame number among the states in the frame synchronization strategy to adapt to the synchronization requirements under various channel conditions.
The state transition control module performs serial/parallel/serial conversion, synchronous code group matching identification, frame supplementing, inverse taking and other data stream control on the data stream according to the data stream identified by the frame header detection module, gives out single-frame, multi-frame synchronous signals and word synchronous signals of the data, and gives out required frame matching state signals.
The data output control module divides the working state of frame synchronization into a capturing state and a tracking state, controls the data flow and outputs corresponding synchronous signals, detects single frames/sub frames in parallel in the capturing and tracking states, adaptively switches the threshold of a frame header and the threshold judgment of capturing out-of-step, adjusts the threshold according to the capturing and tracking states of the system, carries out matching correlation and threshold judgment, and carries out frame compensation correction processing on the data frames after frame synchronization, thereby realizing capturing and tracking of the frames, frame compensation and inverse. To accommodate different synchronization code sets and fault tolerance requirements. Improving system performance. The single frame/sub-frame parallel detection can reduce the re-capture caused by the loss of the single frame or the sub-frame, and improve the out-of-step re-capture speed. And for the loss of the positive synchronous code group in the fault tolerance range, the pseudo-step-out distinguishing capability of the system can be improved through the frame compensation correction processing.
After receiving the frame synchronization locking pulse, the data output control module outputs a control signal, starts a reading flow, reads out the data in the buffer according to the designated data clock beat, sends out a frame header pulse before locking, uses the frame header pulse in combination with the frame synchronization locking state, sends the first frame to the frame packing module for packing, and after receiving the frame header pulse indication, the frame packing module stores the data into a buffer area of the data buffer module by utilizing the data clock and fills time code information according to the specific protocol requirement; the method adopts a ping-pong read-write operation mechanism to convert the configured length information into initial time information of a synchronous signal, a table is searched for outputting a single frame, a multi-frame and a word synchronous signal, data under a locked state condition is reported through a data reporting interface channel between the table-tennis read-write operation mechanism and an upper computer, a switch is provided, a data sending or storage function before frame synchronization can be started or closed, and the data reporting and storage functions of the two branches are independently decoupled.
The foregoing describes in detail embodiments of the present invention, which are described herein using specific embodiments, the description of the embodiments being merely intended to aid in the understanding of the methods and apparatus of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (10)
1. A low data overhead frame synchronizer comprising: according to the data flow, the frame head detection module, the state transfer control module, the data output control module, the data buffer memory module and the frame data packing module are connected in series in sequence, and the frame head detection module is characterized in that the frame head detection module carries out frame synchronization code group identification and searching according to the matching correlation of a search fault tolerance threshold, recognizes the starting moment of a digital information sequence, generates a data frame starting pulse aligned with first bit data in a data frame, and takes the starting pulse as a trigger signal for buffering data before the establishment of a frame synchronization state, and is used for enabling the data buffer memory module to start the buffering of the data frame from the completion of the search state to the check state; after the state transition control module is changed from the checking state to the locking state, a trigger pulse is generated by utilizing the rising edge of a locking state indication signal to inform the data output control module, data stored in the data buffer module in frame data are read out from the buffer memory, if the locking is not established and the searching state is restored, the buffer memory address is reset, when the state indication is the searching state, if a data starting pulse is obtained, the 1 st frame data is recorded from the address 0 of the buffer memory area, then each frame data is respectively stored from the starting address 2048 x 8 x (N-1) until all data frames in the checking state are stored, so that invalid data before the frame head is searched next time and the frame head is stored are covered; after receiving the frame synchronization locking pulse, the data output control module starts a reading flow, reads each frame of data stored in the data buffer module from a starting address 2048 x 8 x (N-1) according to a designated data clock beat, reads the frame of data from a buffer, sends the frame of data to the frame data packing module for packing, and after receiving a frame header pulse instruction, the frame data packing module stores the data into a buffer area of the data buffer module by utilizing a data clock and fills time code information according to specific protocol requirements; before frame synchronization, the frame data packaging module adopts a ping-pong read-write operation mechanism to extract cache data in the data cache module, and packages all data frames in a searching stage and a checking stage before frame synchronization state establishment and sends the data frames to upper computer software, wherein N=1, 2 and 3 ….
2. The low data overhead frame synchronizer of claim 1, wherein: and in a searching state, the frame header detection module searches the frame header in the received data sequence by taking the length of the frame synchronization code group as the length of the sliding window, judges that the frame synchronization code group is found when the Hamming distance between the data sequence in the sliding window and the frame synchronization code group meets the preset fault-tolerant threshold, and independently sets the frame length of the fault-tolerant door as an interval detection frame synchronization code group in a checking state if one frame header is searched, and changes into the checking state.
3. The low data overhead frame synchronizer of claim 2 wherein: the frame header detection module continuously detects setup frame headers in a checking state and then switches to a locking state, and if an invalid frame header which does not meet a fault tolerance threshold is detected midway, the frame header detection module returns to a searching state again; after the frame header detection module enters a locking state, continuously detecting frame synchronization code groups by taking a set frame length as an interval, if a valid frame synchronization code group is detected, continuously maintaining the locking state, otherwise entering an out-of-step state, if invalid frame headers are detected continuously hold-1 times in the out-of-step state, entering a searching state, otherwise, returning to the locking state, wherein a setup value is the number of data frames required to be detected in a checking state and is configurable as a frame synchronizer parameter, and a hold value is the number of invalid frame headers required to be continuously detected when returning to the searching state from the synchronizing state and is configurable as a frame synchronizer parameter.
4. The low data overhead frame synchronizer of claim 1, wherein: the data output control module aligns the frame header pulse under the time sequence with the rising edge of the first information bit in the data frame from searching to the first frame synchronous word according to the time sequence in the operation time sequence diagram of the first frame reporting function, and transmits the data to the post-processing module according to the two branches.
5. The low data overhead frame synchronizer of claim 4 wherein: the first branch is transmitted to a frame data packaging module or a branch formed by a later-stage module comprising decoding and descrambling, and the second branch is a branch special for processing data before a locking state, wherein the module of the first branch only processes the data frame in the locking state in combination with the current state of a state transition control module when processing; and the second branch can buffer the data frames in the search state and the check state, and after the frame synchronization state is established, the data frames are packed and output by the frame data packing module.
6. The low data overhead frame synchronizer of claim 5 wherein: the data buffer module in the second branch comprises a buffer space and control logic for writing/reading data into/from the buffer space; when the state indicates the search state, if the data start pulse is obtained, the 1 st frame data is recorded from the address 0 of the buffer area, and then each frame data is stored from the start address 2048 x 8 x (N-1) until all the data frames in the check state period are stored.
7. The low data overhead frame synchronizer of claim 6 wherein: after receiving the frame synchronization locking pulse, the data output control module starts a reading flow, reads each frame of data in the buffer memory from a starting address 2048 x 8 x (N-1) according to a designated data clock beat, sends each frame of data to the frame data packing module for packing, and resets a writing address if the locking is not established and a searching state is restored, so as to ensure that the previous invalid data is covered when the frame head is searched for storage next time, wherein n=1, 2 and 3 ….
8. The low data overhead frame synchronizer of claim 1, wherein: after receiving the frame header pulse indication, the frame data packaging module stores data into an internal cache area by utilizing a data clock and fills time code information according to specific protocol requirements; before frame synchronization, the frame data packaging module adopts a ping-pong read-write operation mechanism to package all data frames in a searching stage and a checking stage before frame synchronization state establishment and send the data frames to upper computer software for external transmission or disk storage.
9. The low data overhead frame synchronizer of claim 1, wherein: the data buffer module divides the storage area according to each row of 1 frame data length, allocates addresses according to the unit of 2048 bytes, namely 16384 bits, of the longest frame length, and performs addressing when writing and reading operations are performed on the buffer data according to the unit of frames.
10. The low data overhead frame synchronizer of claim 1, wherein: the frame head detection module sets 0 and 1 with equal probability characteristics in the data stream, and if the position of the frame head is not the position of the frame head, the frame head detection module judges the false alarm probability of the frame head
：
In the method, in the process of the invention,Mis the frame header length;
the same occurrence probability of 0, 1;Jdetermining the fault-tolerant bit number; calculation of continuityaFrame synchronization false lock probability caused by false alarm>
And average probability of lock-in->
：
In the method, in the process of the invention,Nis a frame length;
the probability of frame synchronization missing detection is determined; and then adjusting the judgment fault-tolerant bit number in each state and the state transition frame number among the states in the frame synchronization strategy to adapt to the synchronization requirements under various channel conditions. />
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