CN202794553U - Cascade connection collection station efficient flow line data transmission system for seismic exploration - Google Patents
Cascade connection collection station efficient flow line data transmission system for seismic exploration Download PDFInfo
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- CN202794553U CN202794553U CN2012204352580U CN201220435258U CN202794553U CN 202794553 U CN202794553 U CN 202794553U CN 2012204352580 U CN2012204352580 U CN 2012204352580U CN 201220435258 U CN201220435258 U CN 201220435258U CN 202794553 U CN202794553 U CN 202794553U
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Abstract
The utility model provides a cascade connection collection station efficient flow line data transmission system for seismic exploration. A master control station is respectively connected with cross stations through two low voltage differential signaling (LVDS) ports, each cross station uses four LVDS ports, uplink ports are in the direction of the master control station, downlink ports are connected with the cross stations in the next stage, left ports and right ports are respectively connected with collection stations, each collection station respectively uses two LVDS ports, and high speed data transmission technology based on LVDS is adopted between the collection stations, between the collection stations and the cross stations and between the cross stations and the master control station. The cascade connection collection station efficient flow line data transmission system has the advantages of being based on the LVDS technology, using a field programmable gate array (FPGA) control logic to directly drive hardware, being capable of meeting high data rate requirements in a seismic exploration system, and being simple in structure and low in transmission error rate.
Description
Technical field
The utility model relates to the transmission of seismic data technology in the geophysical instrument, specially refers to the data transmission system for seismic prospecting.
Background technology
The land seismic data transmission systems of 428XL of the at present both at home and abroad data transmission system subordination in comparatively common seismic prospecting instrument France Sercel company, several biography system in the land seismic detector system in the ES109 of PetroChina Company Limited. ten thousand roads, " high-resolution multi-channel seismic exploration data transmission system at shallow layer of deepwater " patent (CN201010226156.3) of Oceanographic Inst. No.1 of State Bureau of Oceanography's application.
France Sercel company has accumulated many years of experience in seismic instrument development aspect by land, 428 series of its up-to-date release, and function is more powerful after improve on its basis of 408.Data transmission system is divided into two-stage in the 428 serial instruments, and the first order is the transmission system between acquisition station, because its unexposed detail is unable to find out the concrete transmission technology that it adopts; The second level is the transmission system between cross-station, and it has adopted the 100 m ethernet transmission mode based on ICP/IP protocol.Transmission mode based on Ethernet protocol needs bottom-layer network stack software as support, and this needs bottom embedded OS software support usually, and the real-time of data transmission is relatively poor like this, and transfer efficiency is low; For cross-station, this also can increase cross-station complexity and power consumption etc.
The parallel RS485 transmission mode of several biography system's employings in the land seismic detector system in the ES109 of PetroChina Company Limited. ten thousand roads, and No. 201110221626.1 utility application discloses a kind of data transmission system that is used for seismic prospecting that adopts parallel RS485 transmission mode.Because the data transfer rate that system needs is higher, and RS485 data transfer rate under long Distance Transmission is lower usually, so it has adopted the mode of multidiameter delay transmission to satisfy the needs of the high data transmission rate of system.Adopt the RS485 transmission technology, the bottom hardware circuit is realized simple, simple for structure, but owing to need to carry out cutting between the multi-channel data transmission and the restructuring of scheduling and receive data, the whole system complexity increases, and common RS485 chip power-consumption is all higher, and the result of multidiameter delay causes transmission system consumption power consumption very high, for extensive seismic prospecting instrument, this transmission technology can propose very high requirement to the electric power system of whole seismic prospecting instrument.
No. 201010226156.3 patent of Oceanographic Inst. No.1 of State Bureau of Oceanography's application, name is called the transmission mode that has adopted a kind of direct physical chip Network Based in " high-resolution multi-channel seismic exploration data transmission system at shallow layer of deepwater ", also be a kind of network transfer method in essence, yet owing to lost the ICP/IP protocol layer, so need not the bottom layer driving software support, directly add the high-speed transfer that steering logic can be finished data by hardware cell, but this transmission method can't be realized the high-precise synchronization collection of whole system.
To sum up, data transmission system in the seismic prospecting system, on the one hand because the resource limitation of bottom acquisition station or cross-station, need the real-time data transmission that will at every turn gather to master station, so data transmission rate of having relatively high expectations, because data transmission system is one of core of whole prospecting instrument system, so require data transmission system as far as possible simple in structure, transmission error rates is low on the other hand.Data transmission system in the seismic prospecting system adopts more technology to be based on the transmission technology of Ethernet at present, 428 serial instruments such as French Sercel company, its cross spider has just adopted the Ethernet transmission technology based on ICP/IP protocol, this transmission plan technology maturation, but relative complex needs the support of bottom software; Another kind of several transmission methods commonly used are based on the RS485 technology, this also is the comparatively ripe transmission technology of industry member, yet because RS485 is long lower apart from data transfer rate in the situation, so be the High Data Rate requirement in the reply seismic prospecting system, usually require multichannel RS485 parallel transmission, cause whole transmission system consumption power consumption larger; Also be based on the technology of Internet Transmission on the technological essence that transmits for direct driving networked physics layer chip, owing to skipped the ICP/IP protocol layer, so its structure is comparatively simple, but because still technology Network Based in essence, so the system synchronization low precision can't be realized the high-precise synchronization collection of whole system.
The utility model content
The technical problems to be solved in the utility model provides the cascade acquisition station high performance pipeline number biography system data transmission system that is used for seismic prospecting that a kind of data transmission rate is high, structure is simple, transmission error rates is low.
The utility model solves the problems of the technologies described above by the following technical solutions: a kind of cascade acquisition station high performance pipeline number for seismic prospecting passes system, comprise master station, a plurality of cross-stations, a plurality of acquisition stations, and wave detector, described master station is connected to cross-station, the mutual cascade of a plurality of cross-stations, the left and right sides of each cross-station is a plurality of acquisition stations of cascade respectively, and connect one or more wave detectors on each acquisition station, between the cross-station and the data transmission between cross-station and the master station finished by large line, branch line finish between the acquisition station and acquisition station and cross-station between data transmission, described master station uses two LVDS interfaces, be connected respectively to cross-station, each cross-station uses four LVDS interfaces, be respectively upstream Interface, downstream interface, left side interface and right side interface, wherein upstream Interface is the direction to master station, downstream interface is connected to the cross-station of next stage, left side interface and right side interface connect respectively acquisition station, each acquisition station uses respectively two LVDS interfaces, be respectively left side interface and right side interface, large line and branch line adopt identical transmission technology, namely based on the Highspeed Data Transmission Technology of LVDS.
The utility model can be optimized for: be provided with the high speed data transfer circuit in described each master station, cross-station, the acquisition station, this high speed data transfer circuit comprises two paths: transmitting uplink data path and down order transmission channel;
Transmitting uplink data path and down order transmission channel in described cross-station and the acquisition station include FPGA, self-adaptation cable balanced device, deserializer, parallel-to-serial converter, the serial digital cable driver, described self-adaptation cable balanced device, deserializer, FPGA, parallel-to-serial converter, the serial digital cable driver sequentially connects, wherein FPGA finishes deserializer, the driving of parallel-to-serial converter, self-adaptation cable balanced device receives the signal input from the LVDS interface, finish the filtering of input signal, its output signal is connected to string and the conversion of deserializer settling signal, finally is input to the reception that FPGA finishes data; At drive end, FPGA sends to parallel-to-serial converter with parallel data, at first finishes the parallel-serial conversion of data, and then the parallel-to-serial converter output signal finally is transformed into the LVDS signal from another LVDS interface output to the serial digital cable driver;
The data transmission circuit that arranges in the described master station comprises the LVDS input circuit, FPGA and LVDS output circuit, described LVDS input circuit comprises self-adaptation cable balanced device and deserializer, the LVDS output circuit comprises parallel-to-serial converter and serial digital cable driver, the input driver module is set in the FPGA, output driver module and storer, described input driver module is connected to the deserializer of LVDS input circuit, the output driver module is connected to the parallel-to-serial converter of LVDS output circuit, and input driver module and output driver module all are connected to described storer.
The utility model can further be optimized for: be provided with the circuit of realizing the pipeline system data transmission method among the FPGA of described each cross-station and acquisition station;
The circuit of the realization pipeline system data transmission method in the FPGA of described acquisition station comprises such as lower module: 1) local frame makes up module, is connected to acquisition station at the corresponding levels, and this module is finished the frame building work of each image data; 2) local FIFO buffer and the FIFO of subordinate buffer, these FIFO buffers are finished the buffer memory of data, local FIFO buffer input end is connected to local frame and makes up module, the input end of the FIFO of subordinate buffer is connected to the input driver module, the output terminal of local FIFO buffer and the FIFO of subordinate buffer all is connected to the output driver module, data in output driver module read local FIFO buffer and the FIFO of the subordinate buffer send, same, the input driver module is deposited into the FIFO of the subordinate buffer from the data that subordinate receives; 3) input driver module and output driver module are finished the driving of external hardware circuit, namely are connected respectively to described deserializer and parallel-to-serial converter, are used for respectively driving deserializer and parallel-to-serial converter; 4) steering logic, steering logic are connected respectively to input driver module and output driver module, provide the sequential of input driver module and output driver module read local FIFO buffer and the FIFO of subordinate buffer;
The circuit of the realization pipeline system data transmission method in the FPGA of described cross-station comprises such as lower module: the 1) FIFO of subordinate buffer, these FIFO buffers are finished the buffer memory of data, the input end of the FIFO of subordinate buffer is connected to the input driver module, output terminal all is connected to the output driver module, the data that the output driver module reads in the FIFO of the subordinate buffer send, same, the input driver module is deposited into the FIFO of the subordinate buffer from the data that subordinate receives; 2) input driver module and output driver module are finished the driving of external hardware circuit, namely are connected respectively to described deserializer and parallel-to-serial converter, are used for respectively driving deserializer and parallel-to-serial converter; 3) steering logic, steering logic are connected respectively to input driver module and output driver module, provide the sequential that input driver module and output driver module read the FIFO of subordinate buffer.
The utility model can further be optimized for again: the calibration circuit that is provided with data transmission among the FPGA in described acquisition station and the cross-station, described calibration circuit is carried out once at each initialization procedure that this cascade acquisition station high performance pipeline number that is used for seismic prospecting passes system, finish data transmission synchronous calibration work constantly, the delay time register that described calibration circuit comprises counting module and is connected to counting module, described counting module is connected respectively to the FPGA interior input driver module of down order transmission channel and the interior output of the FPGA driver module of transmitting uplink data passage, after the input driver module of down order transmission channel receives the synchronous calibration order, start counting module, after the output driver module superior loopback synchronous calibration order of transmitting uplink data passage, stop counting module, the numerical value of preserving in the counting module is divided by 2, be saved in the delay time register, also just obtained the one-way latency time of our station, after finishing calibration operation, each after acquisition station or cross-station receive other orders, all postpone a period of time by the time value of preserving in the delay time register after just execution.
The utility model has the advantage of:
1. design a kind of cascade acquisition station high speed data transfer circuit, this transmission circuit directly drives hardware based on the LVDS transmission technology by the FPGA steering logic, the contentedly requirement of High Data Rate in the seismic exploration system, and structure is simple, transmission error rates is low.
2. design a kind of data transmission circuit of pipeline system, this circuit is based on the synchronism of each acquisition station transmission time, each acquisition station transmits at the same time point, each acquisition station is in this DBMS of transmission, buffer memory is from the data of subordinate's acquisition station, whole system is finished the data transmission of pipeline system, has increased data transmission efficiency.
3. design a kind of synchronizing circuit of data transmission, this circuit is that the pipeline system data transmission is given security, and utilizes this synchronizing circuit, and each acquisition station will carry out data transfer at identical time point.
Description of drawings
Figure 1 shows that the data transmission system overall topological structure figure of the utility model seismic prospecting.
Figure 2 shows that the utility model is used for the high speed data transfer circuit theory diagrams based on LVDS of the cascade acquisition station high performance pipeline number biography system of seismic prospecting.
Figure 3 shows that the circuit theory diagrams of the pipeline system data transmission method that the utility model uses.
Figure 4 shows that data transmission calibration circuit schematic diagram constantly in the acquisition station.
Figure 5 shows that data transmission synchronization calibration design sketch in the acquisition station.
Shown in Figure 6 is the interior data transmission circuit structure figure of master station.
Fig. 7 is the data transmission method flowchart that the utility model is used for the cascade acquisition station high performance pipeline number biography system of seismic prospecting.
Embodiment
Data transmission system in the seismic prospecting instrument is one of core of whole prospecting instrument, finishes the harmless uploading operation of image data.Usually because the finiteness of bottom acquisition station resource, can't finish the large capacity storage of data, so each data that gather all want the real-time master station that uploads to carry out data buffer storage, high precision (24-bit) and sampling rate (typical 1ksps) requirement based on seismic prospecting instrument, system must support higher data transmission rate usually, and require the lower bit error rate and higher real-time, this design to data transmission system has proposed higher requirement.
Figure 1 shows that the data transmission system overall topological structure figure of the utility model seismic prospecting.As can see from Figure 1, the data transmission system of the utility model seismic prospecting comprises master station 10, a plurality of cross-station 20, a plurality of acquisition station 30, and wave detector 40.
Described master station 10 both sides cascade cross-stations 20, for sending order and reception to cross-station 20 from the data of cross-station 20, described master station 10 uses two LVDS(Low Voltage Differential Signaling, Low Voltage Differential Signal) interface, be connected respectively to cross-station 20.
A plurality of cross-station 20 mutual cascades, each cross-station 20 uses four LVDS interfaces, is respectively upstream Interface, downstream interface, left side interface and right side interface.Wherein upstream Interface is the direction to master station 10, downstream interface is connected to the cross-station 20 of next stage, left side interface and right side interface connect respectively acquisition station 30, the left and right sides of each cross-station 20 is a plurality of acquisition stations 30 of cascade respectively, cross-station 20 is used for to the order of other cross-stations 20 forwarding master stations 10 of acquisition station 30 or vicinity, receive simultaneously the data from other cross-stations 20 of acquisition station 30 or vicinity, and be uploaded to master station 10.
Each acquisition station 30 uses respectively two LVDS interfaces, be respectively left side interface and right side interface, and connect one or more wave detectors 40 on each acquisition station 30, be used for collection signal, adopt the difference cable to connect between acquisition station 30 and the wave detector 40, acquisition station 30 is used for receiving the seismic signals of wave detector 40 collections and is uploaded to cross-station 20 and carries out the order that master station 10 issues.
Between the cross-station 20 and the data transmission between cross-station 20 and the master station 10 finished by large line 12, branch line 32 finish between the acquisition station 30 and acquisition station 30 and cross-station 20 between data transmission, higher the closer to top layer data transmission rate demand, top layer namely refers to the direction of master station 20, and that cross-station 20 and the data transmission rate between the master station 10 of the most close master station 20 are the highest.In the utility model, large line 12 and branch line 32 adopt identical transmission technology, namely based on the Highspeed Data Transmission Technology of LVDS.
As the example of an implementation, large line 12 and branch line 32 all adopt unshielded twisted pair.
See also Fig. 2, Figure 2 shows that the utility model is used for the high speed data transfer circuit theory diagrams based on LVDS of the cascade acquisition station high performance pipeline number biography system of seismic prospecting.This high speed data transfer circuit is arranged in each cross-station 20 and the acquisition station 30.Data transmission all needs two passages: upstream data passage and down order passage, the required hardware of upstream data passage and down order passage is identical.This high speed data transfer circuit comprises FPGA(Field-Programmable Gate Array, field programmable gate array) 50, descending LVDS input circuit 52, descending LVDS output circuit 54, up LVDS input circuit 56, and up LVDS output circuit 58.Described descending LVDS input circuit 52 and up LVDS input circuit 56 structures are identical, and descending LVDS output circuit 54 and up LVDS output circuit 58 structures are identical, and the below introduces this high speed data transfer circuit as an example of the down order passage example.
Described descending LVDS input circuit 52 comprises self-adaptation cable balanced device 522 and deserializer 524, and descending LVDS output circuit 54 comprises parallel-to-serial converter 542 and serial digital cable driver 544.Described self-adaptation cable balanced device 522, deserializer 524, FPGA 50, parallel-to-serial converter 542, serial digital cable driver 544 sequentially connect.Wherein FPGA 50 finishes the driving of deserializer 524, parallel-to-serial converter 542.Self-adaptation cable balanced device 522 receives the signal input from the LVDS interface, finish the filtering of input signal, increase the integrality of input signal, its output signal is connected to string and the conversion of deserializer 524 settling signals, finally is input to the reception that FPGA50 finishes data; At drive end, FPGA 50 sends to parallel-to-serial converter 542 with parallel data, at first finish the parallel-serial conversion of data, then parallel-to-serial converter 542 output signals are to serial digital cable driver 544, finally be transformed into the LVDS signal from another LVDS interface output, be sent to subordinate by unshielded twisted pair.The driving clock ranges of deserializer 524 and parallel-to-serial converter 542 is 10MHz-66MHz, can finish 100Mbps to the interior data transfer task of 660Mbps scope, can satisfy the high speed data transfer requirement of basic all seismic prospecting instruments.
Example as an implementation, the model of described deserializer 524 is SN65LV1224, the model of parallel-to-serial converter 542 is 56SN65LV1023, the model of self-adaptation cable balanced device 522 is CLC012, the model of serial digital cable driver 544 is CLC001, and certainly, this field those skilled in the art all know, these equipment all can adopt the equipment of other models to substitute, and can reach identical function equally.
Figure 3 shows that the circuit of the pipeline system data transmission method that the utility model uses.This circuit is the FPGA of each acquisition station 50 inner realizations.The circuit of the pipeline system data transmission method of FPGA 50 inside comprises such as lower module: 1) local frame makes up module 502, be connected to acquisition station 30 at the corresponding levels, this module is finished the frame building work of each image data, the position of the necessary flag data acquisition station 30 of each data that gather and other information of acquisition station 30, such as current acquisition station temperature, voltage etc., the data that these information gather together with wave detector 40 must be packaged together and upload; 2) local FIFO(first-in first-out) buffer 504 and four FIFO of subordinate buffers 505, these FIFO buffers are finished the buffer memory of data, local FIFO buffer 504 input ends are connected to local frame and make up module 502, wherein the input end of two FIFO of subordinate buffers 505 is connected to up input driver module 506, the output terminal of local FIFO buffer 504 and above-mentioned two FIFO of subordinate buffers 505 all is connected to line output driver module 507, the input end of two FIFO of subordinate buffers 505 and the input end of local FIFO buffer 504 are connected to descending input driver module in addition, the output terminal of two FIFO of subordinate buffers 505 is connected to lower line output driver module in addition, upper line output driver module 507 sends the data in read local FIFO buffer 504 and the FIFO of the subordinate buffer 505, same, up input driver module 506 will be deposited into from the data that subordinate receives the FIFO of the subordinate buffer 505, the order that lower line output driver module will read in the FIFO of the subordinate buffer 505 sends, same, descending input driver module will receive order from the higher level and be deposited into local FIFO buffer 504 and the FIFO of the subordinate buffer 505; 3) up input driver module 506, upper line output driver module 507, descending input drives mould, and lower line output driver module, finish the driving of external hardware circuit, described descending input driver module and up input driver module 506 are connected respectively to described descending LVDS input circuit 52 and up LVDS input circuit 56, lower line output driver module and upper line output driver module 507 are connected respectively to descending LVDS output circuit 58 and up LVDS output circuit, namely input driver module and be connected respectively to corresponding deserializer, the output driver module is connected respectively to corresponding parallel-to-serial converter, is used for respectively driving deserializer and parallel-to-serial converter; 4) upload control logic 508 and descending steering logic, upload control logic 508 is connected respectively to up input driver module 506 and upper line output driver module 507, provide the sequential of up input driver module 506 and upper line output driver module 507 read-write FIFO buffers, descending steering logic is connected respectively to descending input driver module and lower line output driver module, provides the sequential of descending input driver module and lower line output driver module read-write FIFO buffer.
This pipeline system data transmission method is achieved as follows: acquisition station 30 adopts single acquisition, the single transmission working method, and namely each data that gather were finished before collection next time arrives constantly and are uploaded.Take certain collection as example, after AD translation circuit in the acquisition station 30 is finished the collection of simulant signal that wave detector 40 provides, the clear data that collects is sent to FPGA 50, local frame in the FPGA 50 makes up module 502 and finishes the establishment that this sends frame, and the frame after will creating by the agreement prescribed form writes in the local FIFO buffer 504, after upper line output driver module 507 receives this data upload order, log-on data transmits, the at first preferential data that send in the local FIFO buffer 504, after data are sent in the local FIFO buffer 504, just carry out the transmission work of data in the FIFO of the subordinate buffer 505.Because it all is synchronous that the data of each acquisition station 30 send, be that each log-on data is when uploading, each acquisition station 30 at first sends the local frame of storage in the local FIFO buffer 504, up input driver module 506 receives the local frame of subordinate that subordinate's acquisition station 30 is uploaded from subordinate simultaneously, and be prestored in the FIFO of the subordinate buffer 505, when the frame data in the local FIFO buffer 504 are sent out when complete, also finish the reception work of subordinate's one frame data in the FIFO of the subordinate buffer 505, line output driver module 507 switches to the FIFO of subordinate buffer 505 on this moment, carries out the forwarding work of subordinate's frame.Simultaneously up input driver module 506 continues to receive frame data of being transmitted by subordinate's acquisition station 30, so the FIFO of subordinate buffer 505 has two, adopts the ping-pong type mode to carry out the forwarding work of frame.The switching sequence of local FIFO buffer 504 and the FIFO of subordinate buffer 505 is controlled by steering logic 508.The realization that down order sends is similar to the realization of above-mentioned pipeline system data transmission method, repeats no more.
Certainly, the circuit that also has described pipeline system data transmission method in the FPGA 50 of described each cross-station 20, but because cross-station 20 does not need data acquisition, the forwarding of just lower DBMS, therefore, the circuit of the realization pipeline system data transmission method in the FPGA 50 of cross-station 20 does not comprise that above-mentioned local frame makes up module 502 and local FIFO buffer 504, and the circuit of the realization pipeline system data transmission method in other structures and the above-mentioned acquisition station 30 is identical.
Figure 4 shows that cross-station 20 and acquisition station 30 interior data transmission calibration circuit constantly, described calibration circuit is also the FPGA of each cross-station 20 and acquisition station 30 50 inner realizations.Carry out once in the each initialization procedure of calibration circuit, finish data transmission synchronous calibration work constantly.Described calibration circuit comprises the counting module 60 that is connected to up input driver module 506 and lower line output driver module, and the delay time register 70 that is connected to counting module 60.Synchronous transmission calibration is constantly finished by calibration command.
Take acquisition station as example, the course of work of this calibration circuit is as follows.After the descending input driver module of each acquisition station 30 receives the synchronous calibration order, start counting module 60, to order simultaneously by lower line output driver module and be forwarded to next stage acquisition station 30, subordinate's acquisition station 30 is finished identical action, and to the last the one-level acquisition station 30.After afterbody acquisition station 30 receives the synchronous calibration order, owing to be afterbody, it is not transmitted, but by upper this synchronous calibration order of line output driver module 507 superior loopbacks, after the descending input driver module of afterbody acquisition station 30 receives the synchronous calibration order, start counting module 60 and begin counting, after the upper line output driver module 507 superior loopback synchronous calibration orders, stop counting module 60, the numerical value that preserve in the counting module 60 this moment is exactly the internal latency time of this afterbody acquisition station 30, with this numerical value divided by 2, be saved in the delay time register 70, the one-way latency time that just represents this afterbody acquisition station 30, intergrade and first order acquisition station 30 are same after the synchronous calibration order that receives last loopback, when being transmitted to the higher level, stop counting module 60 countings, and with the numerical value preserved in the counting module 60 divided by 2, be saved in the delay time register 70 of self, also just obtained the one-way latency time of this acquisition station 30.After finishing calibration operation, at every turn after acquisition station 30 receives other orders (asynchronous calibration command), just carry out after all postponing a period of time by the time value of preserving in the delay time register 70, to reach each acquisition station 30 fill order simultaneity constantly, all be to be triggered by the upload command that master station 10 sends based on every data transfer, and then finish the synchronism of transmission time.
Fig. 5 is constantly synchronous calibration design sketch of acquisition station data transmission.Take monolateral acquisition station 30 arrays that are connected with cross-station 20 as example, first direct-connected acquisition station 30 of node 1 expression and cross-station 20 among Fig. 5, node 2 is second direct-connected acquisition station 30 of first acquisition station 30, and by that analogy, node n is last acquisition station 30 of this side line.Finishing by two conditions of data synchronous transmission guarantees: the 1) synchronous calibration of command execution; 2) command triggers of every data transfer.The synchronous calibration of command execution is finished in system initialisation phase, and the upload command of the command triggers of every data transfer after by each data acquisition finished.As shown in Figure 5, after each acquisition station 30 receives order, do not carry out at once, but just carry out after postponing a period of time, the time of delay is obtained by the calibration circuit of realizing among Fig. 4, is saved in the delay time register 70 of this acquisition station 30 inside.Can reach like this each acquisition station 30 fill order synchronism constantly.Acquisition station 30 adopts single acquisition, the mode of single transmission, each transmission triggers by the upload command that sends by the acquisition interval time (being the sampling period), thereby reach the synchronism of each acquisition station 30 data transmission, thereby finish the efficient data transmission method of pipeline system between the acquisition station 30.
Through actual measurement, calibrate fixed delay of existence between front four acquisition stations, this mainly is that command transfer postpones to add the result that the acquisition station internal logic postpones, and calibrates and has substantially finished between rear four acquisition stations 30 synchronously, only has the jitter error of a clock.
Because the data that master station 10 does not need the buffer memory next stage to transmit, do not need synchronous calibration yet, therefore shown in Figure 6 is data transmission circuit structure figure in the master station 10, and the data transmission circuit of master station 10 interior settings comprises LVDS input circuit 102, FPGA 104 and LVDS output circuit 106.Described LVDS input circuit 102 comprises self-adaptation cable balanced device 1022 and deserializer 1024, and LVDS output circuit 106 comprises parallel-to-serial converter 1062 and serial digital cable driver 1064.FPGA 104 interior input driver module 1042, output driver module 1044 and the storeies 1046 of arranging, described input driver module 1042 is connected to the deserializer 1024 of LVDS input circuit 102, output driver module 1044 is connected to the parallel-to-serial converter 1062 of LVDS output circuit 106, input driver module 1042 and output driver module 1044 all are connected to described storer 1046, input driver module 1042 is put into storer 1046 with the data of collecting and is stored, and the order in the storer 1046 issues by output driver module 1044.Described storer 1046 is connected to system work station by network interface or USB interface.The principle of work of the circuit module in the master station 10 all principle of work with the interior same circuits module of cross-station 20 and acquisition station 30 is identical.
The data transmission method flowchart that above-mentioned cascade acquisition station high performance pipeline number for seismic prospecting passes system comprises the steps: as shown in Figure 7
Step 1: carry out initial work after system powers on, in initialization procedure, finish each cross-station 20 and acquisition station 30 command execution synchronous calibration constantly, this sends the synchronous calibration order by master station 10 and finishes, from system level, synchronous calibration is divided into two stages to be finished: 1) finish the synchronous calibration of each cross-station 20 on the large line 12, the synchronous calibration process of cross-station 20 is with acquisition station 30, and specific implementation process is seen above-mentioned explanation in conjunction with Fig. 4; 2) finish the synchronous calibration of each acquisition station 30 on each branch line 32, after synchronous calibration was finished, each cross-station 20 and acquisition station 30 internal latency registers 70 had all been preserved the each fill order of our station (the every other order outside the asynchronous calibration command) fixed delay time before;
Step 2: after initialization was finished, each acquisition station 30, cross-station 20 entered into the order cycle detection stage, carried out user configured various task;
Step 3: after the user disposed the normal acquisition of startup, acquisition station 30 entered into normal drainage pattern, gathered the signal that wave detector 40 enters;
Step 4: after each collection is finished, local frame makes up module 502 and creates local frames and deposit local FIFO buffer 504 in medium to be uploaded, the triggering of data upload sends upload command by master station 10 by fixed intervals (being sampling interval) and finishes, because command execution has been done calibration constantly, so uploading at every turn, each acquisition station 30 constantly all keeps the identical moment, thereby made up a kind of data transmission method based on pipeline system, each acquisition station 30 is sending frame data in the upper level, the frame data that reception is uploaded from next stage by up input driver module 506, and be kept in the FIFO of the subordinate buffer 505, the each sampling of acquisition station all can receive a data upload command, after receiving this order, acquisition station just carries out the transmission work of frame, because each acquisition station command execution simultaneity constantly, thereby guaranteed data upload simultaneity constantly, can satisfy the demand of synchronous transmission between each acquisition station;
Step 5: when the frame data in the local FIFO buffer 504 are sent out when complete, also finish the reception work of subordinate's one frame data in the FIFO of the subordinate buffer 505, line output driver module 507 switches to the FIFO of subordinate buffer 505 on this moment, carries out the forwarding work of subordinate's frame.Simultaneously up input driver module 506 continues to receive frame data of being transmitted by subordinate's acquisition station 30;
Step 6: when cross-station 20 and acquisition station 30 receive master station 10 stop acquisition after, namely return step 2, continue wait command, otherwise, return step 4, continue to transmit data.
To sum up, the utility model has designed a kind of cascade acquisition station high speed data transfer circuit, this transmission circuit directly drives hardware based on the LVDS transmission technology by the FPGA steering logic, the contentedly requirement of high data transmission rate in the 100Mbps-660Mbps scope in the seismic exploration system.The data transmission rate that seismograph uses shown in Fig. 1 is 110Mbps, typical case's sampling rate is 1ksps, each sampled point is 3 bytes, adopt encapsulation format in the following table 1, wherein 8 track datas are encapsulated as a frame, and the length of each frame is 208 bytes, wherein payload data is 192 bytes, useful load is the clear data that ADC collects, and other fields are identification field, status information and check field.
Table 1 data frame format
Encapsulation format in the table 1 in the employing, the clear data byte number that then 8 passages need to be uploaded in the per second are 3000 bytes (1ksps * 3B * 1s).Consider the frame transfer efficiency, namely need this moment the byte number of actual transmissions to be (3000/192) * 208=3250 byte, it is 110M/8=13.75M that per second can support to upload maximum number of byte, and the max number of channels that namely can support is 13.75M * 8/3250=33846 road.Consider that phaselocked loop can lock input clock in the LVDS interface in order to keep in the transmission, between frame and the frame certain interval must be arranged, 20% the time of supposing is used for clock lock, 80% time was used for the transmission of data, the max number of channels of then supporting is 33846 * 80%=27077, can satisfy the at present basic seismographic data transmission demand of all types.
The utility model has also designed a kind of data transmission circuit of pipeline system, this circuit is based on the synchronism of each acquisition station transmission time, each acquisition station transmits at the same time point, each acquisition station is in this DBMS of transmission, buffer memory is from the data of subordinate's acquisition station, whole system is finished the data transmission of pipeline system, has increased data transmission efficiency.Take transfer rate as example as 100Mbps, shown in Fig. 1 in the seismograph every frame length be 208 bytes (seeing Table 1), the clear data byte number is 192 bytes, data transmission method based on LVDS interface pipeline system, need not to add before frame other protocol fields, namely this time frame effective rate of utilization is 92.3% again; Under the Internet Transmission mode of same transfer rate, an ICP/IP protocol shared byte number is 54 bytes (14 byte MAC heads+20 byte IPv4 heads+20 byte TCP heads), namely before every frame, must add the protocol headers of at least 54 bytes, this is to adopt the extra duty that must increase based on ICP/IP protocol Internet Transmission mode, so total frame length is 262 bytes (208+54) after the combination, this moment, the clear data byte number still was 192 bytes, and namely the frame effective rate of utilization is 73.3% under the Internet Transmission mode.Namely under identical frame utilization factor, can be reduced to 80Mbps based on the transfer rate of the transmission mode of LVDS interface pipeline system, the reduction of transfer rate will greatly reduce the requirement to transmission line, also reduce error rate of system, increase system reliability.
The utility model has also designed a kind of synchronous calibration circuit of data transmission, and this circuit is that the pipeline system data transmission is given security, and utilizes this synchronizing circuit, and each acquisition station will carry out data transfer at identical time point.Data transmission synchronization is aligned in the initialization procedure and finishes, and only need carry out once.
The preferred embodiment that the above is only created for the utility model; do not create in order to limit the utility model; all any modifications of within spirit that the utility model is created and principle, doing, be equal to and replace and improvement etc., all should be included within the protection domain that the utility model creates.
Claims (5)
1. a cascade acquisition station high performance pipeline number that is used for seismic prospecting passes system, comprise master station, a plurality of cross-stations, a plurality of acquisition stations, and wave detector, described master station is connected to cross-station, the mutual cascade of a plurality of cross-stations, the left and right sides of each cross-station is a plurality of acquisition stations of cascade respectively, and connect one or more wave detectors on each acquisition station, between the cross-station and the data transmission between cross-station and the master station finished by large line, branch line finish between the acquisition station and acquisition station and cross-station between data transmission, it is characterized in that: described master station uses two LVDS interfaces, be connected respectively to cross-station, each cross-station uses four LVDS interfaces, is respectively upstream Interface, downstream interface, left side interface and right side interface, wherein upstream Interface is the direction to master station, downstream interface is connected to the cross-station of next stage, left side interface and right side interface respectively connect acquisition station, and each acquisition station uses respectively two LVDS interfaces, is respectively left side interface and right side interface.
2. the cascade acquisition station high performance pipeline number for seismic prospecting as claimed in claim 1 passes system, it is characterized in that: be provided with the high speed data transfer circuit in described each master station, cross-station, the acquisition station, this high speed data transfer circuit comprises two paths: transmitting uplink data path and down order transmission channel;
Transmitting uplink data path and down order transmission channel in described cross-station and the acquisition station include FPGA, self-adaptation cable balanced device, deserializer, parallel-to-serial converter, the serial digital cable driver, described self-adaptation cable balanced device, deserializer, FPGA, parallel-to-serial converter, the serial digital cable driver sequentially connects, wherein FPGA finishes deserializer, the driving of parallel-to-serial converter, self-adaptation cable balanced device receives the signal input from the LVDS interface, finish the filtering of input signal, its output signal is connected to string and the conversion of deserializer settling signal, finally is input to the reception that FPGA finishes data; At drive end, FPGA sends to parallel-to-serial converter with parallel data, at first finishes the parallel-serial conversion of data, and then the parallel-to-serial converter output signal finally is transformed into the LVDS signal from another LVDS interface output to the serial digital cable driver;
The data transmission circuit that arranges in the described master station comprises the LVDS input circuit, FPGA and LVDS output circuit, described LVDS input circuit comprises self-adaptation cable balanced device and deserializer, the LVDS output circuit comprises parallel-to-serial converter and serial digital cable driver, the input driver module is set in the FPGA, output driver module and storer, described input driver module is connected to the deserializer of LVDS input circuit, the output driver module is connected to the parallel-to-serial converter of LVDS output circuit, and input driver module and output driver module all are connected to described storer.
3. the cascade acquisition station high performance pipeline number for seismic prospecting as claimed in claim 2 passes system, it is characterized in that: be provided with the circuit of realizing the pipeline system data transmission method among the FPGA of described each cross-station and acquisition station;
The circuit of the realization pipeline system data transmission method in the FPGA of described acquisition station comprises such as lower module: 1) local frame makes up module, is connected to acquisition station at the corresponding levels, and this module is finished the frame building work of each image data; 2) local FIFO buffer and the FIFO of subordinate buffer, these FIFO buffers are finished the buffer memory of data, local FIFO buffer input end is connected to local frame and makes up module, the input end of the FIFO of subordinate buffer is connected to the input driver module, the output terminal of local FIFO buffer and the FIFO of subordinate buffer all is connected to the output driver module, data in output driver module read local FIFO buffer and the FIFO of the subordinate buffer send, same, the input driver module is deposited into the FIFO of the subordinate buffer from the data that subordinate receives; 3) input driver module and output driver module are finished the driving of external hardware circuit, namely are connected respectively to described deserializer and parallel-to-serial converter, are used for respectively driving deserializer and parallel-to-serial converter; 4) steering logic, steering logic are connected respectively to input driver module and output driver module, provide the sequential of input driver module and output driver module read local FIFO buffer and the FIFO of subordinate buffer;
The circuit of the realization pipeline system data transmission method in the FPGA of described cross-station comprises such as lower module: the 1) FIFO of subordinate buffer, these FIFO buffers are finished the buffer memory of data, the input end of the FIFO of subordinate buffer is connected to the input driver module, output terminal all is connected to the output driver module, the data that the output driver module reads in the FIFO of the subordinate buffer send, same, the input driver module is deposited into the FIFO of the subordinate buffer from the data that subordinate receives; 2) input driver module and output driver module are finished the driving of external hardware circuit, namely are connected respectively to described deserializer and parallel-to-serial converter, are used for respectively driving deserializer and parallel-to-serial converter; 3) steering logic, steering logic are connected respectively to input driver module and output driver module, provide the sequential that input driver module and output driver module read the FIFO of subordinate buffer.
4. the cascade acquisition station high performance pipeline number for seismic prospecting as claimed in claim 3 passes system, it is characterized in that: the calibration circuit that is provided with data transmission among the FPGA in described acquisition station and the cross-station, the delay time register that described calibration circuit comprises counting module and is connected to counting module, described counting module are connected respectively to the FPGA interior input driver module of down order transmission channel and the interior output of the FPGA driver module of transmitting uplink data passage.
5. pass system such as each described cascade acquisition station high performance pipeline number for seismic prospecting of claim 1 to 4, it is characterized in that: described large line and branch line all adopt unshielded twisted pair.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104237935A (en) * | 2014-09-28 | 2014-12-24 | 北京优科海青技术发展有限公司 | Common data recording system architecture for geophysical exploration and constructing method of architecture |
| CN104656129A (en) * | 2015-02-06 | 2015-05-27 | 中国地质大学（北京） | Data transmission method applied to distributed earthquake collection stations |
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| CN107765296A (en) * | 2017-12-07 | 2018-03-06 | 合肥国为电子有限公司 | A kind of wired seismic detector arrangement architecture for being easy to investigate automatically and its investigation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104237935A (en) * | 2014-09-28 | 2014-12-24 | 北京优科海青技术发展有限公司 | Common data recording system architecture for geophysical exploration and constructing method of architecture |
| CN104237935B (en) * | 2014-09-28 | 2017-04-19 | 北京优科海青技术发展有限公司 | Common data recording system architecture for geophysical exploration and constructing method of architecture |
| CN104656129A (en) * | 2015-02-06 | 2015-05-27 | 中国地质大学（北京） | Data transmission method applied to distributed earthquake collection stations |
| CN105700426A (en) * | 2016-03-29 | 2016-06-22 | 吉林大学 | Data exchange device in hybrid remote measurement seismic exploration system and data control method |
| CN106443767A (en) * | 2016-10-18 | 2017-02-22 | 连云港杰瑞自动化有限公司 | Petroleum seismic acquisition high-speed transmission system |
| CN107765296A (en) * | 2017-12-07 | 2018-03-06 | 合肥国为电子有限公司 | A kind of wired seismic detector arrangement architecture for being easy to investigate automatically and its investigation method |
| CN107765296B (en) * | 2017-12-07 | 2024-03-15 | 合肥国为电子有限公司 | Wired seismograph arrangement structure convenient for automatic investigation and investigation method thereof |
| CN109286423A (en) * | 2018-09-28 | 2019-01-29 | 中南大学 | A kind of either simplex two-way carrier communication device based on mountain area exploration receiver |
| CN109286423B (en) * | 2018-09-28 | 2022-02-08 | 中南大学 | Simplex bidirectional carrier communication device based on mountain area survey receiver |
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