CN102569177A - Method for realizing high-performance copper interconnection by using upper mask - Google Patents
Method for realizing high-performance copper interconnection by using upper mask Download PDFInfo
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- CN102569177A CN102569177A CN2012100149642A CN201210014964A CN102569177A CN 102569177 A CN102569177 A CN 102569177A CN 2012100149642 A CN2012100149642 A CN 2012100149642A CN 201210014964 A CN201210014964 A CN 201210014964A CN 102569177 A CN102569177 A CN 102569177A
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Abstract
The invention discloses a method for realizing high-performance copper interconnection by using an upper mask. The upper mask comprises a semiconductor substrate with a metal interconnecting layer, wherein a composite structure is formed on the metal interconnecting layer of the semiconductor substrate; the composite structure consists of an etching stop layer, a medium layer, an upper coating layer, an etching adjusting layer and a mask layer from bottom to top; and the etching adjusting layer is a silicon oxide thin film. The method has the advantages that: according to the technical flow and the method provided by the invention, the depth of a copper interconnecting line ditch is selectively changed by using the added silicon oxide to etch a depth-adjusting layer, so the square resistance of a copper interconnecting line which is in accordance with a condition in a specific area is reduced, and the aim of selectively reducing chip interconnecting resistance is fulfilled. According to the application of the method, the interconnecting resistance can be reduced to the great extent on the premise that the overall copper interconnection depth is not changed, the process difficulty is not increased, and the size of a technical window is not reduced, the signal delay of a chip is reduced, the loss is reduced, and the overall performance of a chip is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, especially a kind of method of utilizing mask to realize the high-performance copper interconnection.
Background technology
In semiconductor integrated circuit industry, the high performance integrated circuit chip needs high performance back segment electricity to connect.Metallic copper is because its low-resistivity characteristic has obtained application more and more widely in advanced IC chip.From the aluminum steel to the copper cash, the change of material has brought the huge reduction of resistivity.Along with the progress of integrated circuit technique, the increase of chip complexity this means that the resistance of the back segment interconnection line in the chip becomes one of bottleneck of performance.How to reduce resistance effectively, become an important subject of back segment interconnection.
From the resistance formula, we can obtain some inspirations:
(in the last figure formula, R represents resistance, and ρ represents the resistivity of material, and L represents conductor length, and W represents the interconnection line width, and H represents the thickness of interconnection line.) along with the dwindling of chip size, the raising of density and the raising of chip complexity, the width of interconnection line constantly reduces, the also inevasible increase of the total length L of interconnection line.The factor of resistance be can reduce and only resistivity and thickness have been left.And switch to copper-connection, thereby reduce the reduction of the resistivity realization overall resistance of interconnection line from the aluminium interconnection.And for same material, its resistivity is certain basically.Unique factor that therefore, can be used to reduce the resistance of high-end copper interconnecting line has just had only the thickness H that improves interconnection line.In order to characterize the influence of thickness to resistance more accurately, (sheet resistance also is sheet resistance, and computing formula does to adopt square resistance in the semiconductor technology
Rs=ρ/H, R=Rs*L/W) characterize.For the difform interconnection line of same process, square resistance can characterize out the influence of thickness to resistance accurately like this, and does not receive the influence of conductor length and width.
In fact, because the restriction of metal filled technology and etching technics, Embedded copper interconnection structure will realize successfully that its basic technology conditional request depth-width ratio can not be excessive, and promptly for the copper interconnecting line of a certain width, its thickness can not be too thick.Because thickness is too thick, mean that the groove structure degree of depth is very big, will be unfavorable for that etching technics controls etched pattern and size; And the also difficult completion complete filling of metal filled technology; Can increase resistance so on the contrary, reduce the reliability of interconnection, bring very adverse influence.Therefore integral thickness that can not unconfined increase interconnection line reduces resistance.
Summary of the invention
To the problems referred to above that existing back segment electricity syndeton exists, the present invention provides a kind of method of utilizing mask to realize the high-performance copper interconnection.
The technological means that technical solution problem of the present invention is adopted is:
A kind of method of utilizing mask to realize the high-performance copper interconnection comprises that one exists the semiconductor-based end of metal interconnecting layer, wherein, comprises following concrete steps:
Step a, on the metal interconnecting layer at the said semiconductor-based end, form a composite construction, said composite construction is etching stop layer, dielectric layer, overlying strata, etching adjustment layer and mask layer from down to up successively, and said etching adjustment layer is a silicon oxide film;
Step b, said composite construction is carried out etching, form the pattern of metal interconnection structure and make etching stopping in said etching adjustment layer in said mask layer;
Step c, in said metal interconnection structure plan, the said etching adjustment layer in the predetermined zone that needs to deepen is removed;
Steps d, photoetching and partial etching are carried out in the predetermined position that forms through hole in said metal interconnect structure pattern, make the through-hole pattern that forms desired depth on the said composite construction;
Step e, said composite construction is carried out etching, to form groove and the through hole that said metal interconnection structure plan sketches the contours;
Step f, in said groove and through hole embedded with metal, make said metal be full of said groove and through hole;
Step g, smooth said composite structure surface.
Mask is realized the method for high-performance copper interconnection in the above-mentioned utilization, and wherein, said etching stop layer is the nitrogen-doped silicon carbide layer.
Mask is realized the method for high-performance copper interconnection in the above-mentioned utilization, and wherein, the relative dielectric constant of said dielectric layer is 2-4.2.
Mask is realized the method for high-performance copper interconnection in the above-mentioned utilization, and wherein, said overlying strata is a silicon oxide layer.
Mask is realized the method for high-performance copper interconnection in the above-mentioned utilization, and wherein, the formation method of said silicon oxide film is a chemical vapor deposition.
Mask is realized the method for high-performance copper interconnection in the above-mentioned utilization, and wherein, said mask layer is the titanium nitride metal level.
Mask is realized the method for high-performance copper interconnection in the above-mentioned utilization; Wherein, The said composite construction of etching ground method is among the said step b: utilize photoetching that said metal interconnection structure plan is transferred to said mask layer, etching is removed the mask layer in the said metal interconnection structure plan.
Mask is realized the method for high-performance copper interconnection in the above-mentioned utilization; Wherein, The method of removing said etching adjustment layer among the said step c is: utilize a predefine light shield; The said etching adjustment layer in the zone that the said reservation of etching need be deepened, the etching mode is the plasma dry etching, said etching stopping is in said overlying strata.
Mask is realized the method for high-performance copper interconnection in the above-mentioned utilization, and wherein, among the said step f, the metal of inlaying is a copper.
Mask is realized the method for high-performance copper interconnection in the above-mentioned utilization, and wherein, the method for smooth said composite structure surface is a cmp in the said step g.
Mask is realized the method for high-performance copper interconnection in the above-mentioned utilization, and wherein, the formation method of said nitrogen-doped silicon carbide layer is a chemical vapor deposition.
Mask is realized the method for high-performance copper interconnection in the above-mentioned utilization, and wherein, the formation method of said dielectric layer is a chemical vapor deposition.
Mask is realized the method for high-performance copper interconnection in the above-mentioned utilization, and wherein, the formation method of said silicon oxide layer is a chemical vapor deposition.
Mask is realized the method for high-performance copper interconnection in the above-mentioned utilization, and wherein, the formation method of said titanium nitride metal level is a PVD.
Mask is realized the method for high-performance copper interconnection in the above-mentioned utilization, wherein, has the barrier layer between groove on said metallic copper and the said composite construction and the through hole.
Mask is realized the method for high-performance copper interconnection in the above-mentioned utilization, and wherein, the method for embedding of said metallic copper is for electroplating.
Mask is realized the method for high-performance copper interconnection in the above-mentioned utilization, and wherein, said barrier layer is tantalum or tantalum nitride.
Mask is realized the method for high-performance copper interconnection in the above-mentioned utilization, and wherein, the formation method of said tantalum or desalination tantalum barrier layer is a PVD.
The invention has the beneficial effects as follows:
Through technological process of the present invention and method; Utilize the silica etching depth adjustment layer that adds; The degree of depth to the copper interconnecting line groove is carried out selectively changing, thereby the copper interconnecting line square resistance of qualified specific region is reduced, thereby realizes that selectivity reduces the purpose of chip interconnect resistance.Through utilization of the present invention, can not increase technology difficulty not changing the global copper interconnect depth, under the prerequisite of reduction process window, farthest do not reduce interconnected resistance, thereby reduce the signal delay of chip, reduce the wastage, improve the chip overall performance.
Description of drawings
Fig. 1 is a kind of flow chart that utilizes mask to realize the method for high-performance copper interconnection of the present invention;
Fig. 2 is the profile status structure chart after a kind of step a that utilizes mask to realize the method for high-performance copper interconnection of the present invention accomplishes;
Fig. 3 is the profile status structure chart after a kind of step b that utilizes mask to realize the method for high-performance copper interconnection of the present invention accomplishes;
Fig. 4 is the profile status structure chart after a kind of step c that utilizes mask to realize the method for high-performance copper interconnection of the present invention accomplishes;
Fig. 5 is the profile status structure chart after a kind of steps d of utilizing mask to realize the method for high-performance copper interconnection of the present invention is accomplished;
Fig. 6 is the profile status structure chart after a kind of step e that utilizes mask to realize the method for high-performance copper interconnection of the present invention accomplishes;
Fig. 7 is the profile status structure chart after a kind of step f that utilizes mask to realize the method for high-performance copper interconnection of the present invention accomplishes;
Fig. 8 is the profile status structure chart after a kind of step g of utilizing mask to realize the method for high-performance copper interconnection of the present invention is accomplished.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the present invention is described further, but not as qualification of the present invention.
As shown in Figure 1, a kind of method of utilizing mask to realize the high-performance copper interconnection of the present invention comprises that one exists the semiconductor-based end 100 of metal interconnecting layer 110, wherein, comprises following concrete steps:
As shown in Figure 2, step a, on the metal interconnecting layer 110 at the semiconductor-based end 100, form a composite construction 200, composite construction 200 is etching stop layer 210, dielectric layer 220, overlying strata 230, etching adjustment layer 240 and mask layer 250 from down to up successively.
Wherein said etching stop layer 210 is the nitrogen-doped silicon carbide layer, and its formation method can be a chemical vapor deposition; Dielectric layer 220 can be a fluorine doped silicon oxide glass; Carbon doped silicon oxide; The porous low dielectric constant material; Also can be traditional dielectric material such as silica in the practical application, relative dielectric constants such as boron phosphor silicon oxide glass be 2-4.2 dielectric material, and its formation method can be a chemical vapor deposition; Overlying strata 230 is a silicon oxide layer, and its formation method can be a chemical vapor deposition; Etching adjustment layer 240 is a silicon oxide film; Its thickness range is several nanometers to hundreds of nanometers; Its thickness is selected to determine jointly that according to the different materials etching selection ratio of the size of the required adjustment degree of depth and adjustment layer film and copper-connection dielectric film its formation method can be a chemical vapor deposition; Mask layer 250 is the titanium nitride metal level, and its formation method can be a physical vapour deposition (PVD).
As shown in Figure 3, step b, composite construction 200 is carried out etching, form the pattern 300 of metal interconnection structures and make etching stopping in mask layer 250 in etching adjustment layer 210; Wherein the method for etching composite construction 200 is: form photoresistance 400 and utilize photoetching that metal interconnection structure plan 300 is transferred to mask layer 250, etching is removed the mask layer 250 in the metal interconnection structure plan 300.
As shown in Figure 4, step c, in metal interconnection structure plan 300, the etching adjustment layer 240 in the zone 310 that reservation is needed deepen is removed; The method of removing etching adjustment layer 240 is: utilize a predefine light shield 410 to cover the zone that need not deepen, and the etching adjustment layer 240 in the zone 310 that the etching reservation need be deepened, the etching mode is the plasma dry etching, etching stopping is in overlying strata 230.
As shown in Figure 5, steps d, photoetching and partial etching are carried out in the predetermined position that forms through hole 340 in metal interconnect structure pattern 300, make the pattern that forms the through hole 330 of desired depth on the composite construction 200; The pattern of through hole 340 is middle through making through hole 340 structures temporarily rest on dielectric layer 220 after the method for partial etching; Help reducing the damage of final through hole 340 structures in the process of removing photoresistance like this, in this step, control the depth scale of groove and through hole in the final form through the degree of depth of regulating partial etching.
As shown in Figure 6, step e, composite construction 200 is carried out etching, to form the groove 330 and through hole 340 that metal interconnection structure plan 300 sketches the contours; After removing photoresistance, substrate 100 surfaces have only kept the mask layer 250 with metal interconnection structure plan 300 characteristics.Utilize stopping of mask layer 250; Composite construction in the substrate 100 200 is carried out the plasma dry etching; Form groove 330, make through hole 340 etch into dielectric layer 220 bottoms simultaneously, and open etching barrier layer 210 so that the connection of the metal interconnecting layer 110 in the former substrate 100.The effect of adjusting layer 240 owing to etching makes the predetermined groove 330 of intensification regional 310 that needs darker than other regional grooves 330.
As shown in Figure 7, step f, in groove 330 and through hole 340 embedded with metal 350, make metal 350 be full of groove 340 and through hole 350; Wherein, the metal of inlaying 350 is copper, has barrier layer (not marking in the drawings) between groove 330 on metal 350 and the composite construction 200 and the through hole 340, and the barrier layer is tantalum or tantalum nitride, and its formation method is a PVD.On the barrier layer, form the inculating crystal layer of a bronze medal; Adopt electric plating method on the inculating crystal layer of copper, to continue to fill and make copper be full of groove 330 and through hole 340, wherein this copper filling step must have a certain amount of redundancy to remedy the loss of the metallic copper that possibly cause in the follow-up surfacing step.
As shown in Figure 8, copper redundancy and mask layer, etching adjustment layer and the overlying strata of inlaying generating step are removed in step g, smooth composite construction 200 surfaces, and the method on smooth composite construction 200 surfaces is a cmp.
As can be seen from Figure 8 the groove copper interconnecting line of deepening zone 310 has bigger thickness, and copper that promptly should the zone has bigger conductive section, therefore has lower square resistance Rs.Because, can guaranteeing the copper interconnecting line of deepening less than the degree of depth of copper in the through hole 340, this regional copper degree of depth can realize good filling smoothly again, unrestricted on the technological ability.
In fact, the present invention also can be used for individual layer embedded (single Damascus) technology.As long as the fill process of copper can guarantee that copper can be filled in the structure smoothly, and the structure of below, selected groove intensification zone does not affect adversely.
The above is merely preferred embodiment of the present invention; Be not so limit claim of the present invention; So the equivalent structure that all utilizations specification of the present invention and diagramatic content have been done changes, utilizes the material of mentioning same-actions such as tool among known and the present invention to replace; Utilize the means and methods of the same-actions of mentioning among known and the present invention such as means and methods tool to replace, resulting execution mode or result of implementation all are included in protection scope of the present invention.
Claims (18)
1. mask is realized the method for high-performance copper interconnection comprising that one exists the semiconductor-based end of metal interconnecting layer in the utilization, it is characterized in that, comprises following concrete steps:
Step a, on the metal interconnecting layer at the said semiconductor-based end, form a composite construction, said composite construction is etching stop layer, dielectric layer, overlying strata, etching adjustment layer and mask layer from down to up successively, and said etching adjustment layer is a silicon oxide film;
Step b, said composite construction is carried out etching, form the pattern of metal interconnection structure and make etching stopping in said etching adjustment layer in said mask layer;
Step c, in said metal interconnection structure plan, the said etching adjustment layer in the predetermined zone that needs to deepen is removed;
Steps d, photoetching and partial etching are carried out in the predetermined position that forms through hole in said metal interconnect structure pattern, make the through-hole pattern that forms desired depth on the said composite construction;
Step e, said composite construction is carried out etching, to form groove and the through hole that said metal interconnection structure plan sketches the contours;
Step f, in said groove and through hole embedded with metal, make said metal be full of said groove and through hole;
Step g, smooth said composite structure surface.
2. utilize according to claim 1 and go up the method that mask is realized the high-performance copper interconnection, it is characterized in that said etching stop layer is the nitrogen-doped silicon carbide layer.
3. utilize according to claim 1 and go up the method that mask is realized the high-performance copper interconnection, it is characterized in that the relative dielectric constant of said dielectric layer is 2-4.2.
4. utilize according to claim 1 and go up the method that mask is realized the high-performance copper interconnection, it is characterized in that said overlying strata is a silicon oxide layer.
5. utilize according to claim 1 and go up the method that mask is realized the high-performance copper interconnection, it is characterized in that the formation method of said silicon oxide film is a chemical vapor deposition.
6. utilize according to claim 1 and go up the method that mask is realized the high-performance copper interconnection, it is characterized in that said mask layer is the titanium nitride metal level.
7. utilize the method that mask is realized the high-performance copper interconnection that goes up according to claim 1; It is characterized in that; The said composite construction of etching ground method is among the said step b: utilize photoetching that said metal interconnection structure plan is transferred to said mask layer, etching is removed the mask layer in the said metal interconnection structure plan.
8. utilize the method that mask is realized the high-performance copper interconnection that goes up according to claim 1; It is characterized in that; The method of removing said etching adjustment layer among the said step c is: utilize a predefine light shield; The said etching adjustment layer in the zone that the said reservation of etching need be deepened, the etching mode is the plasma dry etching, said etching stopping is in said overlying strata.
9. utilize according to claim 1 and go up the method that mask is realized the high-performance copper interconnection, it is characterized in that among the said step f, the metal of inlaying is a copper.
10. utilize according to claim 1 and go up the method that mask is realized the high-performance copper interconnection, it is characterized in that the method for smooth said composite structure surface is a cmp in the said step g.
11. realize the method that high-performance copper interconnects like mask in the said utilization of claim 2, it is characterized in that the formation method of said nitrogen-doped silicon carbide layer is a chemical vapor deposition.
12. realize the method that high-performance copper interconnects like mask in the said utilization of claim 3, it is characterized in that the formation method of said dielectric layer is a chemical vapor deposition.
13. realize the method that high-performance copper interconnects like mask in the said utilization of claim 4, it is characterized in that the formation method of said silicon oxide layer is a chemical vapor deposition.
14. realize the method that high-performance copper interconnects like mask in the said utilization of claim 6, it is characterized in that the formation method of said titanium nitride metal level is a PVD.
15. realize the method that high-performance copper interconnects like mask in the said utilization of claim 9, it is characterized in that, there is the barrier layer between groove on said metallic copper and the said composite construction and the through hole.
16. realize the method that high-performance copper interconnects, it is characterized in that the method for embedding of said metallic copper is for electroplating like mask in the said utilization of claim 9.
17. realize the method that high-performance copper interconnects like mask in the said utilization of claim 15, it is characterized in that said barrier layer is tantalum or tantalum nitride.
18. realize the method that high-performance copper interconnects, it is characterized in that the formation method of said tantalum or desalination tantalum barrier layer is a PVD like mask in the said utilization of claim 17.
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| US20090121353A1 (en) * | 2007-11-13 | 2009-05-14 | Ramappa Deepak A | Dual damascene beol integration without dummy fill structures to reduce parasitic capacitance |
| US20100178771A1 (en) * | 2009-01-09 | 2010-07-15 | Samsung Electronics Co., Ltd. | Methods of Forming Dual-Damascene Metal Interconnect Structures Using Multi-Layer Hard Masks |
| US20110101538A1 (en) * | 2009-11-02 | 2011-05-05 | International Business Machines Corporation | Creation of vias and trenches with different depths |
| US20110175233A1 (en) * | 2010-01-19 | 2011-07-21 | Akira Ueki | Semiconductor device and method for fabricating the same |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1412845A (en) * | 2001-10-19 | 2003-04-23 | 日本电气株式会社 | Semiconductor device and its mfg. method |
| US20090121353A1 (en) * | 2007-11-13 | 2009-05-14 | Ramappa Deepak A | Dual damascene beol integration without dummy fill structures to reduce parasitic capacitance |
| US20100178771A1 (en) * | 2009-01-09 | 2010-07-15 | Samsung Electronics Co., Ltd. | Methods of Forming Dual-Damascene Metal Interconnect Structures Using Multi-Layer Hard Masks |
| US20110101538A1 (en) * | 2009-11-02 | 2011-05-05 | International Business Machines Corporation | Creation of vias and trenches with different depths |
| US20110175233A1 (en) * | 2010-01-19 | 2011-07-21 | Akira Ueki | Semiconductor device and method for fabricating the same |
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Application publication date: 20120711 |