CN102446849B - Method for forming single Damascus of thick metal - Google Patents
Method for forming single Damascus of thick metal Download PDFInfo
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- CN102446849B CN102446849B CN201110388371.8A CN201110388371A CN102446849B CN 102446849 B CN102446849 B CN 102446849B CN 201110388371 A CN201110388371 A CN 201110388371A CN 102446849 B CN102446849 B CN 102446849B
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Abstract
The invention provides a method for forming a single Damascus of thick metal. An additional metal interconnection for reducing copper interconnection sheet resistance is added in a through hole layer through the single Damascus process; a through hole structure and an addition abundant metal interconnection are merged in the same optical mask so as to reduce process complexity; a final structure can be finished by only twice photoetching processes; and the through hole structure and the addition abundant metal interconnection are combined with copper metal wires at the next layer of the single Damascus so as to finally obtain copper interconnection wires with lower sheet resistance. Through the method provided by the invention, the depth of a copper interconnection wire trench can be selectively changed so as to reduce the sheet resistance of the copper interconnection wires which meet conditions and are in a specified region and selectively reduce the chip interconnection sheet resistance. Under the condition of not changing the whole copper interconnection depth, not increasing process difficulty, and not reducing a process window, the interconnection sheet resistance is reduced to a maximum extent so as to reduce a signal delay of the chip, reduce loss and improve the integral performance of the chip.
Description
Technical field
The present invention relates to relate to field of semiconductor manufacture, relate in particular to a kind of single damascene process that forms thick metal.
Background technology
In semiconductor integrated circuit industry, high performance integrated circuit chip needs high performance back segment electricity interlinkage.Because metallic copper has low-resistivity characteristic, and in advanced integrated circuit (IC) chip, obtained application more and more widely.From aluminum steel to copper cash, the change of material has brought the huge reduction of resistivity.Along with the progress of integrated circuit technique, the increase of chip complexity, complexity and the length of back segment interconnection are increasing, this means that the resistance of the back segment interconnection line in chip becomes one of bottleneck of performance.Effectively reduce resistance and become an important subject in integrated circuit.
Resistance calculations formula is
wherein R is resistance, the resistivity that ρ is material, and L is conductor length, W is interconnection line width, the thickness that H is interconnection line.Along with dwindling of chip size, the raising of density and the raising of chip complexity, the width of interconnection line constantly reduces, and the total length L of interconnection line is inevasible increase also.The factor that thus, can reduce resistance is only left resistivity and thickness.And be switched to metallic copper interconnection from using metallic aluminium to interconnect, thereby from reducing the resistivity of interconnection line, realize the reduction of overall resistance.And for same material, its resistivity is fixed substantially.Therefore, can just only be improved the thickness H of interconnection line for reducing unique factor of the resistance of high-end copper interconnecting line.In order to characterize more accurately the impact of thickness on resistance, (Sheet Resistance, is also sheet resistance, and its computing formula is in semiconductor technology, to adopt square resistance
) characterize, like this for difform interconnection line, square resistance can symbolize the impact of thickness on resistance accurately, and is not subject to the impact of conductor length and width.
In fact, due to the restriction of metal filled technique and etching technics, Embedded copper interconnection structure will successfully be realized, and its basic technology conditional request depth-width ratio can not be excessive, and, for the copper interconnecting line of a certain width, its thickness can not be too thick.Because thickness is too thick, mean that the groove structure degree of depth is very large, will be unfavorable for that etching technics controls etched pattern and size, and metal filled technique also more difficult complete completely fill, can increase square resistance so on the contrary, reduce the reliability of interconnection, bring very adverse influence.Therefore integral thickness that can not unconfined increase interconnection line reduces square resistance.
Summary of the invention
The present invention, according to problems of the prior art, provides a kind of single damascene process that forms thick metal to realize elective reduction square resistance of copper interconnection.By adopting at single Damascus copper wiring technique in via layer, utilize a photoetching and etching to form respectively the part-structure that needs through-hole structure and reduce the wire of square resistance.Adopt above it subsequently single Damascus technics to carry out again the making of normal metal valley.Owing to only having and have structure in channeled layer in normal region, and fall the two-part structure that low-resistance interconnection line comprises via layer and metal valley layer, be equivalent to realize the copper interconnecting line thickness that zones of different is different, reduced the square resistance of defined range copper interconnecting line.
In order to realize above-mentioned object, a kind of single damascene process that forms thick metal is provided, comprise following sequential steps:
Step 1: successively deposit one etching barrier layer, a SiOCH low k dielectric and a SiO in lower metal layer of interconnect structure
2dielectric protection layer, at a SiO
2spin coating the first photoresist layer in dielectric protection layer; on the first photoresist layer, photoetching forms through hole and the figure that can thicken metallic channel; through hole and the figure that can thicken metallic channel are carried out to etching; till being etched to and exposing etching barrier layer in through hole and metallic channel; remove the first photoresist layer, described through hole is arranged in the interconnect architecture top of the mutual structure sheaf of lower metal.
Step 2: at a SiO
2the bottom of dielectric protection layer surface, through hole and metallic channel and sidepiece be deposit the first metal barrier and the first copper seed layer successively, grinds and remove a SiO
2dielectric protection layer and cover the first metal barrier and the first copper seed layer thereon and expose a SiOCH low k dielectric surface, described the first metal barrier and interconnect architecture contact.
Step 3: at successively deposit of SiOCH low k dielectric surface one etching barrier layer, the 2nd SiOCH low k dielectric and the 2nd SiO
2dielectric protection layer, at the 2nd SiO
2spin coating the second photoresist layer in dielectric protection layer; on the second photoresist layer, be photo-etched into the figure of whole plain conductors; whole plain conductor figures are carried out to etching; be etched to expose a SiOCH low k dielectric till and form whole metallic channels; in metallic channel, expose the first metal barrier and the first copper seed layer, remove the second photoresist layer.
Step 4: at the 2nd SiO
2the bottom of dielectric protection layer surface and all metallic channel and sidewall be deposit the second metal barrier and the second copper seed layer successively, and described the second metal barrier contacts with the first metal barrier, the first copper seed layer.
Step 5: grind and remove the 2nd SiO
2dielectric protection layer and covering the second metal barrier and the second copper seed layer thereon.
In above-mentioned provider's method, wherein said metal barrier is TaN/Ta material.
In above-mentioned provider's method, wherein said photoresist layer is comprised of photoresist material.
In above-mentioned provider's method, the scope of the relative dielectric constant of wherein said SiOCH low k dielectric is 2～4.2.The SiOCH low k dielectric material that can select is one or more in fluorine doped silicon oxide glass, carbon doped silicon oxide, porous low dielectric constant material, silica, boron phosphor silicon oxide glass.
In above-mentioned provider's method, wherein said etching barrier layer is SiCN.
In above-mentioned provider's method, wherein said grinding adopts chemical mechanical milling method.
In above-mentioned provider's method, wherein said etching using plasma dry etching.
In above-mentioned provider's method, wherein said etching barrier layer, SiOCH low k dielectric and SiO
2dielectric protection layer adopts chemical vapor deposition growth.
In above-mentioned provider's method, wherein said metal barrier and copper seed layer adopt physical vapor deposition growth.
The present invention adopts single Damascus technics, in via layer, increase the additional metal interconnection for reducing square resistance of copper interconnection, through-hole structure and extra excess metal interconnection are incorporated in same light shield, can reduce process complexity, only need Twi-lithography etching can complete final structure.And combine with the copper metal line in later layer list Damascus, finally obtain the copper interconnecting line of lower one piece resistance.By method provided by the invention, can carry out selectively changing to the degree of depth of copper interconnecting line groove, thereby the copper interconnecting line square resistance of qualified specific region is reduced, thereby realize the object of elective reduction chip interconnects square resistance.Not changing global copper interconnect depth, do not increase technology difficulty, under the prerequisite of non-reduction process window, farthest reduce interconnected square resistance, thereby reduce the signal delay of chip, reduce the wastage, improve chip overall performance.
Accompanying drawing explanation
Fig. 1 completes deposit the one SiO in the present invention
2structural representation after dielectric protection layer.
Fig. 2 forms the structural representation after pattern on the first photoresist layer in the present invention.
Fig. 3 forms through hole and can thicken the structural representation after metallic channel in the present invention.
Fig. 4 is the structural representation after complete the first metal barrier of deposit and the first copper seed layer in the present invention.
Fig. 5 is complete the 2nd SiO of deposit in the present invention
2structural representation after dielectric protection layer.
Fig. 6 is the structural representation forming in the present invention after the second photoresist layer pattern.
Fig. 7 is the structural representation forming in the present invention after whole metallic channels.
Fig. 8 is the structural representation after complete the second metal barrier of deposit and the second copper seed layer in the present invention.
Fig. 9 is the formed copper interconnection structure of supplying method in the present invention.
Embodiment
The invention provides a kind of single damascene process that forms thick metal.Utilize single Damascus technics in via layer, to add the latter half of the copper-connection that need to reduce square resistance, this layer needs Twi-lithography etching technics.Carry out subsequently metal filled and cmp, the first of the copper-connection of the square resistance that is reduced.Then utilize single Damascus technics to build metal valley, in this layer, the ditch slot thickness of all plain conductors is the same.Due to levels aligned relationship, have part metals wire bottom also to have the copper interconnecting line pre-setting in ground floor, so this part copper interconnection line compares with common interconnection line, being equivalent to has thicker metal thickness, or have the existence in parallel of two interconnection lines, therefore obtain lower square resistance.
In order to obtain high-performance, just must reduce metal interconnected resistance, but along with the progress of integrated level and technology, the size of interconnection line is more and more less, so sectional area of wire is more and more less, resistance is increasing.And due to the restriction of the growth barrier layer of copper and the physics vapor phase deposition technique of inculating crystal layer, for the groove of certain width, there is the restriction of depth capacity.Therefore, for whole chip, can not adopt the unrestricted method that strengthens interconnected metal thickness to realize the reduction of square resistance.Yet, in circuit layout design, the interconnection line of some specific part, there is not metal throuth hole in its underpart.The present invention by optionally for these specific interconnection lines, thickeies its thickness, makes its thickness be greater than the common through-hole interconnection line that has, and therefore can reduce square resistance with respect to common metal interconnection line.Owing to adopting single Damascus technics in the present invention, the depth of cracking closure of single Damascus technics will be much smaller than double damask structure, at metal filled technical bottleneck before also not existing, can easily utilize existing physical vapour deposition (PVD) and electric plating method to carry out the filling of copper-connection.
By the following examples single damascene process of the thick metal of formation provided by the invention is described in detail, to the content of the invention is better described, but the content of embodiment is not restricted to the protection range of innovation and creation.
It is effective object that the present embodiment is selected double-deck embedded metal copper interconnection structure, and its lower floor exists copper interconnection structure, is convenient to show the annexation between interconnection layer.
First, on the copper interconnection structure that is lower floor in underlying structure as shown in Figure 1, successively adopt chemical gas-phase method deposit one SiCN etching barrier layer 11, a SiOCH low k dielectric 21 and a SiO
2dielectric protection layer 31.The scope of the relative dielectric constant of SiOCH low k dielectric is between 2～4.2, and its optional material is one or more in fluorine doped silicon oxide glass, carbon doped silicon oxide, porous low dielectric constant material, silica, boron phosphor silicon oxide glass.The thickness of film requires to be controlled at several nanometers between hundreds of nanometer according to actual process.As shown in Figure 2, at a SiO
2spin coating the first photoresist layer 41 in dielectric protection layer 31, 42, 43, 44, 45, at the first photoresist layer 41, 42, 43, 44, on 45, photoetching forms through hole and the figure that can thicken metallic channel, through hole and the figure that can thicken metallic channel are carried out to etching, be etched to through hole 101, 103 and in can thicken metallic channel 102, 104 expose SiCN etching barrier layer 11 till, remove this photoresist layer 41, 42, 43, 44, 45, for next step photoetching is prepared, formed via hole image is arranged in the interconnect architecture top of the mutual structure sheaf of lower metal, its structure as shown in Figure 3.
Secondly, the SiCN etching barrier layer 11 of via bottoms is carried out to etching, makes via bottoms expose interconnect architecture, be beneficial to follow-up when metal filled through hole contact with the electricity of lower interconnection.
Then, as shown in Figure 4, profit adopts physical vapor method at a SiO
2dielectric protection layer 31 surfaces, through hole 101,103 and bottom and sidepiece priority deposit the first metal barrier (TaN/Ta) 61 and the first copper seed layer 71 that can thicken metallic channel 102,104.Utilize and electroplate the filling of carrying out metallic copper, finally adopt cmp to remove unnecessary copper, only retain desired structure.A SiO is removed in grinding
2dielectric protection layer 31 and cover the first metal barrier (TaN/Ta) 61 and the first copper seed layer 71 thereon and expose SiOCH low k dielectric 21 surfaces, contacts the first metal barrier (TaN/Ta) 61 and interconnect architecture.Process of lapping has certain advanced low-k materials loss, can guarantee that like this metallic copper, barrier layer, the silica protective layer on its top is all removed completely.Thus, comprising elective reduction square resistance structure just completes in the via layer of interior single Damascus technics.
Afterwards, as illustrated in Figures 5 and 6, on SiOCH low k dielectric 21 surfaces, adopt chemical gas-phase method deposition growing one SiCN etching barrier layer 12, the 2nd SiOCH low k dielectric 22 and the 2nd SiO
2dielectric protection layer 32, carries out the film growth of single Damascus metal connecting line layer.At the 2nd SiO
2spin coating the second photoresist layer 46,47,48,49 in dielectric protection layer 32; on the second photoresist layer 46,47,48,49, be photo-etched into the figure of whole metallic channels; whole metallic channel figures are carried out to plasma dry etching; till being etched to and exposing a SiOCH low k dielectric 21; and form whole metallic channels; in metallic channel, expose the first metal barrier (TaN/Ta) 61 and the first copper seed layer 71; remove the second photoresist layer 46,47,48,49, the structure of formation as shown in Figure 7.
Finally, as shown in Figure 8, at the 2nd SiO
2the bottom of dielectric protection layer surface 32 and metallic channel 111,112,113 and sidewall utilize physical vapor method to deposit successively grow the second metal barrier (TaN/Ta) 62 and the second copper seed layer 72, and the second metal barrier (TaN/Ta) 62 is contacted with the first metal barrier (TaN/Ta) 61, the first copper seed layer 71.Formed structure is filled in electro-coppering, and reaches certain redundancy copper.Adopt chemical mechanical milling method to remove the 2nd SiO
2dielectric protection layer 32 and covering the second metal barrier 62 and the second copper seed layer 72 thereon, only retain needed copper interconnection structure, and formed copper interconnection structure as shown in Figure 9.
Through above-mentioned steps, just obtained the double-deck copper interconnection structure that partly reduces square resistance of copper interconnection.In Fig. 9, copper interconnecting line a-quadrant is normal resistance region, and copper interconnecting line B region is for reducing the region of square resistance.H1 is the thickness of normal copper interconnecting line, and H is the thickness of the copper interconnecting line of elective reduction square resistance, and H2 is the gross thickness of whole two-layer single Damascus technics copper cash and through hole.From scheming, can find out H1 < h < H2.Due to H > H1, make the copper interconnecting line of selective area just have larger conductive section, therefore there is lower square resistance.And H < H2, it is unrestricted that the copper interconnecting line that can guarantee thickening can be realized on good filling and technological ability smoothly.
Above specific embodiments of the invention be have been described in detail, but it is just as example, the present invention is not restricted to specific embodiment described above.To those skilled in the art, any equivalent modifications that the present invention is carried out and alternative also all among category of the present invention.Therefore, equalization conversion and the modification done without departing from the spirit and scope of the invention, all should contain within the scope of the invention.
Claims (8)
1. form a single damascene process for thick metal, it is characterized in that, comprise following sequential steps:
Step 1: successively deposit one etching barrier layer, a SiOCH low k dielectric and a SiO in lower metal layer of interconnect structure
2dielectric protection layer, at a SiO
2spin coating the first photoresist layer in dielectric protection layer, on the first photoresist layer, photoetching forms through hole and the figure that can thicken metallic channel, through hole and the figure that can thicken metallic channel are carried out to etching, till being etched to and exposing etching barrier layer in through hole and metallic channel, remove the first photoresist layer, described through hole is arranged in the interconnection structure top of lower metal layer of interconnect structure; The etching barrier layer of via bottoms is carried out to etching, makes via bottoms expose interconnection structure, be beneficial to follow-up when metal filled through hole contact with the electricity of lower interconnection;
Step 2: at a SiO
2the bottom of dielectric protection layer surface, through hole and metallic channel and sidepiece be deposit the first metal barrier and the first copper seed layer successively, grinds and remove a SiO
2dielectric protection layer and cover the first metal barrier and the first copper seed layer thereon and expose a SiOCH low k dielectric surface, described the first metal barrier and interconnection structure contact;
Step 3: at successively deposit of SiOCH low k dielectric surface one etching barrier layer, the 2nd SiOCH low k dielectric and the 2nd SiO
2dielectric protection layer, at the 2nd SiO
2spin coating the second photoresist layer in dielectric protection layer, on the second photoresist layer, be photo-etched into the figure of whole plain conductors, whole plain conductor figures are carried out to etching, be etched to expose a SiOCH low k dielectric till and form whole metallic channels, in metallic channel, expose the first metal barrier and the first copper seed layer, remove the second photoresist layer;
Step 4: at the 2nd SiO
2the bottom of dielectric protection layer surface and all metallic channel and sidewall be deposit the second metal barrier and the second copper seed layer successively, and described the second metal barrier contacts with the first metal barrier, the first copper seed layer;
Step 5: grind and remove the 2nd SiO
2dielectric protection layer and covering the second metal barrier and the second copper seed layer thereon;
Described etching using plasma dry etching;
The relative dielectric constant scope of described SiOCH low k dielectric is between 2～4.2.
2. method according to claim 1, is characterized in that, described metal barrier is TaN/Ta material.
3. method according to claim 1, is characterized in that, described photoresist layer is comprised of photoresist material.
4. method according to claim 1, is characterized in that, described SiOCH low k dielectric material is one or more in fluorine doped silicon oxide glass, carbon doped silicon oxide, porous low dielectric constant material, boron phosphor silicon oxide glass.
5. method according to claim 1, is characterized in that, described etching barrier layer is SiCN.
6. method according to claim 1, is characterized in that, described grinding adopts chemical mechanical milling method.
7. method according to claim 1, is characterized in that, described etching barrier layer, SiOCH low k dielectric and SiO
2dielectric protection layer adopts chemical vapor deposition growth.
8. method according to claim 1, is characterized in that, described metal barrier and copper seed layer adopt physical vapor deposition growth.
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