CN102437108A - Manufacturing method of copper interconnection structure capable of reducing block resistance - Google Patents
Manufacturing method of copper interconnection structure capable of reducing block resistance Download PDFInfo
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- CN102437108A CN102437108A CN2011103889451A CN201110388945A CN102437108A CN 102437108 A CN102437108 A CN 102437108A CN 2011103889451 A CN2011103889451 A CN 2011103889451A CN 201110388945 A CN201110388945 A CN 201110388945A CN 102437108 A CN102437108 A CN 102437108A
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Abstract
The invention discloses a manufacturing method of a copper interconnection structure capable of reducing a block resistance. The method comprises the following steps that: a semiconductor substrate is provided; an etching barrier layer, a dielectric layer, a dielectric protective layer, and a metal hard mask layer are successively formed on the semiconductor substrate; photoetching and etching are utilized to form a plurality of groove graphs with a first depth in the dielectric protective layer; the dielectric protective layer is continuously etched in a portion of the groove graphs with a first depth, so that a groove graph with a second depth is formed; a through hole graph that is communicated with the groove graphs with a first depth as well as penetrates the dielectric protective layer and a portion of the dielectric layer is formed by photoetching and etching; integrated etching is simultaneously carried out on the groove graphs with a first depth, the groove graphs with a second depth, and the through hole graph so as to form a first depth groove, a second depth groove and a through hole; a deposited metal diffusion barrier layer and a metal seed layer are formed by sputtering in the first depth groove, the second depth groove and the through hole as well as a plating technology is employed to carry out interconnection metal filling; and chemical mechanical polishing is carried out to remove redundant materials on the dielectric layer so as to form copper interconnection.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of manufacturing approach that reduces the copper interconnection structure of square resistance.
Background technology
In semiconductor integrated circuit industry, the high performance integrated circuit chip needs high performance back segment electricity interlinkage.Metallic copper is because its low-resistivity characteristic has obtained application more and more widely in IC chip.But, along with the progress of integrated circuit technique, the increase of chip complexity, the complexity and the length of back segment interconnection are increasing, this means that the resistance of the back segment interconnection line in the chip becomes one of bottleneck of performance.How to reduce resistance effectively, become an important subject in the integrated circuit.
From the resistance calculations formula, we can obtain some inspirations:
In the formula, R represents resistance, and ρ represents the resistivity of material, and L represents conductor length, and W represents the interconnection line width, and H represents the thickness of interconnection line.Along with dwindling of chip size; The raising of density and the raising of chip complexity, the width of interconnection line constantly reduces, the also inevasible increase of the total length L of interconnection line; Therefore, only remaining resistivity of the factor that can reduce resistance and thickness can have been known from above-mentioned formula.And from the aluminium interconnect improvement to copper-connection, thereby realize the reduction of the resistance of overall interconnection layer exactly through the resistivity that reduces interconnection line, still, for same material, its resistivity is certain basically.Unique factor that therefore, can be used to reduce the resistance of copper interconnecting line has just had only the thickness H that improves interconnection line.
But because the restriction of metal filled technology and etching technics, Embedded copper interconnection structure will realize successfully that its basic technology conditional request depth-width ratio can not be excessive, and promptly for the copper interconnecting line of a certain width, its thickness can not be too thick.Because thickness is too thick, mean that the groove structure degree of depth is very big, will be unfavorable for that etching technics controls etched pattern and size; And the also difficult completion complete filling of metal filled technology; Can increase square resistance so on the contrary, reduce the reliability of interconnection, bring very adverse influence.Therefore integral thickness that can not unconfined increase interconnection line reduces square resistance.
Summary of the invention
The purpose of this invention is to provide a kind of manufacturing approach that reduces the copper interconnection structure of square resistance; To realize optionally increasing the thickness of part metals line; Reduce square resistance, thereby improve the speed of chip and reduce the wastage the final purpose that realizes improving chip performance.
For addressing the above problem, the present invention provides a kind of manufacturing approach that reduces the copper interconnection structure of square resistance, comprises the steps:
The semiconductor-based end that comprises an anterior layer copper interconnection layer, be provided;
On the said semiconductor-based end, form etching barrier layer, dielectric layer, dielectric protection layer and metal hard mask layer in regular turn;
Through photoetching and etching, in dielectric protection layer, form the groove figure of a plurality of first degree of depth;
In the groove figure of said first degree of depth of part, continue the etching dielectric protection layer, form the groove figure of second degree of depth, in the anterior layer copper interconnection layer at the wherein said semiconductor-based end, do not have through hole with the corresponding position of the groove figure of said second degree of depth;
Form the via hole image that is connected with the groove figure of said first degree of depth and runs through dielectric protection layer and part dielectric layer through photoetching and etching, the degree of depth of the groove figure of wherein said second degree of depth is less than the groove figure of first degree of depth and the total depth of via hole image;
Adopt etching technics, the groove figure of said first degree of depth, the groove figure and the synchronous down etching of via hole image of second degree of depth are removed until the dielectric layer of via hole image bottom fully, form first depth groove, second depth groove and through hole;
Remove the etching barrier layer of via bottoms, make the intrabasement anterior layer copper interconnection layer of through hole and said semiconductor be connected;
Sputtering sedimentation metal diffusion barrier layer and copper seed layer in first depth groove, second depth groove and through hole adopt electroplating technology to carry out copper and fill;
Adopt cmp to remove unnecessary metallic copper, metal hard mask layer and dielectric protection layer on the dielectric layer, form copper-connection.
As preferably, the degree of depth of said second depth groove is greater than the degree of depth of first depth groove and less than the total depth of first depth groove and through hole.
As preferably, the technology that said etching adopted is dry etching.
As preferably, said dielectric layer adopts chemical vapor deposition or spin coating process to form, and said dielectric layer adopts advanced low-k materials, and dielectric constant is 2～4.2.
As preferably, the material of said metal hard mask layer is TiN or TaN.
Compared with prior art; A kind of manufacturing approach that reduces the copper interconnection structure of square resistance of the present invention adopts dual damascene process to increase the gash depth of specific region in the copper interconnecting line through photoetching and etching; Make the copper interconnecting line thickness that is filled in this groove increase; Optionally reduce the square resistance of the copper interconnecting line of this trench region; Under the situation that does not increase technology difficulty, farthest reduce the square resistance of copper interconnection structure, thereby can reduce the signal delay of chip, improve the overall performance of chip.
Description of drawings
Fig. 1 is a manufacturing approach flow chart of the present invention;
Fig. 2 a-Fig. 2 l is the profile of each processing step in one embodiment of the invention manufacturing approach flow process.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
To combine generalized section that the manufacturing approach of a kind of copper interconnection structure of the present invention is described in more detail below; The preferred embodiments of the present invention have wherein been represented; Should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing to those skilled in the art, and not as limitation of the present invention.
Fig. 2 a-Fig. 2 l shows one embodiment of the invention, and is as shown in Figure 1, and the manufacturing approach of the said copper interconnection structure that reduces square resistance is following:
In step 101, shown in Fig. 2 a, semiconductor substrate 200 is provided; The said semiconductor-based end 200 can be the silicon chip that is formed with device layer and/or metal interconnecting layer; In present embodiment, be formed with the anterior layer interconnection layer at semiconductor-based the end 200, have groove 210 in this anterior layer interconnection layer.For convenient diagram, all omitted the part below the groove among Fig. 2 a-Fig. 2 l.On the said semiconductor-based end 200, adopt chemical vapor deposition to form etching barrier layer 201, the material of said etching barrier layer 201 is a nitrogen-doped silicon carbide; Deposition of dielectric layer 202 on etching barrier layer 201, and said dielectric layer 202 adopts chemical vapor deposition or rotation to apply and forms, and said dielectric layer 202 adopts advanced low-k materials, and dielectric constant is 2～4.2; Chemical vapor deposition SiO on dielectric layer 202
2 Dielectric protection layer 203 adopts physical vapour deposition (PVD) or chemical vapour deposition (CVD) on said dielectric protection layer 203, to form metal hard mask layer 204, and the material of said metal hard mask layer 204 is TiN or TaN, and its thickness arrives between the hundreds of nanometer in the number nanometer.
In step 102,, in dielectric protection layer, form the groove figure of a plurality of first degree of depth through photoetching and etching.Shown in Fig. 2 b, deposition bottom antireflective coating 205 applies photoresist on bottom antireflective coating 205 on metal hard mask layer 204, forms first photoresist layer 206 of the groove figure of corresponding first degree of depth through the photoetching first time; Shown in Fig. 2 c, be mask for 206 layers with said first photoresist for another example, etching bottom antireflective coating 205 forms first etching window 207 with metal hard mask layer 204; Shown in Fig. 2 d, the dielectric protection layer 203 in etching first etching window 207, the groove figure of formation first degree of depth is removed said first photoresist layer 206 in dielectric protection layer 203; In the present embodiment, preferably adopt the groove figure of dual damascene process etching first degree of depth; The method of said etching bottom antireflective coating 205 and metal hard mask layer 204 preferably adopts dry etching.
In step 103, in the groove figure of said first degree of depth of part, continue the etching dielectric protection layer, form the groove figure of second degree of depth.In the groove figure of above-mentioned a plurality of first degree of depth, selection its underpart does not exist the variation of the parasitic capacitance of through hole and following square structure can ignore to the influence of device or part groove figure within the acceptable range continues etching; Shown in Fig. 2 e, at said structure surface-coated photoresist, in photoresist, open the second etching window 207a through the photoetching second time, form the corresponding second photoresist layer 206a that continues the part groove figure of etching; For another example shown in Fig. 2 f; Dielectric protection layer in the etching second etching window 207a; In dielectric protection layer 207a, form the groove figure of second degree of depth; Remove the said second photoresist layer 206a, then obtain the structure shown in Fig. 2 g, in the anterior layer copper interconnection layer at the wherein said semiconductor-based end 200; Do not have through hole with the corresponding position of the groove figure of said second degree of depth, and the variation of the parasitic capacitance of square structure can be ignored to the influence of device or within the acceptable range under this groove figure; In the present embodiment, the method for etching dielectric protection layer preferably adopts dry etching.
In step 104, shown in Fig. 2 h,, in photoresist, open three quarters of an hour fenetre mouth 207b through photoetching for the third time at said structure surface-coated photoresist, form the 3rd photoresist layer 206b of corresponding via hole image; For another example shown in Fig. 2 i; Dielectric protection layer 203 and dielectric layer 202 in the etching three quarters of an hour fenetre mouth; Formation runs through the via hole image of dielectric protection layer 203 and part dielectric layer 202, removes said the 3rd photoresist layer 206b, then obtains the structure shown in Fig. 2 j; Wherein, Groove figure with first degree of depth is connected with via hole image, and the degree of depth h of the groove figure of said second degree of depth is greater than the degree of depth h1 of the groove figure of first degree of depth, and less than the groove figure of first degree of depth and the total depth h2 of via hole image.In the present embodiment, preferably adopt dual damascene process etching through hole figure.
Wherein, the degree of depth h1 of the groove figure of said first degree of depth and the degree of depth h3 of via hole image are normal depth, and the degree of depth h of the groove figure of second degree of depth deepens than normal depth to some extent.
In step 105; Shown in Fig. 2 k, adopt integrated etching technics, to the groove figure of the groove figure of said first degree of depth, second degree of depth and via hole image etching down synchronously; Dielectric layer 202 until the via hole image bottom is removed fully; Form first depth groove, second depth groove and through hole, and remove the etching barrier layer 201 of via bottoms, make through hole be connected with groove 210 in the anterior layer copper interconnection layer; In the anterior layer copper interconnection layer at the wherein said semiconductor-based end 200; There is not through hole with corresponding position, said second depth groove zone, thereby can not influences through hole resistance, simultaneously should the zone can ignore to the influence of device with the variation of the parasitic capacitance of following square structure or within the acceptable range; In addition, the depth H of said second depth groove is greater than the depth H 1 of first depth groove and less than the total depth H2 of first depth groove and through hole.
In step 106, sputtering sedimentation metal barrier and copper seed layer in first depth groove, second depth groove and through hole adopt electroplating technology to carry out copper and fill; In the present embodiment, also can adopt ald (ALD) growing metal barrier layer and copper seed layer.
In step 107, shown in Fig. 2 l, adopt cmp to remove metallic copper, metal hard mask layer, bottom antireflective coating and dielectric protection layer redundant on the dielectric layer 202, form copper-connection 208.
The manufacturing approach that reduces the copper interconnection structure of square resistance of the present invention can be carried out the selectivity thickening to the degree of depth of copper interconnecting line groove; The copper interconnecting line square resistance of qualified specific region is reduced; Thereby realize that selectivity reduces the purpose of chip interconnect square resistance; Thereby reduce the signal delay of chip, reduce the wastage, improve the chip overall performance.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of equivalent technologies of claim of the present invention if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (5)
1. the manufacturing approach that can reduce the copper interconnection structure of square resistance is characterized in that, may further comprise the steps:
The semiconductor-based end that comprises an anterior layer copper interconnection layer, be provided;
On the said semiconductor-based end, form etching barrier layer, dielectric layer, dielectric protection layer and metal hard mask layer in regular turn;
Through photoetching and etching, in dielectric protection layer, form the groove figure of a plurality of first degree of depth;
In the groove figure of said first degree of depth of part, continue the etching dielectric protection layer, form the groove figure of second degree of depth, in the anterior layer copper interconnection layer at the wherein said semiconductor-based end, do not have through hole with the corresponding position of the groove figure of said second degree of depth;
Form the via hole image that is connected with the groove figure of said first degree of depth and runs through dielectric protection layer and part dielectric layer through photoetching and etching, the degree of depth of the groove figure of wherein said second degree of depth is less than the groove figure of first degree of depth and the total depth of via hole image;
Adopt etching technics, the groove figure of said first degree of depth, the groove figure and the synchronous down etching of via hole image of second degree of depth are removed until the dielectric layer of via hole image bottom fully, form first depth groove, second depth groove and through hole;
Remove the etching barrier layer of via bottoms, make the intrabasement anterior layer copper interconnection layer of through hole and said semiconductor be connected;
Sputtering sedimentation metal diffusion barrier layer and copper seed layer in first depth groove, second depth groove and through hole adopt electroplating technology to carry out copper and fill;
Adopt cmp to remove unnecessary metallic copper, metal hard mask layer and dielectric protection layer on the dielectric layer, form copper-connection.
2. method according to claim 1 is characterized in that, the degree of depth of said second depth groove is greater than the degree of depth of first depth groove and less than the total depth of first depth groove and through hole.
3. method according to claim 1 is characterized in that the technology that said etching adopted is dry etching.
4. method according to claim 1 is characterized in that, said dielectric layer adopts chemical vapor deposition or spin coating process to form, and said dielectric layer adopts advanced low-k materials, and dielectric constant is 2～4.2.
5. method according to claim 1 is characterized in that, the material of said metal hard mask layer is TiN or TaN.
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| CN 201110388945 CN102437108B (en) | 2011-11-30 | 2011-11-30 | Manufacturing method of copper interconnection structure capable of reducing block resistance |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102790010A (en) * | 2012-08-16 | 2012-11-21 | 上海华力微电子有限公司 | Preparation method of copper interconnected layer for improving reliability and semiconductor device |
| CN102867780A (en) * | 2012-09-17 | 2013-01-09 | 上海华力微电子有限公司 | Copper interconnection process |
| CN102867735A (en) * | 2012-09-17 | 2013-01-09 | 上海华力微电子有限公司 | Manufacture method of MOM capacitor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6498092B2 (en) * | 2000-07-25 | 2002-12-24 | Samsung Electronics Co., Ltd. | Method of making a semiconductor device having dual damascene line structure using a patterned etching stopper |
| US20050184288A1 (en) * | 2004-02-25 | 2005-08-25 | Tien-I Bao | Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method |
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2011
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6498092B2 (en) * | 2000-07-25 | 2002-12-24 | Samsung Electronics Co., Ltd. | Method of making a semiconductor device having dual damascene line structure using a patterned etching stopper |
| US20050184288A1 (en) * | 2004-02-25 | 2005-08-25 | Tien-I Bao | Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102790010A (en) * | 2012-08-16 | 2012-11-21 | 上海华力微电子有限公司 | Preparation method of copper interconnected layer for improving reliability and semiconductor device |
| CN102790010B (en) * | 2012-08-16 | 2014-08-27 | 上海华力微电子有限公司 | Preparation method of copper interconnected layer for improving reliability and semiconductor device |
| CN102867780A (en) * | 2012-09-17 | 2013-01-09 | 上海华力微电子有限公司 | Copper interconnection process |
| CN102867735A (en) * | 2012-09-17 | 2013-01-09 | 上海华力微电子有限公司 | Manufacture method of MOM capacitor |
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| CN102437108B (en) | 2013-10-23 |
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