CN102446843B - Method for achieving high-performance copper interconnection by utilizing upper mask - Google Patents
Method for achieving high-performance copper interconnection by utilizing upper mask Download PDFInfo
- Publication number
- CN102446843B CN102446843B CN201110359760.8A CN201110359760A CN102446843B CN 102446843 B CN102446843 B CN 102446843B CN 201110359760 A CN201110359760 A CN 201110359760A CN 102446843 B CN102446843 B CN 102446843B
- Authority
- CN
- China
- Prior art keywords
- layer
- etching
- interconnection
- utilize
- copper interconnection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a method for achieving high-performance copper interconnection by utilizing an upper mask. The method is characterized in that a semiconductor substrate with a metal interconnection layer is arranged, wherein a composite structure is formed on the metal interconnection layer of the semiconductor substrate and comprises an etch stop layer, a dielectric layer, an upper coating, an etch adjustment layer and a mask layer from bottom to top in sequence; and the etch adjustment layer is made of a low dielectric constant material film. The invention has the following beneficial effects: through the process flow and method disclosed by the invention, the added low dielectric constant material etch depth adjustment layer is utilized to selectively change the depth of the grooves of copper interconnection lines, thus reducing the square resistance of the copper interconnection lines which conform to the conditions and are arranged in the specific region, and further achieving the aim of selectively reducing the chip interconnection resistance; and by utilizing the method, the interconnection resistance can be furthest reduced on the premises of not changing the overall copper interconnection depth, not increasing the process difficulty and not reducing the process window, thus reducing the signal delay of the chips, reducing the losses and improving the overall performance of the chips.
Description
Technical field
The present invention relates to field of semiconductor manufacture, especially a kind of method of utilizing mask to realize high-performance copper interconnection.
Background technology
In semiconductor integrated circuit industry, high performance integrated circuit chip needs high performance back segment electricity to connect.Metallic copper, due to its low-resistivity characteristic, has obtained application more and more widely in advanced integrated circuit (IC) chip.From aluminum steel to copper cash, the change of material has brought the huge reduction of resistivity.Along with the progress of integrated circuit technique, the increase of chip complexity, this means that the resistance of the back segment interconnection line in chip becomes one of bottleneck of performance.How effectively to reduce resistance, become an important subject of back segment interconnection.
From resistance formula, we can obtain some inspirations:
(in above-mentioned formula, R represents resistance, and ρ represents the resistivity of material, and L represents conductor length, and W represents interconnection line width, and H represents the thickness of interconnection line.) along with the dwindling of chip size, the raising of density and the raising of chip complexity, the width of interconnection line constantly reduces, the also inevasible increase of the total length L of interconnection line.The factor of resistance be can reduce and only resistivity and thickness have been left.And be switched to copper-connection from aluminium interconnection, thereby the resistivity that reduces interconnection line realizes the reduction of overall resistance.And for same material, its resistivity is certain substantially.Therefore, can just only be improved the thickness H of interconnection line for reducing unique factor of the resistance of high-end copper interconnecting line.In order to characterize more accurately the impact of thickness on resistance, (sheet resistance, is also sheet resistance, and computing formula is in semiconductor technology, to adopt square resistance
rs=ρ/H, R=Rs*L/W) characterize.For the difform interconnection line of same process, square resistance can symbolize the impact of thickness on resistance accurately like this, and is not subject to the impact of conductor length and width.
In fact, due to the restriction of metal filled technique and etching technics, Embedded copper interconnection structure will successfully be realized, and its basic technology conditional request depth-width ratio can not be excessive, and, for the copper interconnecting line of a certain width, its thickness can not be too thick.Because thickness is too thick, mean that the groove structure degree of depth is very large, will be unfavorable for that etching technics controls etched pattern and size, and metal filled technique also more difficult complete completely fill, can increase resistance so on the contrary, reduce the reliability of interconnection, bring very adverse influence.Therefore integral thickness that can not unconfined increase interconnection line reduces resistance.
Summary of the invention
The problems referred to above that exist for existing back segment electricity syndeton, the invention provides a kind of method of utilizing mask to realize high-performance copper interconnection.
The technological means that technical solution problem of the present invention adopts is:
Utilize mask to realize a method for high-performance copper interconnection, comprise that one exists the semiconductor base of metal interconnecting layer, wherein, comprise following concrete steps:
Step a, on the metal interconnecting layer of described semiconductor base, form a composite construction, described composite construction is etching stop layer, dielectric layer, overlying strata, etching adjustment layer and mask layer from down to up successively, and it is low-dielectric constant film that described etching is adjusted layer;
Step b, described composite construction is carried out to etching, in described mask layer, form the pattern of metal interconnection structure and make etching stopping adjust layer in described etching;
Step c, in described metal interconnection structure plan, the predetermined described etching that needs the region of deepening is adjusted to layer and removes;
Steps d, in described metal interconnect structure pattern, photoetching and partial etching are carried out in the predetermined position that forms through hole, make to form on described composite construction the through-hole pattern of desired depth;
Step e, described composite construction is carried out to etching, the groove and the through hole that to form described metal interconnection structure plan, sketch the contours;
Step f, in described groove and through hole embedded with metal, make described metal be full of described groove and through hole;
Step g, smooth described composite structure surface.
In above-mentioned utilization, mask is realized the method for high-performance copper interconnection, and wherein, described etching stop layer is nitrogen-doped silicon carbide layer.
In above-mentioned utilization, mask is realized the method for high-performance copper interconnection, and wherein, the relative dielectric constant of described dielectric layer is 2-4.2.
In above-mentioned utilization, mask is realized the method for high-performance copper interconnection, and wherein, described overlying strata is silicon oxide layer.
In above-mentioned utilization, mask is realized the method for high-performance copper interconnection, and wherein, described low-dielectric constant film is fluorine doped silicon oxide glass film, or carbon doped silicon oxide film, or porous low dielectric constant material film.
In above-mentioned utilization, mask is realized the method for high-performance copper interconnection, and wherein, described mask layer is titanium nitride metal level.
In above-mentioned utilization, mask is realized the method for high-performance copper interconnection, wherein, in described step b, described in etching, composite construction ground method is: utilize photoetching that described metal interconnection structure plan is transferred to described mask layer, etching is removed the mask layer in described metal interconnection structure plan.
In above-mentioned utilization, mask is realized the method for high-performance copper interconnection, wherein, the method of removing described etching adjustment layer in described step c is: utilize a predefine light shield, described in etching, subscribe and need the described etching in the region of intensification to adjust layer, etching mode is plasma dry etching, and described etching stopping is in described overlying strata.
In above-mentioned utilization, mask is realized the method for high-performance copper interconnection, and wherein, in described step f, the metal of inlaying is copper.
In above-mentioned utilization, mask is realized the method for high-performance copper interconnection, and wherein, in described step g, the method for smooth described composite structure surface is cmp.
In above-mentioned utilization, mask is realized the method for high-performance copper interconnection, and wherein, the formation method of described nitrogen-doped silicon carbide layer is chemical vapor deposition.
In above-mentioned utilization, mask is realized the method for high-performance copper interconnection, and wherein, the formation method of described dielectric layer is chemical vapor deposition.
In above-mentioned utilization, mask is realized the method for high-performance copper interconnection, and wherein, the formation method of described silicon oxide layer is chemical vapor deposition.
In above-mentioned utilization, mask is realized the method for high-performance copper interconnection, and wherein, the formation method of described low-dielectric constant film is chemical vapor deposition.
In above-mentioned utilization, mask is realized the method for high-performance copper interconnection, and wherein, the formation method of described titanium nitride metal level is physical vapor deposition.
In above-mentioned utilization, mask is realized the method for high-performance copper interconnection, wherein, between the groove on described metallic copper and described composite construction and through hole, has barrier layer.
In above-mentioned utilization, mask is realized the method for high-performance copper interconnection, and wherein, the method for embedding of described metallic copper is for electroplating.
In above-mentioned utilization, mask is realized the method for high-performance copper interconnection, and wherein, described barrier layer is tantalum or tantalum nitride.
In above-mentioned utilization, mask is realized the method for high-performance copper interconnection, and wherein, the formation method of described tantalum or desalination tantalum barrier layer is physical vapor deposition.
The invention has the beneficial effects as follows:
By technological process of the present invention and method, utilize the advanced low-k materials etching depth adding to adjust layer, the degree of depth of copper interconnecting line groove is carried out to selectively changing, thereby the copper interconnecting line square resistance of qualified specific region is reduced, thereby realize the object of elective reduction chip interconnects resistance.Through utilization of the present invention, can not increase technology difficulty not changing global copper interconnect depth,, under the prerequisite of reduction process window, farthest do not reduce interconnected resistance, thereby reduce the signal delay of chip, reduce the wastage, improve chip overall performance.
Accompanying drawing explanation
Fig. 1 is a kind of flow chart that utilizes mask to realize the method for high-performance copper interconnection of the present invention;
Fig. 2 is the profile status structure chart after a kind of step a that utilizes mask to realize the method for high-performance copper interconnection of the present invention completes;
Fig. 3 is the profile status structure chart after a kind of step b that utilizes mask to realize the method for high-performance copper interconnection of the present invention completes;
Fig. 4 is the profile status structure chart after a kind of step c that utilizes mask to realize the method for high-performance copper interconnection of the present invention completes;
Fig. 5 is the profile status structure chart after a kind of steps d of utilizing mask to realize the method for high-performance copper interconnection of the present invention completes;
Fig. 6 is the profile status structure chart after a kind of step e that utilizes mask to realize the method for high-performance copper interconnection of the present invention completes;
Fig. 7 is the profile status structure chart after a kind of step f that utilizes mask to realize the method for high-performance copper interconnection of the present invention completes;
Fig. 8 is the profile status structure chart after a kind of step g of utilizing mask to realize the method for high-performance copper interconnection of the present invention completes.
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention will be further described, but not as limiting to the invention.
As shown in Figure 1, a kind of method of utilizing mask to realize high-performance copper interconnection of the present invention, comprises that one exists the semiconductor base 100 of metal interconnecting layer 110, wherein, comprises following concrete steps:
As shown in Figure 2, step a, on the metal interconnecting layer 110 of semiconductor base 100, form a composite construction 200, composite construction 200 is that etching stop layer 210, dielectric layer 220, overlying strata 230, etching are adjusted layer 240 and mask layer 250 from down to up successively.
Wherein said etching stop layer 210 is nitrogen-doped silicon carbide layer, and its formation method can be chemical vapor deposition; Dielectric layer 220 can be fluorine doped silicon oxide glass, carbon doped silicon oxide, porous low dielectric constant material, in practical application, can be also that traditional dielectric material is as silica, the dielectric material that the relative dielectric constants such as boron phosphor silicon oxide glass are 2-4.2, its formation method can be chemical vapor deposition; Overlying strata 230 is silicon oxide layer, and its formation method can be chemical vapor deposition; It is low-dielectric constant film that etching is adjusted layer 240, the general low-dielectric constant film that adopts k value <4, its thickness range is 5 ~ 800 nanometers, the size of the required adjustment degree of depth of its thickness selective basis and the different materials etching selection ratio of adjustment layer film and copper-connection dielectric film determine jointly, its formation method can be chemical vapor deposition, and its material can be selected fluorine doped silicon oxide glass film, carbon doped silicon oxide film or porous low dielectric constant material film; Mask layer 250 is titanium nitride metal level, and its formation method can be physical vapour deposition (PVD).
As shown in Figure 3, step b, composite construction 200 is carried out to etching, in mask layer 250, form the pattern 300 of metal interconnection structures and make etching stopping adjust layer 210 in etching; Wherein the method for etching composite construction 200 is: form photoresistance 400 and utilize photoetching that metal interconnection structure plan 300 is transferred to mask layer 250, etching is removed the mask layer 250 in metal interconnection structure plan 300.
As shown in Figure 4, step c, in metal interconnection structure plan 300, adjusts layer 240 by the predetermined etching that needs the region 310 of deepening and removes; The method of removing etching adjustment layer 240 is: utilize predefine light shield 410 coverings not need the region of deepening, etching is subscribed the etching adjustment layer 240 in the region 310 that need to deepen, and etching mode is plasma dry etching, and etching stopping is in overlying strata 230.
As shown in Figure 5, steps d, in metal interconnect structure pattern 300, photoetching and partial etching are carried out in the predetermined position that forms through hole 340, make to form on composite construction 200 pattern of the through hole 330 of desired depth; The pattern of through hole 340 makes through hole 340 structures temporarily rest in the middle of dielectric layer 220 after the method for partial etching, be conducive to like this to reduce the damage of final through hole 340 structures in the process of removing photoresistance, in this step by regulating the degree of depth of partial etching to control the depth scale of groove and through hole in final form.
As shown in Figure 6, step e, composite construction 200 is carried out to etching, the groove 330 and through hole 340 that to form metal interconnection structure plan 300, sketch the contours; Remove after photoresistance, substrate 100 surfaces have only retained the mask layer 250 with metal interconnection structure plan 300 features.Utilize stopping of mask layer 250, composite construction 200 in substrate 100 is carried out to plasma dry etching, form groove 330, make through hole 340 etch into dielectric layer 220 bottoms simultaneously, and open etching barrier layer 210 so that the connection of the metal interconnecting layer 110 in former substrate 100.Because the effect of etching adjustment layer 240 makes the predetermined groove 330 that need to deepen region 310 darker than the groove in other regions 330.
As shown in Figure 7, step f, in groove 330 and the interior embedded with metal 350 of through hole 340, makes metal 350 be full of groove 340 and through hole 350; Wherein, the metal 350 of inlaying is copper, has barrier layer (not marking in the drawings) between the groove 330 on metal 350 and composite construction 200 and through hole 340, and barrier layer is tantalum or tantalum nitride, and its formation method is physical vapor deposition.On barrier layer, form the inculating crystal layer of a bronze medal, adopt electric plating method on the inculating crystal layer of copper, to continue to fill and make copper be full of groove 330 and through hole 340, wherein this copper filling step must have a certain amount of redundancy to make up the loss of the metallic copper that may cause in follow-up surfacing step.
As shown in Figure 8, step g, smooth composite construction 200 surfaces, remove and inlay copper redundancy and mask layer, etching adjustment layer and the overlying strata that step produces, and the method on smooth composite construction 200 surfaces is cmp.
As can be seen from Figure 8 the copper interconnecting line in groove intensification region 310 has larger thickness, and the copper in this region has larger conductive section, therefore has lower square resistance Rs.Due to the copper degree of depth in this region, be less than again the degree of depth of copper in through hole 340, can guarantee that the copper interconnecting line of intensification can be realized good filling smoothly, unrestricted on technological ability.
In fact, the present invention also can embedded for individual layer (single Damascus) technique in.As long as the fill process of copper can guarantee that copper can be filled in structure smoothly, and the structure of below, selected groove intensification region does not affect adversely.
The foregoing is only preferred embodiment of the present invention; not thereby limit claim of the present invention; so the equivalent structure that all utilizations specification of the present invention and diagramatic content have been done changes, utilizes the material of mentioning the same-actions such as tool in known and the present invention to replace; utilize the means and methods of the same-actions such as means and methods tool of mentioning in known and the present invention to replace, resulting execution mode or result of implementation are all included in protection scope of the present invention.
Claims (18)
1. in utilization, mask is realized the method for high-performance copper interconnection, comprises that one exists the semiconductor base of metal interconnecting layer, it is characterized in that, comprises following concrete steps:
Step a, on the metal interconnecting layer of described semiconductor base, form a composite construction, described composite construction is etching stop layer, dielectric layer, overlying strata, etching adjustment layer and mask layer from down to up successively, and it is low-dielectric constant film that described etching is adjusted layer;
Step b, described composite construction is carried out to etching, in described mask layer, form the pattern of metal interconnection structure and make etching stopping adjust layer in described etching;
Step c, in described metal interconnection structure plan, the predetermined described etching adjustment layer in the region of intensification that needs is removed, the method that described etching adjustment layer is removed is: utilize a predefine light shield, cover the predetermined position that forms through hole, described in etching, the predetermined described etching in the region of intensification that needs is adjusted layer, etching mode is plasma dry etching, and described etching stopping is in described overlying strata;
Steps d, in described metal interconnect structure pattern, photoetching and partial etching are carried out in the predetermined position that forms through hole, make to form on described composite construction the through-hole pattern of desired depth;
Step e, described composite construction is carried out to etching, the groove and the through hole that to form described metal interconnection structure plan, sketch the contours;
Step f, in described groove and through hole embedded with metal, make described metal be full of described groove and through hole;
Step g, smooth described composite structure surface.
2. utilize as claimed in claim 1 upper mask to realize the method for high-performance copper interconnection, it is characterized in that, described etching stop layer is nitrogen-doped silicon carbide layer.
3. utilize as claimed in claim 1 upper mask to realize the method for high-performance copper interconnection, it is characterized in that, the relative dielectric constant of described dielectric layer is 2-4.2.
4. utilize as claimed in claim 1 upper mask to realize the method for high-performance copper interconnection, it is characterized in that, described overlying strata is silicon oxide layer.
5. utilize as claimed in claim 1 upper mask to realize the method for high-performance copper interconnection, it is characterized in that, described low-dielectric constant film is fluorine doped silicon oxide glass film, or carbon doped silicon oxide film, or porous low dielectric constant material film.
6. utilize as claimed in claim 1 upper mask to realize the method for high-performance copper interconnection, it is characterized in that, described mask layer is titanium nitride metal level.
7. utilize as claimed in claim 1 upper mask to realize the method for high-performance copper interconnection, it is characterized in that, the method of composite construction described in etching in described step b: utilize photoetching that described metal interconnection structure plan is transferred to described mask layer, etching is removed the mask layer in described metal interconnection structure plan.
8. utilize as claimed in claim 1 upper mask to realize the method for high-performance copper interconnection, it is characterized in that, in described step f, the metal of inlaying is copper.
9. utilize as claimed in claim 1 upper mask to realize the method for high-performance copper interconnection, it is characterized in that, in described step g, the method for smooth described composite structure surface is cmp.
10. utilize as claimed in claim 2 upper mask to realize the method for high-performance copper interconnection, it is characterized in that, the formation method of described nitrogen-doped silicon carbide layer is chemical vapor deposition.
11. utilize upper mask to realize the method for high-performance copper interconnection as claimed in claim 3, it is characterized in that, the formation method of described dielectric layer is chemical vapor deposition.
12. utilize upper mask to realize the method for high-performance copper interconnection as claimed in claim 4, it is characterized in that, the formation method of described silicon oxide layer is chemical vapor deposition.
13. utilize upper mask to realize the method for high-performance copper interconnection as claimed in claim 5, it is characterized in that, the formation method of described low-dielectric constant film is chemical vapor deposition.
14. utilize upper mask to realize the method for high-performance copper interconnection as claimed in claim 6, it is characterized in that, the formation method of described titanium nitride metal level is physical vapor deposition.
15. utilize upper mask to realize the method for high-performance copper interconnection as claimed in claim 9, it is characterized in that, between the groove on the groove on described composite construction and the metallic copper in through hole and described composite construction and through hole, have barrier layer.
16. utilize upper mask to realize the method for high-performance copper interconnection as claimed in claim 9, it is characterized in that, the groove on described composite construction and the method for embedding of the metallic copper in through hole are for electroplating.
17. utilize upper mask to realize the method for high-performance copper interconnection as claimed in claim 15, it is characterized in that, described barrier layer is tantalum or tantalum nitride.
18. utilize upper mask to realize the method for high-performance copper interconnection as claimed in claim 17, it is characterized in that, the formation method on described barrier layer is physical vapor deposition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110359760.8A CN102446843B (en) | 2011-11-15 | 2011-11-15 | Method for achieving high-performance copper interconnection by utilizing upper mask |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110359760.8A CN102446843B (en) | 2011-11-15 | 2011-11-15 | Method for achieving high-performance copper interconnection by utilizing upper mask |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102446843A CN102446843A (en) | 2012-05-09 |
| CN102446843B true CN102446843B (en) | 2014-10-15 |
Family
ID=46009222
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110359760.8A Active CN102446843B (en) | 2011-11-15 | 2011-11-15 | Method for achieving high-performance copper interconnection by utilizing upper mask |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102446843B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446846B (en) * | 2011-11-28 | 2014-03-12 | 上海华力微电子有限公司 | Method for achieving high-performance copper interconnection by utilizing upper mask |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5601974B2 (en) * | 2010-01-19 | 2014-10-08 | パナソニック株式会社 | Semiconductor device and manufacturing method thereof |
-
2011
- 2011-11-15 CN CN201110359760.8A patent/CN102446843B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN102446843A (en) | 2012-05-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102446846B (en) | Method for achieving high-performance copper interconnection by utilizing upper mask | |
| CN102394227B (en) | Manufacturing method of copper interconnection structure capable of reducing square resistance | |
| CN102362343B (en) | Metallization system of semiconductor device comprising extra-tapered transition vias | |
| CN102222643B (en) | Method for filling redundant metal in manufacturing process of integrated circuit and semiconductor device | |
| US8645879B2 (en) | Algorithm of Cu interconnect dummy inserting | |
| CN101060108A (en) | Anchored damascene structures | |
| CN102315163A (en) | Manufacturing method of ultralow-dielectric-constant film copper-interconnecting layer | |
| CN102569176A (en) | Method for preparing dual Damascene structure | |
| CN104701143B (en) | Dual layer hardmask for robust metallization profile | |
| CN102446843B (en) | Method for achieving high-performance copper interconnection by utilizing upper mask | |
| KR101841199B1 (en) | Method of forming semiconductor device and the device formed by the method | |
| US20130244544A1 (en) | Process control methods for cmp (chemical mechanical polishing) and other polishing methods used to form semiconductor devices | |
| CN102456618B (en) | Method for realizing high-performance copper interconnection by upper mask | |
| CN104253087B (en) | The fill method in aluminum metal process contact hole | |
| CN104934367A (en) | Preparation method of interconnect copper | |
| CN102569178A (en) | Method for realizing high-performance copper interconnection by using upper mask | |
| CN102446847B (en) | Full photoresistance dual damascene method capable of reducing sheet resistance of copper interconnection | |
| CN102437108B (en) | Manufacturing method of copper interconnection structure capable of reducing block resistance | |
| CN102569177A (en) | Method for realizing high-performance copper interconnection by using upper mask | |
| CN102443830A (en) | Method for improving copper electroplating process | |
| CN102324399B (en) | Semiconductor device and manufacturing method thereof | |
| CN102446848B (en) | Single Damascus method used for reducing square resistance of copper interconnection | |
| CN102324403B (en) | Method for manufacturing ultra-low dielectric constant film copper interconnection | |
| CN211480005U (en) | Semiconductor structure | |
| CN102446849B (en) | Method for forming single Damascus of thick metal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |