CN102569096A - 具有垫连接的集成电路封装系统及其制造方法 - Google Patents

具有垫连接的集成电路封装系统及其制造方法 Download PDF

Info

Publication number
CN102569096A
CN102569096A CN2011103970472A CN201110397047A CN102569096A CN 102569096 A CN102569096 A CN 102569096A CN 2011103970472 A CN2011103970472 A CN 2011103970472A CN 201110397047 A CN201110397047 A CN 201110397047A CN 102569096 A CN102569096 A CN 102569096A
Authority
CN
China
Prior art keywords
integrated circuit
pin
pad
package system
articulamentum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011103970472A
Other languages
English (en)
Other versions
CN102569096B (zh
Inventor
H·D·巴森
Z·R·卡马乔
D·A·梅里洛
E·埃斯皮里图
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Stats Chippac Pte Ltd
Original Assignee
Stats Chippac Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Pte Ltd filed Critical Stats Chippac Pte Ltd
Publication of CN102569096A publication Critical patent/CN102569096A/zh
Application granted granted Critical
Publication of CN102569096B publication Critical patent/CN102569096B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本发明涉及具有垫连接的集成电路封装系统及其制造方法，该制造集成电路封装系统的方法包含：形成引脚，该引脚在引脚顶侧具有水平脊部；直接在该引脚顶侧上形成具有内垫和外垫的连接层，该内垫具有内垫底面；将集成电路装设至该内垫上方；在该集成电路、该内垫、及该外垫上方施加具有制模底面的制模化合物；以及直接在该制模底面及该内垫底面上施加介电质。

Description

具有垫连接的集成电路封装系统及其制造方法
技术领域
本发明大体上系关于集成电路封装系统，且尤系关于用于具有连接的集成电路封装系统的系统。
背景技术
现代的电子装置(例如智能型手机、个人数字助理、与位置相关的服务装置、企业级服务器、或企业级储存数组)将更多个集成电路组装至更小的实体体积内，并同时期待能减低成本。已发展出多种符合这些要求的科技。一些研发策略专注在新科技，但其它的研发策略则专注在改良现有和成熟的科技。针对现有科技的研发有各式各样不同的方向。
消费性电子装置的要求使得在集成电路封装件中必需有更多个集成电路，但却又反常地在用于该增加的集成电路内容的系统中提供更少的实体空间。持续的成本降低又是另一项要求。一些技术主要是专注于将这些集成电路堆栈至单一封装件中。虽然这些方法在集成电路中提供更多种功能，然而，它们并没有完全针对较低的高度、较小的空间、及成本降低的要求。
一种经证明可降低成本的方法是以现有的制造方法和设备，来使用成熟的封装科技。但反常的是，现有制造制程的再使用却通常无法降低封装件的尺寸。仍持续要求较低成本、较小尺寸、和更多种功能。
因此，仍需要集成电路封装系统能具有较低成本、较小尺寸、和更多种功能。就改良集成和成本降低的持续增加的需求这方面来看，找到这些问题的答案变得非常重要。就持续增加的商业竞争压力、持续增长的消费者期待、并市场上针对有意义的产品差异性的消失机会等方面来看，找到这些问题的答案变得非常重要。此外，降低成本、改良效率和效能、及达到竞争压力等需求，对找到这些问题的答案的必要性增加更大的急迫性。
长期以来一直寻找这些问题的解决方案，但习知的发展并没有教示或建议任何解决方案，因此，这些问题的解决方案仍困扰着本领域中的熟习技术者。
发明内容
本发明提供一种制造集成电路封装系统的方法，包含：形成引脚，该引脚在引脚顶侧具有水平脊部；直接在该引脚顶侧上形成具有内垫和外垫的连接层，该内垫具有内垫底面；将集成电路装设至该内垫上方；在该集成电路、该内垫、及该外垫上方施加具有制模底面的制模化合物；以及直接在该制模底面及该内垫底面上施加介电质。
本发明提供一种集成电路封装系统，包含：引脚，其在引脚顶侧具有水平脊部；连接层，其具有直接在该引脚顶侧上的内垫和外垫，该内垫具有内垫底面；集成电路，在该内垫上方；制模化合物，具有制模底面且在该集成电路、该内垫、及该外垫上方；以及介电质，直接在该制模底面及该内垫底面上。
本发明的特定实施例除了上述的步骤和组件外另具有其它步骤和组件、或另具有其它步骤和组件以取代上述的步骤和组件。本领域中熟习技术者在阅读接下来的详细描述、并参考附随的图式后，该步骤和组件将变得明显。
附图说明
图1是本发明的第一实施例中集成电路封装系统沿着图2的线1-1的剖面图。
图2是该集成电路封装系统的下视图。
图3是本发明在电镀制造阶段中该集成电路封装系统沿着图4的线3-3的剖面图。
图4为在该电镀阶段中该集成电路封装系统的上视图。
图5为在固定阶段中图3的结构。
图6为在制模阶段中图5的结构。
图7为在移除阶段中图6的结构。
图8为在应用阶段中图7的结构。
图9为本发明的第二实施例中集成电路封装系统的剖面图。
图10为本发明的另一实施例中制造该集成电路封装系统的方法的流程图。
具体实施方式
以下实施例系充分详细描述以使熟悉本领域之技艺人士可制造及使用本发明，其它实施例依此揭露可明了而理解，而且其系统、制程或机构上的改变并未悖离本发明之范畴。
于下列叙述中，系给定多个详细说明以提供本发明之完整了解，然而，该发明之实施为显而易见的则未有这些详细细节。为避免模糊本发明，一些已知的电路、系统结构及制程步骤未详细地揭露。同样地，本发明实施例该些图的显示系为概略的且未有比例，且特别地，一些尺寸为清楚呈现本发明系夸大地显示于图标中。另外，在多个实施例中揭露及描述某些共同特征，为清楚及容易说明、描述及理解，彼此相似及相同特征将一般以相同参考编号来描述。
为说明的原因，在此使用的“水平(horizontal)”系定义为平行该集成电路的平面或表面，无论其定位；该“垂直(vertical)”名称系指垂直所定义的“水平”之方向，称“在…上面(above)”、“在…下面(below)”、“底部(bottom)”、“上方(top)”、“侧边”(如在“侧壁”)、“较高(higher)”、“较低(lower)”、“上面的(upper)”、“覆于…上(over)”以及“在…之下(under)”，系相对该水平平面而定义，称“在…上(on)”系指在组件间有直接接触，在此称“处理(processing)”系包含材料的设置、图案化、曝光、显影、蚀刻、清洁、注模，以及/或材料的移除或形成上述结构所需之要求，在此称“系统(system)”意指且系指依照上下文其系使用的本发明之方法及装置。
现在参考图1，其显示本发明的第一实施例中集成电路封装系统100沿着图2的线1-1的剖面图。该集成电路封装系统100可包含多列四方形平面无引脚(QFN)封装件，其具有用于覆晶的绕线迹线及底屏蔽。该集成电路封装系统100可包含不带有底座(standoff)的四方平面无引脚锯带蚀刻(QFNs-se)封装件。
该集成电路封装系统100可包含引脚102，该引脚102在该集成电路封装系统100及外部系统(未显示)之间提供电性连接。该引脚102可包含引脚底部104和相对于该引脚底部104或在该引脚底部104上方的引脚顶部106。
该引脚102可包含引脚底侧108和相对于该引脚底侧108的引脚顶侧110。该引脚底侧108为该引脚底部104的底部分。该引脚顶侧110为该引脚顶部106的顶部分。
该引脚102可包含介于该引脚底侧108和该引脚顶侧110之间的引脚非水平侧112。该引脚非水平侧112的平面可穿透该引脚底侧108和该引脚顶侧110的平面。
该引脚102可包含水平脊部114，该水平脊部114为该引脚102的端部，从该引脚非水平侧112水平地沿伸。该水平脊部114可形成在该引脚顶侧110处。
该水平脊部114可包含脊部下侧116和在该脊部下侧116上方的脊部上侧118。该脊部下侧116可包含曲面。该脊部上侧118可包含平面。
该集成电路封装系统100可包含导电层120，该导电层120在该引脚102和外部系统之间提供电性连接。该导电层120可连接或固定至该引脚102。该导电层120可直接形成在该引脚底侧108上。
该集成电路封装系统100可包含介电质122，该介电质122保护一部分该引脚102。该介电质122可包含绝缘材料，该绝缘材料包含钝化件、防焊件、树脂、或底胶。
该介电质122可将该引脚102电性隔离于另一个该引脚102。该介电质122可形成围绕该水平脊部114。该介电质122可直接形成在该脊部下侧116上。该介电质122可形成围绕该引脚102的该引脚顶部106。
该介电质122可包含介电质底侧124和相对于该介电质底侧124的介电质顶侧126。该介电质底侧124可在该导电层120上方。
该引脚顶部106可包含该引脚顶侧110。该引脚顶侧110的平面或该脊部上侧118的平面可与该介电质顶侧126的平面共平面。
该引脚102的该引脚底部104可暴露于该介电质122外。该引脚底部104可从该介电质底侧124突出。该引脚底部104可包含该引脚底侧108，该引脚底侧108在该介电质底侧124下方。该导电层120可在该介电质底侧124下方。
该集成电路封装系统100可包含连接层128，该连接层128为一种在半导体装置和该引脚102之间提供电性连接的结构。举例来说，该连接层128可包含重新分配层(RDL)，其在多列铜引脚框架上。
该连接层128可包含外垫130，该外垫130提供至该引脚102的电性连接。该外垫130可包含直接在该引脚顶侧110上的外垫底面132。该外垫130可包含相对于该外垫底面132的外垫顶面134。
该连接层128可包含导电迹线136。该导电迹线136在该外垫130和接触垫之间提供或绕线电性连接。举例来说，该导电迹线136可包含电性连接器，该电性连接器包含重新分配迹线、绕线的预电镀框架(PPF)层、或重新分配层(RDL)。
该导电迹线136可包含迹线底面138，该迹线底面138直接在该介电质顶侧126和一部分该引脚顶侧110上。该迹线底面138可直接在一部分该脊部上侧118上。该导电迹线136可包含相对于该迹线底面138的迹线顶面140。
该连接层128可包含内垫142。该内垫142为一种提供至半导体装置的装设支撑和电性连接的接触垫。该内垫142可连接或固定至该导电迹线136。
该内垫142可包含直接在该介电质顶侧126上的内垫底面144。该内垫142可包含相对于该内垫底面144的内垫顶面146。
该连接层128可包含彼此共平面的该外垫底面132、该迹线底面138、和该内垫底面144的平面。该连接层128可包含彼此共平面的该外垫顶面134、该迹线顶面140、和该内垫顶面146的平面。
该集成电路封装系统100可包含集成电路148，其为一种半导体装置。该集成电路148可包含非作用侧150和相对于该非作用侧150的作用侧152。举例来说，该集成电路148可包含半导体装置，该半导体装置包含覆晶或硅(Si)晶粒。
该集成电路148可包含面对该连接层128的该作用侧152。该集成电路148可装设在该连接层128的该内垫142上方。
该集成电路封装系统100可包含内部连接器154，其为一种电性导体连接器。该内部连接器154可连接或固定至该内垫142和该作用侧152。该内部连接器154可直接在该内垫顶面146上。
该集成电路封装系统100可包含该介电质122，该介电质122将该连接层128电性隔离于另一个该连接层128。该集成电路封装系统100可包含数个该外垫130，其围绕该集成电路148或在该集成电路148的周界外部。该集成电路封装系统100可包含数个该内垫142，在该集成电路148的非作用侧150下方。
该集成电路封装系统100可包含制模化合物166，其覆盖半导体封装件，以密封提供机械或环境保护的半导体装置。该制模化合物166可形成覆盖该介电质122、该连接层128、该集成电路148、和该内部连接器154。该制模化合物166可应用在该介电质顶侧126、该外垫130、该导电迹线136、该内垫142、该集成电路148、和该内部连接器154上方。
该制模化合物166可包含制模底面168。该制模底面168的平面可与该外垫底面132、该迹线底面138、和该内垫底面144的平面共平面。该制模底面168和该内垫底面144可直接在该介电质顶侧126上。
该制模化合物166可包含制模非水平侧170，其为该制模化合物166的水平部分。该制模非水平侧170的平面可与该介电质122的介电质非水平侧172的平面共平面。该介电质非水平侧172为该介电质122的水平部分。
经发现连接至该引脚102和该集成电路148的该连接层128提供简单且具成本效益的制程给多列四方形平面非引脚(QFN)封装件，其具有覆晶，以铜基带蚀刻制程技术作成，从而完成为覆晶装置有效地组构多列四方形平面非引脚(QFN)封装件的需求。
经发现具有固定至该外垫130和该内垫142的该导电迹线136的该连接层128提供一种解决方案，该解决方案没有使用覆晶应用的BT(bismaleimide triazine)薄片，以将覆晶讯号重新分配至四方形平面非引脚(QFN)多列引脚。
经发现该连接层128提供成本降低，这是因为相较于标准覆晶球格数组的较简单的引脚框架架构。
经发现具有被该介电质122覆盖的该水平脊部114的该引脚102改良引脚连锁(interlocking)，从而消除引脚拔出(pullout)。
经不预期地判定固定至该引脚顶侧110的该外垫130提供可靠的连接点，以将该引脚102固定或连接至堆栈装置。
经不预期地认识到被该介电质122保护的连接层128最好用于覆晶装设，从而消除焊锡倒塌(solder collapse)、焊锡蔓延(soldercreep)、或无法对准(misalignment)。
经不预期地确定该介电质122藉由将该连接层128隔离于另一个该连接层128或将该引脚102隔离于另一个该引脚102而改良可靠度，从而消除焊锡蔓延或电性短路。
经不预期地证实该导电层120在该引脚102和外部系统之间提供可靠的电性连接。
经不预期地观察到直接在该引脚102和该介电质122上的该连接层128提供覆晶封装的简单制程流程和封装结构。
经不预期地发现具有减少垫间距的该外垫130和该内垫142以及具有细间距图案化公差的该导电迹线136显著地降低该集成电路148的晶粒尺寸，导致封装件足迹(footprint)的减少。
参考图2，其显示该集成电路封装系统100的下视图。该集成电路封装系统100可包含多列或周界数组的数个该导电层120。该导电层120可形成邻近或在该介电质122的介电质周界202的内部。该导电层120可由该介电质122所围绕。
为了例示的目的，该导电层120是显示为方形形状，虽然了解到该导电层120可具有任何形状。举例来说，该导电层120可为圆形。
参考图3，其显示在电镀制造阶段中该集成电路封装系统100沿着图4的线3-3的剖面图，该剖面图绘示引脚框架制造阶段的电镀阶段。
该集成电路封装系统100可包含引脚框架302，其为一种用于将半导体装置装设及连接于其上的结构。举例来说，该引脚框架302可包含大约0.015mm的引脚框架制程尺寸公差或准确度。
该引脚框架302可形成具有电性导电材料，其包含铜(Cu)或任何其它材料。举例来说，该引脚框架302可包含一种空铜基底、多列铜引脚框架、或绕线预电镀框架(PPF)铜(Cu)引脚框架的结构。
该引脚框架302可包含引脚框架底侧304和相对于该引脚框架底侧304的引脚框架顶侧306。该引脚框架302在该引脚框架底侧304处的一部分可以控制的方式加以移除，以形成部分移除区域308。该部分移除区域308可以包含蚀刻的移除制程来加以形成。
举例来说，该部分移除区域308可以该引脚框架302半蚀刻(half-etched)来加以形成。另举一例，该剖面图将该引脚框架302绘示成具有底部半蚀刻的蚀刻铜框架。
该引脚框架302可包含引脚框架厚度310。该引脚框架302可包含具有非移除厚度312的该部分移除区域308。举例来说，该引脚框架厚度310和该非移除厚度312分别大约为4mm和3mm。
作为一个例子，可移除大约1mm的该引脚框架302，以形成具有大约3mm的该非移除厚度312的该部分移除区域308。作为另一个例子，该非移除厚度312可至少是该引脚框架厚度310的一半。
该集成电路封装系统100可包含直接形成在该引脚框架底侧304上的该导电层120。该导电层120可以电性导电材料形成，该电性导电材料包含金属化材料或金属合金。
该导电层120可形成具有数个层。举例来说，该导电层120可形成具有导电材料，该导电材料包含镍(Ni)、铂(Pd)、金(Au)、任何其它金属化材料、金属合金、或其组合。另举一例，该导电层120可形成具有镍-铂(NiPd)或镍-铂-金(NiPdAu)。
作为一个例子，该导电层120可以电镀制程来加以形成。作为另一个例子，该导电层120可包含选择性预电镀的增层预电镀框架(PPF)的结构。
该集成电路封装系统100可包含直接在该引脚框架顶侧306上的该连接层128。该连接层128可以电性导电材料来加以形成，该电性导电材料包含金属化材料或金属合金。
举例来说，该连接层128可形成具有数个层。另举一例，该连接层128可形成具有导电材料，其包含镍(Ni)、铂(Pd)、金(Au)、或其它金属化材料、金属合金、或其组合。也举一例，该连接层128可形成具有镍-铂(NiPd)或镍-铂-金(NiPdAu)。
作为一个例子，该连接层128可以电镀制程来加以形成。作为另一个例子，该连接层128可包含选择性预电镀的增层预电镀框架(PPF)的结构。
该连接层128可包含该外垫130、该导电迹线136、及该内垫142，该外垫130、该导电迹线136、及该内垫142以共同电性导电材料而形成如单一集成结构。该导电迹线136可电性连接或固定至该外垫130和该内垫142。
参考图4，其显示在该电镀阶段中该集成电路封装系统100的上视图。该上视图绘示数个具有该外垫130、该导电迹线136、和该内垫142的该连接层128。
该集成电路封装系统100可包含数个以数个该导电迹线136连接至数个该内垫142的该外垫130。该内垫142可形成在该引脚框架302的中央部分。该内垫142可形成较该外垫130更靠近该引脚框架302的该中央部分。
该集成电路封装系统100可包含多列该外垫130和多列该内垫142。该集成电路封装系统100可包含多个该外垫130的周界数组。该外垫130可形成邻近或在该引脚框架302的引脚框架周界402的内部。
该导电迹线136可形成具有数个区段404，其为该导线迹线136中接续地形成如单一集成结构的区段。该区段404可在该外垫130与该内垫142之间彼此连接或固定。
该区段404彼此之间可形成在预定的角度，该预定的角度有助于在该外垫130的数组之间隔离距离，以改良至堆栈装置或外部系统级(未显示)的连接。举例来说，该预定的角度可相关于设计纲要或几何限制。
参考图5，其显示在固定阶段中图3的结构。该集成电路封装系统100可包含装设在该连接层128上方的该集成电路148，该集成电路148可包含面对该连接层128的该作用侧152。
该集成电路封装系统100可包含连接或固定至该内垫142及该作用侧152的该内部连接器154，该内部连接器154可直接在该内垫142上。
为了例示的目的，该内部连接器154是显示为导电凸块，虽然了解到该内部连接器154可包含任何其它电性导体连接器。举例来说，该内部连接器154可包含导电膏。也举一例，该内部连接器154可形成具有导电材料，其包含焊锡、金属、或金属化合金。
参考图6，其显示在该制模阶段中图5的结构。该集成电路封装系统100可包含制模制程，其包含液态环氧模具或压缩制模。该制模制程也可包含胶带辅助制模(tape assisted molding)，其以粘结胶带涂布于该集成电路148上方并涂布于该引脚框架底侧304上，以支撑并覆盖该部分移除区域308及该引脚框架302中突出、穿透、或沉入至该粘结胶带之一者中的部分。
该制模化合物166可被制模于该引脚框架302、该连接层128、该集成电路148、和该内部连接器154上方。该制模化合物166可形成以覆盖该引脚框架顶侧306、该连接层128、该集成电路148、及该内部连接器154。
经发现该引脚框架302的结构集成度是藉由制模该制模化合物166以较低的封装压力来加以保存，不同于传送制模，其是使用非常高的封装压力，从而防止该部分移除区域308免于在制模期间下弯。
经发现以控制的方法所形成的具有该非移除厚度312的该部分移除区域308改良该引脚框架302的结构集成度，从而在制模期间消除在该部分移除区域308处的弯曲。
参考图7，其显示在移除阶段中图6的结构。该集成电路封装系统100可包含移除制程，其包含在该移除阶段中蚀刻。该移除制程并不影响或移除该连接层128。举例来说，该移除制程可包含使用包含碱金属的化学溶液的铜蚀刻。
图3的该引脚框架302在图3的该引脚框架底侧304处的部分可加以移除，以形成该引脚102并暴露一部分该制模底面168、该迹线底面138、及该内垫底面144。该引脚框架302在该引脚框架底侧304处被移除的部分可包含图3的该部分移除区域308。该引脚102可与另一个该引脚102电性隔离。
该引脚102可形成具有从该引脚非水平侧112水平地突出的该水平脊部114，该水平脊部114可形成在该引脚顶侧110处。
该水平脊部114可包含该脊部下侧116和该脊部下侧116上方的该脊部上侧118。该引脚顶侧110可包含该脊部上侧118。该迹线底面138可直接在一部分该引脚顶侧110上或一部分该脊部上侧118上。
该导电迹线136及该内垫142可被该制模化合物166所保护或埋置。该导电迹线136及该内垫142可在该移除制程期间不受影响或不被移除。了解到该移除制程不会攻击或移除该导电迹线136及该内垫142。
经发现具有该部分移除区域308的该引脚框架302可提供更有效率的底部或背部蚀刻的优点，这是归因于具有底部半蚀刻特征的该引脚框架302，从而有效地控制该移除制程。
现在参考图8，其显示在应用阶段中图7的结构。该集成电路封装系统100可包含应用方法，其包含网印(screen print)、旋转涂布(spin-coat)、分配(dispense)、虹吸作用(capillary action)。
该集成电路封装系统100可包含该介电质122，该介电质122可直接涂布或填充至该迹线底面138、该内垫底面144、和该制模底面168上。该介电质122可保护或隔离该迹线底面138或该内垫底面144。
该介电质122可电性隔离该引脚102及另一个该引脚102。该介电质122可形成围绕该水平脊部114。该介电质122可直接形成在该脊部下侧116上。该介电质122可形成围绕该引脚顶部106。
该引脚顶部106可包含该引脚顶侧110。该引脚顶侧110的平面或该脊部上侧118的平面可与该介电质顶侧126的平面共平面。
该介电质122可包含该介电质底侧124及相对于该介电质底侧124的该介电质顶侧126。该介电质底侧124可在该导电层120上方。
该引脚底部104可从该介电质122暴露。该引脚底部104可从该介电质底侧124突出。该引脚底部104可包含在该介电质底侧124下方的该引脚底侧108。该导电层120可在该介电质底侧124下方。
该集成电路封装系统100可包含封装件切单制程，以产生该集成电路封装系统100的个别单元或封装件。该封装件切单制程可包含机械或光学制程。
该制模化合物166可包含该制模非水平侧170。该制模非水平侧170的平面可与该介电质122的该介电质非水平侧172的平面共平面。
参考图9，其显示本发明的第二实施例中集成电路封装系统900的剖面图。该集成电路封装系统900可以类似于图1的集成电路封装系统100的方式加以形成，除了增加固定件、装置、和连接器，以及图1的该制模化合物的形成。
该集成电路封装系统900可包含具有引脚底部904的引脚902、、引脚顶部906、引脚底侧908、引脚顶侧910、引脚非水平侧912、及水平脊部914，该水平脊部914具有脊部下侧916及脊部上侧918。该引脚902可以类似于图1的引脚102的方式加以形成。
该集成电路封装系统900可包含导电层920及介电质922，该介电质922具有介电质底侧924及介电质顶侧926。该导电层920及该介电质922可分别以类似于图1的该导电层120及图1的该介电质122之方式加以形成。
该集成电路封装系统900可包含连接层928。该连接层928可包含外垫930，该外垫930具有外垫底面932及外垫顶面934。该连接层928可包含导电迹线936，该导电迹线936具有迹线底面938及迹线顶面940。该连接层928可包含内垫942，该内垫942具有内垫底面944及内垫顶面946。该连接层928可以类似于图1的连接层128的方式加以形成。
该集成电路封装系统900可包含基底集成电路948，该基底集成电路948具有基底非作用侧950及基底作用侧952。该集成电路封装系统900可包含基底内部连接器954。该基底集成电路948及该基底内部连接器954可分别以类似于图1的该集成电路148及图1的该内部连接器154的方式加以形成。
该集成电路封装系统900可包含固定层956，其将堆栈集成电路958固定至该基底集成电路948。该堆栈集成电路958为半导体装置。
该堆栈集成电路958可包含堆栈非作用侧960及相对于该堆栈非作用侧960的堆栈作用侧962。该堆栈集成电路958可装设在该基底集成电路948上方。举例来说，该堆栈集成电路958可包含半导体装置，该半导体装置包含打线晶粒或集成电路晶粒。
该堆栈集成电路958可包含面对该基底非作用侧950的该堆栈非作用侧960。该堆栈集成电路958可包含以该固定层956固定至该基底非作用侧950的该堆栈非作用侧960。
为了例示目的，该堆栈集成电路958是显示具有大于该基底集成电路948的宽度的宽度，虽然了解到该堆栈集成电路958及该基底集成电路948的宽度可为任何长度。举例来说，该堆栈集成电路958的宽度可大约等于该基底集成电路948的宽度。该堆栈集成电路958及该基底集成电路948的宽度分别为堆栈集成电路958及该基底集成电路948的水平部分之间的水平距离。
该集成电路封装系统900可包含堆栈内部连接器964，其为电性导体连接器。数个堆栈内部连接器964可连接或固定至该堆栈作用侧962及数个该外垫顶面934。该堆栈内部连接器964可直接在该外垫顶面934上。
该集成电路封装系统900可包含制模化合物966，其覆盖半导体封装件，以密封提供机械及环境保护的半导体装置。该制模化合物966可形成以覆盖该介电质922、该连接层928、该基底集成电路948、该基底内部连接器954、该固定层956、该堆栈集成电路958、及该堆栈内部连接器964。该制模化合物966可施加至该介电质顶侧926、该外垫930、该导电迹线936、该内垫942、该基底集成电路948、该基底内部连接器954、该固定层956、该堆栈集成电路958、及该堆栈内部连接器964上方。
该制模化合物966可包含制模底面968。该制模底面968的平面可与该外垫底面932、该迹线底面938、及该内垫底面944的平面共平面。该制模底面968及该内垫底面944可直接在该介电质顶侧926上。
该制模化合物966可包含制模非水平侧970，其为该制模化合物966的水平部分。该制模非水平侧970的平面可与该介电质922的该介电质非水平侧972的平面共平面。该介电质非水平侧972为该介电质922的水平部分。
经不预期地发现装设于该基底集成电路948上方的该堆栈集成电路958改良装置集成度。
经不预期地判定固定至该外垫顶面934的该堆栈内部连接器964允许该堆栈集成电路958被电性连接至该基底集成电路948及外部系统。
参考图10，其显示本发明的另一实施例中制造该集成电路封装系统100的方法1000的流程图。该方法1000包含：在方块1002中形成引脚，该引脚在引脚顶侧具有水平脊部；在方块1004中形成连接层，该连接层具有直接在该引脚顶侧上的内垫及外垫，该内垫具有内垫底面；在方块1006中将集成电路装设在该内垫上方；在方块1008中将具有制模底面的制模化合物施加至该集成电路、该内垫、及该外垫上方；以及，在方块1010中直接在该制模底面及该内垫底面施加介电质。
因此，经发现本发明的该集成电路封装系统针对具有连接的集成电路封装系统，提供重要及至今未知且未有的解决方案、能力、及功能态样。该产生的方法、制程、设备、装置、产品、及/或系统是直接的、具成本效益的、不复杂的、具高度变化性的、及有效的，可藉由采用已知科技而惊奇且非显而易知地加以实作，并且因此可立刻用来以有效率、经济地方式制造完全兼容于传统制造方法或制程及科技的集成电路封装系统。
本发明的另一个重要态样为其有价值地支持并服务降低成本、简化系统及增加效能等历史潮流。
本发明的这些和其它有价值的态样因此可将该科技的状态进阶至少次一个阶段。
虽然该发明系以一特定的最佳模式而描述，众多替代的、修改的及各种变化，因前述说明而为熟悉此项技艺的人士了解所显而易见的，据此，其系倾向包含所有这类替代的、修改的及各种变化皆于包含的专利范围内，在此提出的所有事项或显示于附图系为范例之说明而非用于限制。

Claims (10)

1.一种制造集成电路封装系统的方法，包含：
形成引脚，该引脚在引脚顶侧具有水平脊部；
直接在该引脚顶侧上形成具有内垫和外垫的连接层，该内垫具有内垫底面；
将集成电路装设至该内垫上方；
在该集成电路、该内垫、及该外垫上方施加具有制模底面的制模化合物；以及
直接在该制模底面及该内垫底面上施加介电质。
2.如权利要求1所述的制造集成电路封装系统的方法，其中，形成该连接层包含直接在该水平脊部上形成具有导电迹线的该连接层。
3.如权利要求1所述的制造集成电路封装系统的方法，其中，形成该连接层包含形成具有固定至该内垫及该外垫的导电迹线的该连接层。
4.如权利要求1所述的制造集成电路封装系统的方法，另包含直接在该引脚的引脚底侧上形成导电层。
5.如权利要求1所述的制造集成电路封装系统的方法，另包含在该集成电路上方装设堆栈集成电路。
6.一种集成电路封装系统，包含：
引脚，其在引脚顶侧具有水平脊部；
连接层，其具有直接在该引脚顶侧上的内垫和外垫，该内垫具有内垫底面；
集成电路，在该内垫上方；
制模化合物，其具有制模底面且在该集成电路、该内垫、及该外垫上方；以及
介电质，其直接在该制模底面及该内垫底面上。
7.如权利要求6所述的集成电路封装系统，其中，该连接层包含直接在该水平脊部上的导电迹线。
8.如权利要求6所述的集成电路封装系统，其中，该连接层包含固定至该内垫及该外垫的导电迹线。
9.如权利要求6所述的集成电路封装系统，另包含直接在该引脚的引脚底侧上的导电层。
10.如权利要求6所述的集成电路封装系统，另包含在该集成电路上方的堆栈集成电路。
CN201110397047.2A 2010-12-06 2011-12-02 具有垫连接的集成电路封装系统及其制造方法 Active CN102569096B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/961,490 2010-12-06
US12/961,490 US8193037B1 (en) 2010-12-06 2010-12-06 Integrated circuit packaging system with pad connection and method of manufacture thereof

Publications (2)

Publication Number Publication Date
CN102569096A true CN102569096A (zh) 2012-07-11
CN102569096B CN102569096B (zh) 2017-03-01

Family

ID=46148021

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110397047.2A Active CN102569096B (zh) 2010-12-06 2011-12-02 具有垫连接的集成电路封装系统及其制造方法

Country Status (4)

Country Link
US (1) US8193037B1 (zh)
CN (1) CN102569096B (zh)
SG (1) SG182057A1 (zh)
TW (1) TWI597789B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106328624A (zh) * 2015-07-01 2017-01-11 艾马克科技公司 制造具有多层囊封的传导基板的半导体封装的方法及结构

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5629969B2 (ja) 2008-09-29 2014-11-26 凸版印刷株式会社 リードフレーム型基板の製造方法と半導体装置の製造方法
US8735224B2 (en) 2011-02-14 2014-05-27 Stats Chippac Ltd. Integrated circuit packaging system with routed circuit lead array and method of manufacture thereof
US8420447B2 (en) * 2011-03-23 2013-04-16 Stats Chippac Ltd. Integrated circuit packaging system with flipchip leadframe and method of manufacture thereof
US8623711B2 (en) 2011-12-15 2014-01-07 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
US8629567B2 (en) 2011-12-15 2014-01-14 Stats Chippac Ltd. Integrated circuit packaging system with contacts and method of manufacture thereof
US9219029B2 (en) * 2011-12-15 2015-12-22 Stats Chippac Ltd. Integrated circuit packaging system with terminals and method of manufacture thereof
CN103474362A (zh) * 2013-08-27 2013-12-25 南通富士通微电子股份有限公司 多排qfn封装结构和制作方法
US9331003B1 (en) 2014-03-28 2016-05-03 Stats Chippac Ltd. Integrated circuit packaging system with pre-molded leadframe and method of manufacture thereof
JP6489615B2 (ja) * 2015-07-31 2019-03-27 大口マテリアル株式会社 半導体素子搭載用基板、半導体装置及びそれらの製造方法
JP6481895B2 (ja) * 2015-12-16 2019-03-13 大口マテリアル株式会社 半導体装置用リードフレーム及びその製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08115989A (ja) * 1994-08-24 1996-05-07 Fujitsu Ltd 半導体装置及びその製造方法
US5656550A (en) 1994-08-24 1997-08-12 Fujitsu Limited Method of producing a semicondutor device having a lead portion with outer connecting terminal
US7049177B1 (en) 2004-01-28 2006-05-23 Asat Ltd. Leadless plastic chip carrier with standoff contacts and die attach pad
US6812552B2 (en) 2002-04-29 2004-11-02 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
TWI236721B (en) 2004-06-29 2005-07-21 Advanced Semiconductor Eng Leadframe for leadless flip-chip package and method for manufacturing the same
US8067825B2 (en) * 2007-09-28 2011-11-29 Stats Chippac Ltd. Integrated circuit package system with multiple die
US7838975B2 (en) 2008-05-27 2010-11-23 Mediatek Inc. Flip-chip package with fan-out WLCSP
US7888181B2 (en) * 2008-09-22 2011-02-15 Stats Chippac, Ltd. Method of forming a wafer level package with RDL interconnection over encapsulant between bump and semiconductor die
US8105915B2 (en) * 2009-06-12 2012-01-31 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure between non-linear portions of conductive layers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106328624A (zh) * 2015-07-01 2017-01-11 艾马克科技公司 制造具有多层囊封的传导基板的半导体封装的方法及结构

Also Published As

Publication number Publication date
US8193037B1 (en) 2012-06-05
CN102569096B (zh) 2017-03-01
TWI597789B (zh) 2017-09-01
TW201232682A (en) 2012-08-01
SG182057A1 (en) 2012-07-30
US20120139121A1 (en) 2012-06-07

Similar Documents

Publication Publication Date Title
CN102569096A (zh) 具有垫连接的集成电路封装系统及其制造方法
CN102543777B (zh) 具有垫片连接的集成电路封装系统及其制造方法
US9305868B2 (en) Manufacturing method of forming an etch-back type semiconductor package with locking anchorages
CN100576524C (zh) 引线框架、半导体封装及其制造方法
US6927479B2 (en) Method of manufacturing a semiconductor package for a die larger than a die pad
US6229205B1 (en) Semiconductor device package having twice-bent tie bar and small die pad
US7193161B1 (en) SiP module with a single sided lid
US8557638B2 (en) Integrated circuit packaging system with pad connection and method of manufacture thereof
US7115445B2 (en) Semiconductor package having reduced thickness
US6525406B1 (en) Semiconductor device having increased moisture path and increased solder joint strength
US8513788B2 (en) Integrated circuit packaging system with pad and method of manufacture thereof
TWI557815B (zh) 具有導線包覆之積體電路封裝系統及其製造方法
US20190067212A1 (en) Package with interlocking leads and manufacturing the same
US8354739B2 (en) Thin semiconductor package and method for manufacturing same
US11139233B2 (en) Cavity wall structure for semiconductor packaging
US10224218B2 (en) Method for fabricating semiconductor package having a multi-layer encapsulated conductive substrate and structure
US7495255B2 (en) Test pads on flash memory cards
US20130154105A1 (en) Integrated circuit packaging system with routable trace and method of manufacture thereof
US20150084171A1 (en) No-lead semiconductor package and method of manufacturing the same
US8138586B2 (en) Integrated circuit package system with multi-planar paddle
KR100997791B1 (ko) 반도체 패키지의 제조 방법
US10763203B1 (en) Conductive trace design for smart card
US8669654B2 (en) Integrated circuit packaging system with die paddle and method of manufacture thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CP01 Change in the name or title of a patent holder

Address after: Singapore City

Patentee after: Stats Chippac Ltd.

Address before: Singapore City

Patentee before: Stats Chippac Ltd.

CP01 Change in the name or title of a patent holder