CN102506618B - Device for testing training missiles - Google Patents
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- CN102506618B CN102506618B CN201110385511.6A CN201110385511A CN102506618B CN 102506618 B CN102506618 B CN 102506618B CN 201110385511 A CN201110385511 A CN 201110385511A CN 102506618 B CN102506618 B CN 102506618B
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Abstract
The invention provides a device for testing training missiles, relating to a device for simulation training, aiming at solving the problems that the traditional full-physical simulation has high training cost, training item is limited, realism degree of full-virtual simulation is low and optimal training effect is difficult to achieve. The device for testing training missiles comprises a first simulation component, a second simulation component, a third simulation component and a fourth simulation component, a missile cable, a missile case and a 1188A interface, wherein the size and shape of the missile case are the same with those of a real guided missile, the first simulation component, the second simulation component, the third simulation component and the fourth simulation component as well as the missile cable are all arranged inside the missile case, the first simulation component, the second simulation component, the third simulation component and the fourth simulation component are mutually connected by virtue of the missile cable (2) to realize data exchange, the 1188A interface is arranged inside the missile case, and a data exchange terminal of the 1188A interface is connected with a 1188A data exchange terminal of the first simulation component. The device for testing training missiles provided by the invention is used for simulation training.
Description
Technical field
The present invention relates to the device of simulation training.
Background technology
At present, following two kinds of modes are mainly used in the simulation training field: one, all-real object emulation, so-called all-real object emulation, be exactly the real equipment that all adopts in training process, this mode can be accomplished very high authenticity, therefore but it is more difficult to produce various malfunctions, train that cost is high, training program is restricted; Two, full virtual emulation, under this mode, adopt the mode of software simulation entirely, carrys out the course of work of analog machine, thereby reach training and operation personnel's purpose.Its advantage is, does not need actual hardware supported, convenient and swift, training flexibly, but owing to being entirely virtual, validity is poor, is difficult to reach the optimum training effect.
Summary of the invention
The objective of the invention is that training cost in order to solve existing all-real object emulation is high, training program is restricted, full virtual emulation validity is poor, is difficult to reach the problem of optimum training effect, and a kind of device of testing dummy round is provided.
The device of test dummy round, it comprises analog component No. one, No. two analog components, No. three analog components, No. four analog components, cable on bullet, shell case and 1188A interface, the size and shape of shell case is identical with real guided missile, an analog component, No. two analog components, No. three analog components, on No. four analog components and bullet, cable all is arranged on the inside of shell case, an analog component, No. two analog components, No. three analog components and No. four analog components interconnect and realize exchanges data by cable on bullet (2), the 1188A interface is arranged on the inside of shell case, the exchanges data end of 1188A interface is connected to the 1188A exchanges data end of an analog component.
The plant bulk of test dummy round of the present invention is consistent with the true bomb of Fig. 2, a plurality of analog component emulation bomb hardware simulated failure; Usually the trainee is unfamiliar with bomb operation principle and the course of work, thereby very easily produces the operate miss damage equipment with the real equipment training; Usually same operation is repeated unavoidable damage equipment or cause equipment performance to descend in training process; Better operator training of the present invention, save training cost simultaneously more.
The accompanying drawing explanation
Fig. 1 is the structural representation of the device of test dummy round, Fig. 2 is the satllite-guided bomb structural representation, the system that Fig. 3 is the dummy round simulation component forms schematic diagram, Fig. 4 is that protocol conversion and read-write control unit form schematic diagram, Fig. 5 is that the GJB289A protocol conversion module forms schematic diagram, Fig. 6 is that the RS422 protocol conversion module forms schematic diagram, and Fig. 7 is that GJB289A analog transceiver unit forms schematic diagram, T+: send the input of data forward; T-: send the data back input, R+: receive the output of data forward, R: receive data back output, A/B+: forward data, A/B-: reverse data.
The specific embodiment
The specific embodiment one: present embodiment is described in conjunction with Fig. 1, the device of the described test dummy round of present embodiment comprises analog component 1-1 No. one, No. two analog component 1-2, No. three analog component 1-3, No. four analog component 1-4, on bullet, cable 2, shell case 3 and 1188A interface 4, the size and shape of shell case (3) is identical with real guided missile, an analog component 1-1, No. two analog component 1-2, No. three analog component 1-3, on No. four analog component 1-4 and bullet, cable 2 all is arranged on the inside of shell case 3, an analog component 1-1, No. two analog component 1-2, No. three analog component 1-3 and No. four analog component 1-4 interconnect and realize exchanges data by cable on bullet 2, 1188A interface 4 is arranged on the inside of shell case 3, the exchanges data end of 1188A interface 4 is connected to the 1188A exchanges data end of an analog component 1-1.
The specific embodiment two: in conjunction with Fig. 3, illustrate that described analog component 1-1 to the four analog component 1-4 internal structure of the specific embodiment one is all identical, each analog component is by Simulation Control unit 110, DSP data/address bus 111, conversion unit of protocol 120, GJB289A analog transceiver unit 130, RS422 analog-driven unit 140, external status input block 150, identification code setting unit 160 and authentication code memory unit 170 form, DSP data/address bus 111 is arranged on 110 inside, Simulation Control unit, exchanges data is realized by DSP data/address bus 111 and conversion unit of protocol 120 in Simulation Control unit 110, the analog transceiver exchanges data end of conversion unit of protocol 120 is connected with the exchanges data end of GJB289A analog transceiver unit 130, the RS422 communication data exchange end of conversion unit of protocol 120 is connected with the exchanges data end of RS422 analog-driven unit 140, the external status exchanges data end of conversion unit of protocol 120 is connected with the exchanges data end of external status input block 150, the identification code data exchange end of conversion unit of protocol 120 is connected with the exchanges data end of identification code setting unit 160, the identification code storage exchanges data end of conversion unit of protocol 120 is connected with the exchanges data end of authentication code memory unit 170.
Described Simulation Control unit 110 adopts high-performance digital signal processor (DSP) TMS320240F2812 of TI company, it is the high-end control DSP in the new TMS320C2000 series of releasing of TI, system clock is up to 150M, there is addressability and the operational capability of 32, have that the speed of service is fast, the peripheral hardware integrated level is high, memory space is large, the A/D conversion speed is fast, the conversion accuracy high, it provides a kind of low cost, high performance solution for Industry Control.This unit mainly passes through operation simulation unit software, thereby completes the simulation to different simulation unit.
The specific embodiment three: present embodiment is described in conjunction with Fig. 4, conversion unit of protocol 120 in the specific embodiment one is by GJB289A protocol conversion module 121, RS422 protocol conversion module 122, external status input identification module 123, identification code module for reading and writing 124 and identification code storage control module 125 form, described GJB289A protocol conversion module 121, RS422 protocol conversion module 122, external status input identification module 123 and identification code module for reading and writing 124 all are articulated on DSP data/address bus 111, the data storage output of identification code module for reading and writing 124 is connected to the data storage input of identification code storage control module 125, the identification code storage exchanges data end of identification code storage control module 125 is connected to the exchanges data end of authentication code memory unit 170, the analog transceiver exchanges data end of GJB289A analog transceiver unit 130 is connected to the analog transceiver exchanges data end of GJB289A protocol conversion module 121, the exchanges data end of RS422 protocol conversion module 122 is connected to the exchanges data end of RS422 analog-driven unit 140, the input of external status input identification module 123 is connected to the output of external status input block 150, the input of identification code module for reading and writing 124 is connected to the output of identification code setting unit 160,
Described GJB289A protocol conversion module 121, when sending data, becomes by the parallel data of Simulation Control unit 110 inputs the serial data format that meets the GJB289A protocol requirement, and data are outputed to GJB289A analog transceiver unit 130; Described GJB289A protocol conversion module 121, when receiving data, becomes the serial data that meets the GJB289A protocol requirement of GJB289A analog transceiver unit 130 into parallel data, waits for reading of Simulation Control unit 110;
Described RS422 protocol conversion module 122, when sending data, is converted to the parallel data of Simulation Control unit 110 inputs the serial code stream that meets the RS422 agreement and outputs to RS422 analog-driven unit 140; When receiving data, the serial data that meets the RS422 protocol requirement of RS422 analog-driven unit 140 is become to parallel data, wait for reading of Simulation Control unit 110;
Described external status input identification module 123 reads the status information in external status input block 150, and result is transferred to Simulation Control unit 110;
Described identification code module for reading and writing 124 reads the information of identification code in identification code setting unit 160, and reading result is sent to identification code storage control module 125;
Described identification code storage control module 125 is converted to the input data that walk abreast to meet I
2the serial data of C agreement, be deposited into I
2in the authentication code memory unit 170 of C interface, while supplying to need, read.
Described conversion unit of protocol 120 is with Verilog programming realization on the Cyclone II of ALTERA company Series FPGA chip, and the logical resource that it is abundant and the flexibility of design have brought many convenience for this invention.
The specific embodiment four: present embodiment is described in conjunction with Fig. 5, GJB289A protocol conversion module 121 in the specific embodiment one adopts FPGA to realize, described GJB289A protocol conversion module 121 is by sending FIFO, Manchester encoder, redundant channel A, dual port RAM, protocol process module, control register, receive FIFO, manchester decoder device and redundant channel B form, the transmission control output end of protocol process module is connected to the transmission control input end that sends FIFO, the reception control output end of protocol process module is connected to the reception control input end that receives FIFO, the serial data output control output end of protocol process module is connected to the serial data output control input end of redundant channel A, the serial data input control output of protocol process module is connected to the serial data input control input of redundant channel B, the data output end of protocol process module is connected to the data input pin of dual port RAM, the data output end of dual port RAM is connected to a data input that sends FIFO, the control input end of control register connects the DSP data/address bus for reception control signal, the control output end of control register is connected to the control signal input of protocol process module, the parallel data input that sends FIFO is connected with the parallel data line in the DSP data/address bus, the parallel data output that sends FIFO is connected to the input of Manchester encoder, the output of Manchester encoder is connected to the data input pin of redundant channel A, the serial output terminal mouth that the output of redundant channel A is GJB289A protocol conversion module 121 is connected with GJB289A analog transceiver unit 130, the serial input port that the data input pin of redundant channel B is GJB289A protocol conversion module 121 is connected with GJB289A analog transceiver unit 130, the data output end of redundant channel B is connected to the data input pin of manchester decoder device, the data output end of manchester decoder device is connected to the data input pin that receives FIFO, the control output end of manchester decoder device is connected to the decoding control input end of protocol process module, the parallel data output that receives FIFO is connected with the parallel data line in the DSP data/address bus.
Wherein the detailed diagram of GJB289A protocol conversion module 121 as shown in Figure 5, when sending, after parallel data to be sent is written to and sends FIFO, under the control of protocol processor, data are through the Synchronization device, become the data format that meets the GJB289A protocol requirement, finally data are become to the bipolarity Synchronization by the GJB289A analog channel and send; When receiving, serial code stream to be received is input to graceful Chester decoder through the GJB289A analog channel, under the control of protocol processor, judge that whether data are effective, and the corresponding flag bit of set, valid data are deposited into and receive FIFO, and produce corresponding the interruption to Simulation Control unit 110.
The specific embodiment five: present embodiment is described in conjunction with Fig. 6, RS422 protocol conversion module 122 in the specific embodiment one adopts FPGA to realize, by sending FIFO, read-write control unit, parallel/serial converting unit, the Configuration of baud rate unit, serial/parallel conversion unit, receiving FIFO and interrupt expansion unit forms, the address bus port of read-write control unit is connected with the DSP data/address bus, the transmission FIFO read-write control output end of read-write control unit connects the read-write control input end that sends FIFO, the reception FIFO read-write control output end of read-write control unit is connected with the read-write control input end that receives FIFO, the baud rate read-write control output end of read-write control unit is connected with the read-write control input end of Configuration of baud rate unit, the interruption read-write control output end of read-write control unit is connected with the read-write control input end of interrupt expansion unit, the parallel data input that sends FIFO is connected with the parallel data line in the DSP data/address bus, the data output end that sends FIFO is connected to the data input pin of parallel/serial converting unit, the parallel-serial conversion control output end that sends FIFO is connected to the control input end of parallel/serial converting unit, the interruption control output end that sends FIFO is connected to the transmission control input end of interrupt expansion unit, the serial data output port that the data output end of parallel/serial converting unit is RS422 protocol conversion module 122 is connected with RS422 analog-driven unit 140, the data input pin of Configuration of baud rate unit connects RS422 protocol conversion module 122, the transmission control output end of Configuration of baud rate unit is connected to the transmission control input end of parallel/serial conversion, the reception control output end of Configuration of baud rate unit is connected to the reception control input end of serial/parallel conversion, the serial data input port that the data input pin of serial/parallel conversion unit is RS422 protocol conversion module 122 is connected with RS422 analog-driven unit 140, the data output end of serial/parallel conversion unit is connected to the data input pin that receives FIFO, the control output end of serial/parallel conversion unit is connected to the serial/parallel conversion and control input of interrupt expansion unit, the data output end that receives FIFO is connected with the parallel data line in the DSP data/address bus, the control output end that receives FIFO is connected to the reception control input end of interrupt expansion unit, the data output end of interrupt expansion unit connects the DSP data/address bus, the interruption application int output of interrupt expansion unit is connected to the DSP data/address bus.
Sendaisle completes the transmission task of data, sendaisle mainly forms by sending FIFO and parallel/serial converting unit, when needs send data, controller reads the full flag bit that sends FIFO, if less than, under the effect of write control signal, the data that needs are sent are written to and send in FIFO, now FIFO non-NULL flag bit set, parallel/serial converting unit is sent read control signal, and reading out data from send FIFO, then according to concrete setting, under tranmitting data register, parallel data is converted into to satisfactory serial code stream output;
Receive path completes the reception of data, when the external series data arrive, serial/parallel conversion unit was used the position in fact of detection signal, if start bit is (being 0) effectively, start to receive data, word structure and the parity check bit of data are tested simultaneously, as mistake appears, the corresponding flag bit of set, otherwise, illustrate that the data that receive are effective, produce write control signal, data bit is deposited into and receives in FIFO, if it is full to receive FIFO, flag bit is expired in set, produce and interrupt to DSP, DSP passes through interrupt handling routine, send read control signal, read the data that receive in FIFO, thereby reception and the transmission of data have been completed,
Read-write has been controlled each RS of communication unit inside has been read and write to control, address decoding is carried out in address to input, choose corresponding register or memory cell in conjunction with outside gating signal, coordinate corresponding read-write, data are write or read;
Configuration of baud rate: baud rate is defined as the data bits of each second transmission, is used for the speed of control data transmission, and the setting of control word is mainly used in the form of regulation transmission data;
Interrupt expansion: because this unit produces a plurality of interrupt signals, and the input of the external interrupt of dsp processor is limited, this module is used for a plurality of interrupting informations are processed, finally produce an external interrupt to DSP, DSP reads detailed interrupting information in interrupt service routine, further judgement produces the event of interrupting again, thereby makes corresponding processing;
The detailed composition of RS422 protocol conversion module 122 as shown in Figure 6, when sending data, when send FIFO less than the time, Simulation Control unit 110 is to sending data writing in FIFO, when its non-NULL, data enter into parallel/serial modular converter, and this module is converted to data serial code stream the output that meets the RS422 agreement; When receiving data, the external series data enter into serial/parallel modular converter, in this module, the data that receive are carried out to the verification of parity check sum word structure, as wrong, the corresponding flag bit of set, if data are effective, this set data effective marker position, and parallel data are deposited in and receive FIFO.Interruption processing module is processed each flag bit, produces and interrupts reading detailed interrupting information to 110，Gai unit, Simulation Control unit, judges concrete interrupt source, then takes appropriate measures.External status input identification module 123 reads the status information in external status input block 150, and result is transferred to Simulation Control unit 110.Identification code module for reading and writing 124 reads the information of identification code in identification code setting unit 160, and reading result is sent to identification code storage control module 125, and this module is converted to the input data that walk abreast to meet I
2the serial data of C agreement, be deposited into I
2in the EEPROM of C interface, power down is not lost, and while supplying to need, reads.
The specific embodiment six: present embodiment is described in conjunction with Fig. 7, GJB289A analog transceiver unit 130 in the specific embodiment one is by the transmission logic unit, the slope control module, the RL unit, comparator, input filter unit and isolating transformer form, the serial data input that two transmitted signal input T+ of transmission logic unit are GJB289A analog transceiver unit 130 with T-is connected with the serial output terminal of GJB289A protocol conversion module 121, the output of transmission logic unit connects the input of slope control module, the output of slope control module is connected to the two ends on the former limit of isolating transformer, the two ends on the former limit of described isolating transformer also are connected with two inputs of input filter unit, the output of input filter unit is connected to the input of comparator, the output of comparator is connected to the input of RL unit, two output R+ of RL unit, the serial data output that R-is GJB289A analog transceiver unit 130 is connected with the serial input terminal of GJB289A protocol conversion module 121, two terminals A/B+ of isolating transformer secondary, the data serial port that A/B-is GJB289A analog transceiver unit 130.
Described GJB289A analog transceiver unit 130, as shown in Figure 7, this unit is divided into two parts to its detailed diagram: transceiver and isolating transformer, and transceiver is comprised of sendaisle and receive path.When signal sends, signal process transmission control unit, slope control module by GJB289A conversion unit of protocol 121, finally by isolating transformer, be coupled to and send on cable; When signal receives, the signal on external cable, through isolating transformer, enters into the input filter unit, and input signal is carried out to filtering, then by comparator, enters into the RL unit, finally outputs to GJB289A conversion unit of protocol 121.
Claims (5)
1. test the device of dummy round, it is characterized in that it comprises an analog component (1-1), No. two analog components (1-2), No. three analog components (1-3), No. four analog components (1-4), cable on bullet (2), shell case (3) and 1188A interface (4), the size and shape of shell case (3) is identical with real guided missile, an analog component (1-1), No. two analog components (1-2), No. three analog components (1-3), on No. four analog components (1-4) and bullet, cable (2) all is arranged on the inside of shell case (3), an analog component (1-1), No. two analog components (1-2), No. three analog components (1-3) and No. four analog components (1-4) interconnect and realize exchanges data by cable on bullet (2), 1188A interface (4) is arranged on the inside of shell case (3), the exchanges data end of 1188A interface (4) is connected to the 1188A exchanges data end of an analog component (1-1),
An analog component (1-1) is all identical to No. four analog components (1-4) internal structure, each analog component is by Simulation Control unit (110), DSP data/address bus (111), conversion unit of protocol (120), GJB289A analog transceiver unit (130), RS422 analog-driven unit (140), external status input block (150), identification code setting unit (160) and authentication code memory unit (170) form, DSP data/address bus (111) is arranged on inside, Simulation Control unit (110), exchanges data is realized by DSP data/address bus (111) and conversion unit of protocol (120) in Simulation Control unit (110), the analog transceiver exchanges data end of conversion unit of protocol (120) is connected with the exchanges data end of GJB289A analog transceiver unit (130), the RS422 communication data exchange end of conversion unit of protocol (120) is connected with the exchanges data end of RS422 analog-driven unit (140), the external status exchanges data end of conversion unit of protocol (120) is connected with the exchanges data end of external status input block (150), the identification code data exchange end of conversion unit of protocol (120) is connected with the exchanges data end of identification code setting unit (160), the identification code storage exchanges data end of conversion unit of protocol (120) is connected with the exchanges data end of authentication code memory unit (170).
2. test according to claim 1 the device of dummy round, it is characterized in that conversion unit of protocol (120) is by GJB289A protocol conversion module (121), RS422 protocol conversion module (122), external status input identification module (123), identification code module for reading and writing (124) and identification code storage control module (125) form, described GJB289A protocol conversion module (121), RS422 protocol conversion module (122), external status input identification module (123) and identification code module for reading and writing (124) all are articulated in (111) on the DSP data/address bus, the data storage output of identification code module for reading and writing (124) is connected to the data storage input of identification code storage control module (125), the identification code storage exchanges data end of identification code storage control module (125) is connected to the exchanges data end of authentication code memory unit (170), the analog transceiver exchanges data end of GJB289A analog transceiver unit (130) is connected to the analog transceiver exchanges data end of GJB289A protocol conversion module (121), the exchanges data end of RS422 protocol conversion module (122) is connected to the exchanges data end of RS422 analog-driven unit (140), the input of external status input identification module 123 is connected to the output of external status input block (150), the input of identification code module for reading and writing (124) is connected to the output of identification code setting unit (160).
3. test according to claim 2 the device of dummy round, it is characterized in that GJB289A protocol conversion module (121) adopts FPGA to realize, described GJB289A protocol conversion module (121) is by sending FIFO, Manchester encoder, redundant channel A, dual port RAM, protocol process module, control register, receive FIFO, manchester decoder device and redundant channel B form, the transmission control output end of protocol process module is connected to the transmission control input end that sends FIFO, the reception control output end of protocol process module is connected to the reception control input end that receives FIFO, the serial data output control output end of protocol process module is connected to the serial data output control input end of redundant channel A, the serial data input control output of protocol process module is connected to the serial data input control input of redundant channel B, the data output end of protocol process module is connected to the data input pin of dual port RAM, the data output end of dual port RAM is connected to a data input that sends FIFO, the control input end of control register connects the DSP data/address bus for reception control signal, the control output end of control register is connected to the control signal input of protocol process module, the parallel data input that sends FIFO is connected with the parallel data line in the DSP data/address bus, the parallel data output that sends FIFO is connected to the input of Manchester encoder, the output of Manchester encoder is connected to the data input pin of redundant channel A, the serial output terminal mouth that the output of redundant channel A is GJB289A protocol conversion module (121) is connected with GJB289A analog transceiver unit (130), the serial input port that the data input pin of redundant channel B is GJB289A protocol conversion module (121) is connected with GJB289A analog transceiver unit (130), the data output end of redundant channel B is connected to the data input pin of manchester decoder device, the data output end of manchester decoder device is connected to the data input pin that receives FIFO, the control output end of manchester decoder device is connected to the decoding control input end of protocol process module, the parallel data output that receives FIFO is connected with the parallel data line in the DSP data/address bus.
4. test according to claim 2 the device of dummy round, it is characterized in that RS422 protocol conversion module (122) adopts FPGA to realize, by sending FIFO, read-write control unit, parallel/serial converting unit, the Configuration of baud rate unit, serial/parallel conversion unit, receiving FIFO and interrupt expansion unit forms, the address bus port of read-write control unit is connected with the DSP data/address bus, the transmission FIFO read-write control output end of read-write control unit connects the read-write control input end that sends FIFO, the reception FIFO read-write control output end of read-write control unit is connected with the read-write control input end that receives FIFO, the baud rate read-write control output end of read-write control unit is connected with the read-write control input end of Configuration of baud rate unit, the interruption read-write control output end of read-write control unit is connected with the read-write control input end of interrupt expansion unit, the parallel data input that sends FIFO is connected with the parallel data line in the DSP data/address bus, the data output end that sends FIFO is connected to the data input pin of parallel/serial converting unit, the parallel-serial conversion control output end that sends FIFO is connected to the control input end of parallel/serial converting unit, the interruption control output end that sends FIFO is connected to the transmission control input end of interrupt expansion unit, the serial data output port that the data output end of parallel/serial converting unit is RS422 protocol conversion module (122) is connected with RS422 analog-driven unit (140), the data input pin of Configuration of baud rate unit connects RS422 analog-driven unit (140), the transmission control output end of Configuration of baud rate unit is connected to the transmission control input end of parallel/serial conversion, the reception control output end of Configuration of baud rate unit is connected to the reception control input end of serial/parallel conversion, the serial data input port that the data input pin of serial/parallel conversion unit is RS422 protocol conversion module (122) is connected with RS422 analog-driven unit (140), the data output end of serial/parallel conversion unit is connected to the data input pin that receives FIFO, the control output end of serial/parallel conversion unit is connected to the serial/parallel conversion and control input of interrupt expansion unit, the data output end that receives FIFO is connected with the parallel data line in the DSP data/address bus, the control output end that receives FIFO is connected to the reception control input end of interrupt expansion unit, the data output end of interrupt expansion unit connects the DSP data/address bus, the interruption application int output of interrupt expansion unit is connected to the DSP data/address bus.
5. test according to claim 3 the device of dummy round, it is characterized in that GJB289A analog transceiver unit (130) is by the transmission logic unit, the slope control module, the RL unit, comparator, input filter unit and isolating transformer form, the serial data input that two transmitted signal input T+ of transmission logic unit are GJB289A analog transceiver unit (130) with T-is connected with the serial output terminal of GJB289A protocol conversion module (121), the output of transmission logic unit connects the input of slope control module, the output of slope control module is connected to the two ends on the former limit of isolating transformer, the two ends on the former limit of described isolating transformer also are connected with two inputs of input filter unit, the output of input filter unit is connected to the input of comparator, the output of comparator is connected to the input of RL unit, two output R+ of RL unit, the serial data output that R-is GJB289A analog transceiver unit (130) is connected with the serial input terminal of GJB289A protocol conversion module (121), two terminals A/B+ of isolating transformer secondary, the data serial port that A/B-is GJB289A analog transceiver unit (130).
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4133265A (en) * | 1975-12-19 | 1979-01-09 | Dynamit Nobel Ag | Training projectile |
| US4589342A (en) * | 1985-02-28 | 1986-05-20 | The United States Of America As Represented By The Secretary Of The Navy | Rocket-powered training missile with impact motor splitting device |
| CN2086405U (en) * | 1991-02-22 | 1991-10-09 | 戴斯馨 | Rocket increase distance simulating training shell |
| US5971275A (en) * | 1996-12-30 | 1999-10-26 | The United States Of America As Represented By The Secretary Of The Navy | System for verifying nuclear warhead prearm/safing signals |
| CN101246651A (en) * | 2008-01-31 | 2008-08-20 | 杭州普维光电技术有限公司 | Dynamic objective radiation characteristic simulating system |
-
2011
- 2011-11-28 CN CN201110385511.6A patent/CN102506618B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4133265A (en) * | 1975-12-19 | 1979-01-09 | Dynamit Nobel Ag | Training projectile |
| US4589342A (en) * | 1985-02-28 | 1986-05-20 | The United States Of America As Represented By The Secretary Of The Navy | Rocket-powered training missile with impact motor splitting device |
| CN2086405U (en) * | 1991-02-22 | 1991-10-09 | 戴斯馨 | Rocket increase distance simulating training shell |
| US5971275A (en) * | 1996-12-30 | 1999-10-26 | The United States Of America As Represented By The Secretary Of The Navy | System for verifying nuclear warhead prearm/safing signals |
| CN101246651A (en) * | 2008-01-31 | 2008-08-20 | 杭州普维光电技术有限公司 | Dynamic objective radiation characteristic simulating system |
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