CN102506618A - Device for testing training missiles - Google Patents
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- CN102506618A CN102506618A CN2011103855116A CN201110385511A CN102506618A CN 102506618 A CN102506618 A CN 102506618A CN 2011103855116 A CN2011103855116 A CN 2011103855116A CN 201110385511 A CN201110385511 A CN 201110385511A CN 102506618 A CN102506618 A CN 102506618A
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Abstract
The invention provides a device for testing training missiles, relating to a device for simulation training, aiming at solving the problems that the traditional full-physical simulation has high training cost, training item is limited, realism degree of full-virtual simulation is low and optimal training effect is difficult to achieve. The device for testing training missiles comprises a first simulation component, a second simulation component, a third simulation component and a fourth simulation component, a missile cable, a missile case and a 1188A interface, wherein the size and shape of the missile case are the same with those of a real guided missile, the first simulation component, the second simulation component, the third simulation component and the fourth simulation component as well as the missile cable are all arranged inside the missile case, the first simulation component, the second simulation component, the third simulation component and the fourth simulation component are mutually connected by virtue of the missile cable (2) to realize data exchange, the 1188A interface is arranged inside the missile case, and a data exchange terminal of the 1188A interface is connected with a 1188A data exchange terminal of the first simulation component. The device for testing training missiles provided by the invention is used for simulation training.
Description
Technical field
The present invention relates to the device of simulation training.
Background technology
At present; Following two kinds of modes are mainly used in the simulation training field: one, all-real object emulation; So-called all-real object emulation is exactly the real equipment that all adopts in the training process, and this mode can be accomplished very high authenticity; Therefore but produce relatively difficulty of various malfunctions, train that cost is high, training program is restricted; Two, full virtual emulation under this mode, adopts the mode of software simulation entirely, comes the course of work of analog machine, thereby reaches training and operation personnel's purpose.Its advantage is, do not need actual hardware supports, convenient and swift, training flexibly, but owing to be virtual entirely, validity is poor, is difficult to reach the optimum training effect.
Summary of the invention
The objective of the invention is high for the training cost that solves existing all-real object emulation, training program is restricted, full virtual emulation validity is poor, is difficult to reach the problem of optimum training effect, and a kind of device of testing dummy round is provided.
The device of test dummy round; It comprises cable, shell case and 1188A interface on analog component, No. two analog components, No. three analog components, No. four analog components, the bullet; The size of shell case is identical with real guided missile with shape; Cable all is arranged on the inside of shell case on analog component, No. two analog components, No. three analog components, No. four analog components and the bullet; An analog component, No. two analog components, No. three analog components and No. four analog components interconnect the realization exchanges data through cable on the bullet (2), and the 1188A interface is arranged on the inside of shell case, and the exchanges data end of 1188A interface is connected the 1188A exchanges data end of an analog component.
The plant bulk of test dummy round of the present invention is consistent with the true bomb of Fig. 2, a plurality of analog component emulation bomb hardware and simulated failure; Usually the trainee is unfamiliar with the bomb operation principle and the course of work, thereby very easily produces the operate miss damage equipment with the real equipment training; Usually same operation is repeated unavoidable damage equipment or cause equipment performance to descend in the training process; Training cost is saved in better operator training of the present invention simultaneously more.
Description of drawings
Fig. 1 is the structural representation of the device of test dummy round; Fig. 2 is the satllite-guided bomb structural representation, and Fig. 3 is that the system of dummy round simulation component forms sketch map, and Fig. 4 is protocol conversion and read-write control unit composition sketch map; Fig. 5 forms sketch map for the GJB289A protocol conversion module; Fig. 6 forms sketch map for the RS422 protocol conversion module, and Fig. 7 is that sketch map is formed, T+ in GJB289A analog transceiver unit: send the input of data forward; T-: send the data back input, R+: receive the output of data forward, R: receive data back output, A/B+: forward data, A/B-: reverse data.
The specific embodiment
The specific embodiment one: combine Fig. 1 that this embodiment is described; The device of the described test dummy round of this embodiment comprises cable 2, shell case 3 and 1188A interface 4 on analog component 1-1, No. two analog component 1-2, No. three analog component 1-3, No. four analog component 1-4, the bullet; The size of shell case (3) is identical with real guided missile with shape; Cable 2 all is arranged on the inside of shell case 3 on analog component 1-1, No. two analog component 1-2, No. three analog component 1-3, No. four analog component 1-4 and the bullet; An analog component 1-1, No. two analog component 1-2, No. three analog component 1-3 and No. four analog component 1-4 interconnect the realization exchanges data through cable on the bullet 2; 1188A interface 4 is arranged on the inside of shell case 3, and the exchanges data end of 1188A interface 4 is connected the 1188A exchanges data end of an analog component 1-1.
The specific embodiment two: combine Fig. 3 to explain that the specific embodiment one said analog component 1-1 to four an analog component 1-4 internal structure is all identical; Each analog component by Simulation Control unit 110, DSP data/address bus 111, conversion unit of protocol 120, GJB289A analog transceiver unit 130, RS422 analog-driven unit 140, external status input block 150, unit 160 is set identification code and authentication code memory unit 170 is formed; DSP data/address bus 111 is arranged on 110 inside, Simulation Control unit; Exchanges data is realized through DSP data/address bus 111 and conversion unit of protocol 120 in Simulation Control unit 110; The analog transceiver exchanges data end of conversion unit of protocol 120 is connected with the exchanges data end of GJB289A analog transceiver unit 130; The RS422 communication data exchange end of conversion unit of protocol 120 is connected with the exchanges data end of RS422 analog-driven unit 140; The external status exchanges data end of conversion unit of protocol 120 is connected with the exchanges data end of external status input block 150; The exchanges data end that the identification code data exchange end and the identification code of conversion unit of protocol 120 is provided with unit 160 is connected, and the identification code storage exchanges data end of conversion unit of protocol 120 is connected with the exchanges data end of authentication code memory unit 170.
Simulation Control unit 110 is used for moving simulation unit software, accomplishes command analysis and execution, adopts TI company's high-performance digital signal processor (DSP) TMS320240F2812; Conversion unit of protocol 120 is used for accomplishing protocol conversion and read-write, realizes with the Verilog Programming with Pascal Language at the Cyclone of ALTERA company II Series FPGA (Field Programmable Gate Array field programmable gate array) chip internal; GJB289A analog transceiver unit 130 is made up of transceiver and isolating transformer; RS422 analog-driven unit 140; Adopt the RS485/RS422 transmitter MAX3041 and the receiver MAX3093 of U.S. letter company; Chip is integrated 4 transmission/receive paths, external status input block 150 comprises that the RT address of GJB289A is provided with, throws in and allow signal, chain signal, cable to insert state and I/O input quantity; Identification code is provided with unit 160 and is toggle switch, and the component identification sign indicating number can be set flexibly; Authentication code memory unit 170 is serial (I
2C) erasablely remove power down and do not lose read-only storage (EEPROM), can carry out permanent storage identification code.
Described Simulation Control unit 110 adopts high-performance digital signal processor (DSP) TMS320240F2812 of TI company; It is that DSP is used in high-end control in the new TMS320C2000 series of releasing of TI; System clock is up to 150M; Have 32 addressability and operational capability, have characteristics such as the speed of service is fast, the peripheral hardware integrated level is high, memory space is big, the A/D conversion speed is fast, conversion accuracy height, it provides a kind of low cost, high performance solution for Industry Control.This unit is mainly through operation simulation unit software, thereby completion is to the simulation of different simulation unit.
The specific embodiment three: combine Fig. 4 that this embodiment is described; Conversion unit of protocol 120 in the specific embodiment one is made up of GJB289A protocol conversion module 121, RS422 protocol conversion module 122, external status input identification module 123, identification code module for reading and writing 124 and identification code storage control module 125; Said GJB289A protocol conversion module 121, RS422 protocol conversion module 122, external status input identification module 123 and identification code module for reading and writing 124 all are articulated on the DSP data/address bus 111; The storage output of identification code module for reading and writing 124 is connected the storage input of identification code storage control module 125; The identification code storage exchanges data end of identification code storage control module 125 is connected the exchanges data end of authentication code memory unit 170; The analog transceiver exchanges data end of GJB289A analog transceiver unit 130 is connected the analog transceiver exchanges data end of GJB289A protocol conversion module 121; The exchanges data end of RS422 protocol conversion module 122 is connected the exchanges data end of RS422 analog-driven unit 140; The input of external status input identification module 123 is connected the output of external status input block 150, and the input of identification code module for reading and writing 124 is connected the output that identification code is provided with unit 160;
Said GJB289A protocol conversion module 121 is when sending data, and the parallel data that Simulation Control unit 110 is imported becomes the serial data format that meets the GJB289A protocol requirement, and data are outputed to GJB289A analog transceiver unit 130; Said GJB289A protocol conversion module 121 becomes the serial data that meets the GJB289A protocol requirement of GJB289A analog transceiver unit 130 into parallel data when receiving data, wait for reading of Simulation Control unit 110;
Said RS422 protocol conversion module 122 is when sending data, and the parallel data that Simulation Control unit 110 is imported converts the serial code stream that meets the RS422 agreement into and outputs to RS422 analog-driven unit 140; When receiving data, the serial data that meets the RS422 protocol requirement of RS422 analog-driven unit 140 is become parallel data, wait for reading of Simulation Control unit 110;
Said external status input identification module 123 reads the status information in the external status input block 150, and with result transmission to Simulation Control unit 110;
Said identification code module for reading and writing 124 reads identification code the information of identification code in the unit 160 is set, and will read the result and be sent to identification code storage control module 125;
The input data transaction that said identification code storage control module 125 will walk abreast is for meeting I
2The serial data of C agreement is deposited into and has I
2In the authentication code memory unit 170 of C interface, supply and demand will the time read.
Described conversion unit of protocol 120 realizes that with the Verilog programming logical resource that it is abundant and the flexibility of design have brought many convenience for this invention on the Cyclone II of ALTERA company Series FPGA chip.
The specific embodiment four: combine Fig. 5 that this embodiment is described; GJB289A protocol conversion module 121 in the specific embodiment one adopts FPGA to realize; Said GJB289A protocol conversion module 121 is formed by sending FIFO, manchester encoder, redundant channel A, dual port RAM, protocol process module, control register, reception FIFO, manchester decoder device and redundant channel B; The transmission control output end of protocol process module is connected the transmission control input end of sending FIFO; The reception control output end of protocol process module is connected the reception control input end that receives FIFO; The serial data output control output end of protocol process module is connected the serial data output control input end of redundant channel A; The serial data input control output end of protocol process module is connected the serial data input control input end of redundant channel B; The data output end of protocol process module is connected the data input pin of dual port RAM; The data output end of dual port RAM is connected a data input that sends FIFO; The control input end of control register connects the DSP data/address bus and is used to receive control signal, and the control output end of control register is connected the control signal input of protocol process module, and the parallel data input of transmission FIFO is connected with the parallel data line in the DSP data/address bus; The parallel data output that sends FIFO is connected the input of manchester encoder; The output of manchester encoder is connected the data input pin of redundant channel A, and the output of redundant channel A is that the serial output terminal mouth of GJB289A protocol conversion module 121 is connected with GJB289A analog transceiver unit 130, and the data input pin of redundant channel B is that the serial input terminal mouth of GJB289A protocol conversion module 121 is connected with GJB289A analog transceiver unit 130; The data output end of redundant channel B is connected the data input pin of manchester decoder device; The data output end of manchester decoder device is connected the data input pin that receives FIFO, and the control output end of manchester decoder device is connected the decoding control input end of protocol process module, and the parallel data output of reception FIFO is connected with the parallel data line in the DSP data/address bus.
Wherein the detailed diagram of GJB289A protocol conversion module 121 is as shown in Figure 5; When sending; After parallel data to be sent was written to and sends FIFO, under the control of protocol processor, data were through graceful Chester encoder; Become the data format that meets the GJB289A protocol requirement, at last data are become the graceful Chester of bipolarity coding through the GJB289A analog channel and send; When receiving; Serial code stream to be received is input to graceful Chester decoder through the GJB289A analog channel; Under the control of protocol processor, whether judgment data is effective, and the set corresponding marker bit; Valid data are deposited into reception FIFO, and Simulation Control unit 110 is interrupted in generation accordingly.
The specific embodiment five: combine Fig. 6 that this embodiment is described; RS422 protocol conversion module 122 in the specific embodiment one adopts FPGA to realize; By transmission FIFO, read-write control unit, parallel/serial converting unit, baud rate unit, serial, reception FIFO and interruption expanding element being set forms; The address bus port of read-write control unit is connected with the DSP data/address bus; The transmission FIFO read-write control output end of read-write control unit connects the read-write control input end of sending FIFO; The reception FIFO read-write control output end of read-write control unit is connected with the read-write control input end that receives FIFO; The baud rate read-write control output end of read-write control unit is connected with the read-write control input end that baud rate is provided with the unit; The interruption read-write control output end of read-write control unit is connected with the read-write control input end of interrupting expanding element; The parallel data input of transmission FIFO is connected with the parallel data line in the DSP data/address bus; The data output end that sends FIFO is connected the data input pin of parallel/serial converting unit; Send FIFO's and go here and there the conversion and control output and be connected the control input end of parallel/serial converting unit, the interruption controls output that sends FIFO is connected the transmission control input end of interrupting expanding element, and the data output end of parallel/serial converting unit is that the serial data output port of RS422 protocol conversion module 122 is connected with RS422 analog-driven unit 140; The data input pin that baud rate is provided with the unit connects RS422 protocol conversion module 122; The transmission control output end that baud rate is provided with the unit is connected the transmission control input end of parallel/serial conversion, and the reception control output end that baud rate is provided with the unit is connected the reception control input end of serial/parallel conversion, and the data input pin of serial is that the serial data input port of RS422 protocol conversion module 122 is connected with RS422 analog-driven unit 140; The data output end of serial is connected the data input pin that receives FIFO; The control output end of serial is connected the serial/parallel conversion and control input that interrupts expanding element, and the data output end of reception FIFO is connected with the parallel data line in the DSP data/address bus, and the control output end that receives FIFO is connected the reception control input end of interrupting expanding element; The data output end that interrupts expanding element connects the DSP data/address bus, and the interruption application int output that interrupts expanding element is connected the DSP data/address bus.
Sendaisle is accomplished the transmission task of data, and sendaisle is mainly formed by sending FIFO and parallel/serial converting unit, when needs send data; Controller reads the full flag bit that sends FIFO, if less than, then under the effect of write control signal; The data that needs are sent are written among the transmission FIFO, FIFO non-NULL flag bit set this moment, and parallel/serial converting unit is sent read control signal; From send FIFO, read data; According to concrete setting, under tranmitting data register, parallel data is converted into satisfactory serial code stream output then;
Receive path is accomplished the reception of data, and when the external series data arrived, serial was used the position in fact of detection signal, if start bit effective (being 0); Then begin to receive data, simultaneously the word structure and the parity check bit of data are tested, as mistake occurs, then set corresponding marker bit; Otherwise, explain that the data that receive are effective, then produce write control signal, data bit is deposited among the reception FIFO; If it is full to receive FIFO, then the full flag bit of set produces and interrupts DSP, and DSP passes through interrupt handling routine; Send read control signal, read the data that receive among the FIFO, thereby accomplished the reception and the transmission of data;
Read-write control is accomplished each RS of communication unit inside is read and write control; Address decoding is carried out in address to input; Choose relevant register or memory cell in conjunction with outside gating signal, cooperate corresponding read-write, data are write or read;
Baud rate is provided with: baud rate is defined as the data bits of transmission each second, is used for the speed of control data transmission, and the setting of control word is mainly used in the form of regulation transmission data;
Interrupt expansion: because this unit produces a plurality of interrupt signals; And the input of the external interrupt of dsp processor is limited; This module is used for a plurality of interrupting informations are handled, and produces an external interrupt at last to DSP, and DSP reads detailed interrupting information in interrupt service routine; Further judge again to produce the incident of interrupting, thereby make corresponding processing;
The detailed composition of RS422 protocol conversion module 122 is as shown in Figure 6; When sending data; When send FIFO less than the time, Simulation Control unit 110 writes data in sending FIFO, when its non-NULL; Data enter into parallel/serial modular converter, and this module is serial code stream and the output that meets the RS422 agreement with data transaction; When receiving data, the external series data enter into serial/parallel modular converter, in this module; The data that receive are carried out the verification of parity check sum word structure; As wrong, then set corresponding marker bit is if data are effective; This set data effective marker position, and parallel data are deposited in receive FIFO.Interruption processing module is handled each flag bit, produces to interrupt Simulation Control unit 110, and this unit reads detailed interrupting information, judges concrete interrupt source, takes appropriate measures then.External status input identification module 123 reads the status information in the external status input block 150, and with result transmission to Simulation Control unit 110.Identification code module for reading and writing 124 reads identification code the information of identification code in the unit 160 is set, and will read the result and be sent to identification code storage control module 125, and the input data transaction that this module will walk abreast is for meeting I
2The serial data of C agreement is deposited into and has I
2Among the EEPROM of C interface, power down is not lost, supply and demand will the time read.
The specific embodiment six: combine Fig. 7 that this embodiment is described; GJB289A analog transceiver unit 130 in the specific embodiment one is made up of transmission logic unit, slope control module, RL unit, comparator, input filter unit and isolating transformer; Two of the transmission logic unit send signal input part T+ and T-is that the serial data input of GJB289A analog transceiver unit 130 is connected with the serial output terminal of GJB289A protocol conversion module 121; The output of transmission logic unit connects the input of slope control module; The output of slope control module is connected to the two ends on the former limit of isolating transformer; The two ends on the former limit of said isolating transformer also are connected with two inputs of input filter unit; The output of input filter unit is connected the input of comparator; The output of comparator is connected the input of RL unit; Two output R+ of RL unit, R-are that the serial data output of GJB289A analog transceiver unit 130 is connected with the serial input terminal of GJB289A protocol conversion module 121, and two terminals A/B+ of isolating transformer secondary, A/B-are the data serial port of GJB289A analog transceiver unit 130.
Described GJB289A analog transceiver unit 130, its detailed diagram is as shown in Figure 7, and this unit is divided into two parts: transceiver and isolating transformer, and transceiver is made up of sendaisle and receive path.When signal sends,,, be coupled to and send on the cable at last through isolating transformer by signal process transmission control unit, the slope control module of GJB289A conversion unit of protocol 121; When signal received, the signal on the external cable entered into the input filter unit through isolating transformer, and input signal is carried out filtering, enters into the RL unit through comparator then, outputs to GJB289A conversion unit of protocol 121 at last.
Claims (6)
1. test the device of dummy round; It is characterized in that it comprises cable (2), shell case (3) and 1188A interface (4) on an analog component (1-1), No. two analog components (1-2), No. three analog components (1-3), No. four analog components (1-4), the bullet; The size of shell case (3) is identical with real guided missile with shape; Cable (2) all is arranged on the inside of shell case (3) on an analog component (1-1), No. two analog components (1-2), No. three analog components (1-3), No. four analog components (1-4) and the bullet; An analog component (1-1), No. two analog components (1-2),, No. three analog components (1-3) and No. four analog components (1-4) interconnect the realization exchanges data through cable on the bullet (2); 1188A interface (4) is arranged on the inside of shell case (3), and the exchanges data end of 1188A interface (4) is connected the 1188A exchanges data end of an analog component (1-1).
2. according to the device of the said test dummy round of claim 1; It is characterized in that an analog component (1-1) to No. four analog components (1-4) internal structure is all identical; Each analog component by Simulation Control unit (110), DSP data/address bus (111), conversion unit of protocol (120), GJB289A analog transceiver unit (130), RS422 analog-driven unit (140), external status input block (150), identification code unit (160) is set and authentication code memory unit (170) is formed; DSP data/address bus (111) is arranged on inside, Simulation Control unit (110); Exchanges data is realized through DSP data/address bus (111) and conversion unit of protocol (120) in Simulation Control unit (110); The analog transceiver exchanges data end of conversion unit of protocol (120) is connected with the exchanges data end of GJB289A analog transceiver unit (130); The RS422 communication data exchange end of conversion unit of protocol (120) is connected with the exchanges data end of RS422 analog-driven unit (140); The external status exchanges data end of conversion unit of protocol (120) is connected with the exchanges data end of external status input block (150); The identification code data exchange end of conversion unit of protocol (120) is connected with the exchanges data end that identification code is provided with unit (160), and the identification code storage exchanges data end of conversion unit of protocol (120) is connected with the exchanges data end of authentication code memory unit (170).
3. according to the device of the said test dummy round of claim 2; It is characterized in that conversion unit of protocol (120) is made up of GJB289A protocol conversion module (121), RS422 protocol conversion module (122), external status input identification module (123), identification code module for reading and writing (124) and identification code storage control module (125); Said GJB289A protocol conversion module (121), RS422 protocol conversion module (122), external status input identification module (123) and identification code module for reading and writing (124) all are articulated in (111) on the DSP data/address bus; The storage output of identification code module for reading and writing (124) is connected the storage input of identification code storage control module (125); The identification code storage exchanges data end of identification code storage control module (125) is connected the exchanges data end of authentication code memory unit (170); The analog transceiver exchanges data end of GJB289A analog transceiver unit (130) is connected the analog transceiver exchanges data end of GJB289A protocol conversion module (121); The exchanges data end of RS422 protocol conversion module (122) is connected the exchanges data end of RS422 analog-driven unit (140); The input of external status input identification module 123 is connected the output of external status input block (150), and the input of identification code module for reading and writing (124) is connected the output that identification code is provided with unit (160).
4. according to the device of the said test dummy round of claim 3; It is characterized in that GJB289A protocol conversion module (121) adopts FPGA to realize; Said GJB289A protocol conversion module (121) is formed by sending FIFO, manchester encoder, redundant channel A, dual port RAM, protocol process module, control register, reception FIFO, manchester decoder device and redundant channel B; The transmission control output end of protocol process module is connected the transmission control input end of sending FIFO; The reception control output end of protocol process module is connected the reception control input end that receives FIFO; The serial data output control output end of protocol process module is connected the serial data output control input end of redundant channel A; The serial data input control output end of protocol process module is connected the serial data input control input end of redundant channel B; The data output end of protocol process module is connected the data input pin of dual port RAM; The data output end of dual port RAM is connected a data input that sends FIFO; The control input end of control register connects the DSP data/address bus and is used to receive control signal, and the control output end of control register is connected the control signal input of protocol process module, and the parallel data input of transmission FIFO is connected with the parallel data line in the DSP data/address bus; The parallel data output that sends FIFO is connected the input of manchester encoder; The output of manchester encoder is connected the data input pin of redundant channel A, and the output of redundant channel A is that the serial output terminal mouth of GJB289A protocol conversion module (121) is connected with GJB289A analog transceiver unit (130), and the data input pin of redundant channel B is that the serial input terminal mouth of GJB289A protocol conversion module (121) is connected with GJB289A analog transceiver unit (130); The data output end of redundant channel B is connected the data input pin of manchester decoder device; The data output end of manchester decoder device is connected the data input pin that receives FIFO, and the control output end of manchester decoder device is connected the decoding control input end of protocol process module, and the parallel data output of reception FIFO is connected with the parallel data line in the DSP data/address bus.
5. according to the device of the said test dummy round of claim 1; It is characterized in that RS422 protocol conversion module (122) adopts FPGA to realize; By transmission FIFO, read-write control unit, parallel/serial converting unit, baud rate unit, serial, reception FIFO and interruption expanding element being set forms; The address bus port of read-write control unit is connected with the DSP data/address bus; The transmission FIFO read-write control output end of read-write control unit connects the read-write control input end of sending FIFO; The reception FIFO read-write control output end of read-write control unit is connected with the read-write control input end that receives FIFO; The baud rate read-write control output end of read-write control unit is connected with the read-write control input end that baud rate is provided with the unit; The interruption read-write control output end of read-write control unit is connected with the read-write control input end of interrupting expanding element; The parallel data input of transmission FIFO is connected with the parallel data line in the DSP data/address bus; The data output end that sends FIFO is connected the data input pin of parallel/serial converting unit; Send FIFO's and go here and there the conversion and control output and be connected the control input end of parallel/serial converting unit, the interruption controls output that sends FIFO is connected the transmission control input end of interrupting expanding element, and the data output end of parallel/serial converting unit is that the serial data output port of RS422 protocol conversion module (122) is connected with RS422 analog-driven unit (140); The data input pin that baud rate is provided with the unit connects RS422 protocol conversion module (122); The transmission control output end that baud rate is provided with the unit is connected the transmission control input end of parallel/serial conversion, and the reception control output end that baud rate is provided with the unit is connected the reception control input end of serial/parallel conversion, and the data input pin of serial is that the serial data input port of RS422 protocol conversion module (122) is connected with RS422 analog-driven unit (140); The data output end of serial is connected the data input pin that receives FIFO; The control output end of serial is connected the serial/parallel conversion and control input that interrupts expanding element, and the data output end of reception FIFO is connected with the parallel data line in the DSP data/address bus, and the control output end that receives FIFO is connected the reception control input end of interrupting expanding element; The data output end that interrupts expanding element connects the DSP data/address bus, and the interruption application int output that interrupts expanding element is connected the DSP data/address bus.
6. according to the device of the said test dummy round of claim 4; It is characterized in that GJB289A analog transceiver unit (130) is made up of transmission logic unit, slope control module, RL unit, comparator, input filter unit and isolating transformer; Two of the transmission logic unit send signal input part T+ and T-is that the serial data input of GJB289A analog transceiver unit (130) is connected with the serial output terminal of GJB289A protocol conversion module (121); The output of transmission logic unit connects the input of slope control module; The output of slope control module is connected to the two ends on the former limit of isolating transformer; The two ends on the former limit of said isolating transformer also are connected with two inputs of input filter unit; The output of input filter unit is connected the input of comparator; The output of comparator is connected the input of RL unit; Two output R+ of RL unit, R-are that the serial data output of GJB289A analog transceiver unit (130) is connected with the serial input terminal of GJB289A protocol conversion module (121), and two terminals A/B+ of isolating transformer secondary, A/B-are the data serial port of GJB289A analog transceiver unit (130).
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| US4133265A (en) * | 1975-12-19 | 1979-01-09 | Dynamit Nobel Ag | Training projectile |
| US4589342A (en) * | 1985-02-28 | 1986-05-20 | The United States Of America As Represented By The Secretary Of The Navy | Rocket-powered training missile with impact motor splitting device |
| CN2086405U (en) * | 1991-02-22 | 1991-10-09 | 戴斯馨 | Rocket increase distance simulating training shell |
| US5971275A (en) * | 1996-12-30 | 1999-10-26 | The United States Of America As Represented By The Secretary Of The Navy | System for verifying nuclear warhead prearm/safing signals |
| CN101246651A (en) * | 2008-01-31 | 2008-08-20 | 杭州普维光电技术有限公司 | Dynamic objective radiation characteristic simulating system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103926846A (en) * | 2014-04-25 | 2014-07-16 | 哈尔滨工业大学 | System for simulating aviation ammunition and generating faults |
| CN103926846B (en) * | 2014-04-25 | 2016-06-22 | 哈尔滨工业大学 | The system that aircraft ammunition simulation generates with fault |
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