CN102479714A - Preparation method of metal oxide semiconductor field-effect transistor - Google Patents

Preparation method of metal oxide semiconductor field-effect transistor Download PDF

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Publication number
CN102479714A
CN102479714A CN2010105645813A CN201010564581A CN102479714A CN 102479714 A CN102479714 A CN 102479714A CN 2010105645813 A CN2010105645813 A CN 2010105645813A CN 201010564581 A CN201010564581 A CN 201010564581A CN 102479714 A CN102479714 A CN 102479714A
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Prior art keywords
region
photoresist layer
layer
tagma
grid region
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CN2010105645813A
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Chinese (zh)
Inventor
阿里耶夫·阿里伽日·马高米道维奇
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CSMC Technologies Corp
Wuxi CSMC Semiconductor Co Ltd
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CSMC Technologies Corp
Wuxi CSMC Semiconductor Co Ltd
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Priority to CN2010105645813A priority Critical patent/CN102479714A/en
Priority to PCT/CN2011/082419 priority patent/WO2012071990A1/en
Priority to JP2013540225A priority patent/JP2014501042A/en
Publication of CN102479714A publication Critical patent/CN102479714A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)

Abstract

The embodiment of the invention discloses a preparation method of a metal oxide semiconductor field-effect transistor. The method comprises the following steps: forming a gate oxide layer and a polysilicon layer on the surface of the epitaxial layer of a semiconductor wafer substrate in turn; coating a photoresist layer, carving gate region patterns in the photoresist layer, performing polysilicon gate etching to form a gate region, wherein the side of the gate region is reduced by a set length after polysilicon gate etching compared with the patterns of the gate region in the photoresist layer; using the photoresist layer as the mask to perform ion implantation and impurity diffusion and form a body region; removing the photoresist layer and the preset gate oxide layer in the source region; and forming a source region in the body region. By adopting the technical scheme provided by the embodiment of the invention, the overlapping area of the body region and gate region of the obtained metal oxide semiconductor field-effect transistor is smaller, thus the input capacitance of the device can be effectively reduced, the dynamic characteristic can be improved and the yield rate can be increased.

Description

The metal oxide semiconductor field effect tube manufacturing approach
Technical field:
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of metal oxide semiconductor field effect tube manufacturing approach.
Background technology:
Develop rapidly along with semiconductor fabrication; In order to reach arithmetic speed faster, bigger memory data output and more function; Semiconductor wafer develops towards higher component density, high integration direction, the requirement of semiconductor device physical structure and manufacturing process is also come high.For example: in the metal oxide semiconductor field effect tube; The size of the lap in its grid region and tagma plays an important role to the size of the input capacitance of this device and source, charge leakage; The size of lap is big more; Its input capacitance is just high more, and dynamic characteristic is just poor more, and then the yields of the MOS type FET that obtains is just low more.
Existing production of semiconductor field-effect tube of metal oxide generally includes following step: on the epi-layer surface of semiconductor wafer substrate, form gate oxide and polysilicon layer successively; Through the coating photoresist layer, steps such as mint-mark grid region graphic structure, polysilicon gate etching, removal photoresist layer form the grid region figure at polysilicon surface in photoresist layer, adopt ion to inject and push away trap, the formation tagma successively with impurity; In the tagma, form the source region; Form dielectric layer; In dielectric layer, form the contact hole that leads to grid region and source region; Carry out the local interlinkage of metal connecting line, accomplish metallization.
As shown in Figure 1; The partial structurtes sketch map of the metal oxide semiconductor field effect tube that obtains for above-mentioned manufacturing process, wherein, there is bigger overlapping area in tagma 102 with grid region 101; Cause this device to have bigger input capacitance; Cause its dynamic characteristic relatively poor, do not meet technological requirement, reduced the yields of metal oxide semiconductor field effect tube.
Summary of the invention
For solving the problems of the technologies described above; The object of the present invention is to provide a kind of metal oxide semiconductor field effect tube manufacturing approach, reduce the overlapping area in tagma and grid region, and then reduce the input capacitance of metal oxide semiconductor field effect tube with realization; Improve its dynamic characteristic, improve its yields.
For realizing above-mentioned purpose, the invention provides following technical scheme:
A kind of MOS type FET manufacturing approach comprises:
On the epi-layer surface of semiconductor wafer, form gate oxide and polysilicon layer successively;
Accomplish the coating photoresist layer successively, in photoresist layer mint-mark grid region figure, polysilicon gate etching, form the technology in grid region, wherein, behind the said polysilicon gate etching, the side, grid region of formation is than the grid region figure indentation preseting length in the photoresist layer;
With the photoresist layer is mask, pushes away trap through ion injection and impurity, forms the tagma;
Remove photoresist layer, and remove the gate oxide of preset active area regions;
In said tagma, form the source region.
Preferably,
Said preseting length is 0.1 micron to 0.5 micron.
Preferably,
Adopt isotropic plasma etching polysilicon gate.
Preferably,
Before forming gate oxide and polysilicon layer, also comprise:
On the epi-layer surface of semiconductor wafer substrate, form protective oxide film;
Form the conductive protection regional graphics through photoetching process at protective oxide film;
The ion injection in the conductive protection zone, impurity push away trap, form well region;
Remove protective oxide film.
Preferably,
After removing protective oxide film, also comprise:
The epi-layer surface of oxide-semiconductor wafer substrates;
Photoetching is formed with the source region figure in the oxide of epi-layer surface;
The oxide of erosion removal epi-layer surface.
Preferably,
After forming the source region, also comprise:
On the epi-layer surface of semiconductor wafer substrate, form dielectric layer;
In dielectric layer, form the contact hole that leads to grid region, source region respectively;
Metallize, obtain grid, source electrode.
Preferably,
After forming the source region, also comprise:
Form drain electrode at the semiconductor wafer substrate back side.
Preferably,
Said epitaxial loayer mixes for the N type, mixes for the P type in said tagma, mixes for the N type in said source region.
Preferably,
The said injection with impurity through ion pushes away trap, and the formation tagma is specially:
With the grid region figure in the photoresist layer is mask, injects the boron ion, and carries out impurity and push away trap, forms the tagma that the P type mixes.
Use the technical scheme that the embodiment of the invention provided, behind polysilicon gate etching, the side, grid region of formation is than the grid region figure indentation preseting length in the photoresist layer; Therefore follow-up tagma forms in the processing procedure, is that grid region figure with photoresist layer is a mask because of its ion injects, and resulting tagma end points can be away from the grid region that forms; And then reduce tagma and grid region overlapping area; Can effectively reduce the input capacitance of device, improve its dynamic characteristic, improve its yields.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the partial structurtes sketch map of metal oxide semiconductor field effect tube of the prior art;
The MOS type FET manufacturing approach flow chart that Fig. 2 provides for embodiment one;
Device architecture sketch map behind the formation grid region that Fig. 3 provides for embodiment one;
Device architecture sketch map behind the formation tagma that Fig. 4 provides for embodiment one;
Device architecture sketch map behind the formation source region that Fig. 5 provides for embodiment one;
Fig. 6 is the spread function sketch map in the tagma and the source region of semiconductor structure cell section under the different indentation length;
The partial structurtes sketch map of the metal oxide semiconductor field effect tube that Fig. 7 provides for embodiment two.
Embodiment
In the metal oxide semiconductor field effect tube of prior art; There are bigger overlapping area in tagma and grid region, cause this device to have bigger input capacitance, cause its dynamic characteristic relatively poor; Do not meet technological requirement, reduced the yields of metal oxide semiconductor field effect tube.
For this reason, the embodiment of the invention provides a kind of MOS type FET manufacturing approach, comprising:
On the epi-layer surface of semiconductor wafer, form gate oxide and polysilicon layer successively;
Accomplish the coating photoresist layer successively, in photoresist layer mint-mark grid region figure, polysilicon gate etching, form the technology in grid region, wherein, the side, grid region that forms behind the said polysilicon gate etching is than the grid region figure indentation preseting length in the photoresist layer; With the photoresist layer is mask, pushes away trap through ion injection and impurity, forms the tagma; Remove photoresist layer, and remove the gate oxide of preset active area regions; In said tagma, form the source region.
In the MOS type FET manufacturing approach that the embodiment of the invention provides; Behind the polysilicon gate etching, the side, grid region of formation is than the grid region figure indentation preseting length in the photoresist layer, and therefore follow-up tagma forms in the processing procedure; Because of its ion injects is that grid region figure with photoresist layer is a mask; So the tagma end points that obtains can be away from the grid region that forms, and then reduces tagma and grid region overlapping area, can effectively reduce the input capacitance of device; Improve its dynamic characteristic, improve its yields.
It more than is the application's core concept; To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention carried out clear, intactly description, obviously; Described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
Embodiment one:
Present embodiment provides a kind of MOS type FET manufacturing approach, referring to shown in Figure 2, is a kind of schematic flow sheet of this method, and this method specifically comprises:
Step S201 forms gate oxide and polysilicon layer successively on the epi-layer surface of semiconductor wafer.
Need to prove; Semiconductor wafer in the present embodiment can comprise semiconductor element; The for example silicon of monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe); The semiconductor structure that also can comprise mixing, for example carborundum, indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide, alloy semiconductor or its combination; It also can be silicon-on-insulator (SOI).In addition, semiconductor wafer can also comprise other material, for example the sandwich construction of epitaxial loayer or buried layer.Though in these several examples of having described the material that can form substrate, any material that can be used as Semiconductor substrate all falls into the spirit and scope of the present invention.Said epitaxial loayer can be the N that on substrate, forms -～N +The type structure, the thickness of epitaxial loayer can confirm that epitaxial loayer can be positioned at the front or the back side of semiconductor wafer according to the concrete application requirements of device.
In this step, form gate oxide concrete grammar can for: adopt thermal oxidation technology on the epi-layer surface of semiconductor wafer substrate, to form gate oxide, the gate oxide in the present embodiment comprises silica at least, and its thickness can be 20～50 dusts.Form polysilicon layer concrete grammar can for: the semiconductor wafer that will comprise gate oxide changes low-pressure chemical vapor phase deposition equipment over to; And in the process cavity of equipment, feed silane; After silane decomposed, polysilicon was deposited on the gate oxide surface, and wherein the thickness of polysilicon layer is about 5000 dusts.After the polysilicon deposit is accomplished, can also carry out the polysilicon doping operation.
Step S202, accomplish the coating photoresist layer successively, in photoresist layer mint-mark grid region figure, polysilicon gate etching, form the technology in grid region, wherein, behind the said polysilicon gate etching, the side, grid region of formation is than the grid region figure indentation preseting length in the photoresist layer.
In photoresist layer, form the grid region figure through behind exposure and the developing procedure, and be mask with the photoresist layer, remove grid region figure outside gate oxide and polysilicon layer through etching process, the formation grid region.
As shown in Figure 3, be to form the partial structurtes sketch map of the semiconductor device behind the grid region, the side, grid region that wherein forms than the grid region figure indentation in the photoresist layer preseting length X.301 is the epitaxial loayer of semiconductor wafer, and concrete can be N -～N +The type structure, 302 is gate oxide, and 303 is the grid region that forms behind the polysilicon gate etching, and 304 is the grid region figure in the photoresist layer.
In this step; Specifically can pass through isotropic plasma etching polysilicon gate; Also can accomplish by wet chemical etching technique technology; Polysilicon layer carries out etching with identical etch rate on all directions, corrosion reaction is also carried out in polysilicon gate side corresponding under the grid region figure in the photoresist layer, makes the width of the width of the polysilicon gate that obtains less than the grid region figure in the photoresist layer; And then after being implemented in polysilicon gate etching, the side, grid region of formation is than the grid region figure indentation preseting length in the photoresist layer.
Step S103 is a mask with the photoresist layer, pushes away trap through ion injection and impurity, forms the tagma.
In the present embodiment, it is emphasized that after step S102 is finished; Directly cleaning and removing is removed photoresist layer, but is mask with the grid region figure in the photoresist layer, carries out ion and injects; And impurity pushes away trap, forms the tagma, and this is and a tangible difference part of the prior art.In the ion implantation process of tagma, the gate oxide of epi-layer surface can be controlled the degree of depth that ion injects.
As shown in Figure 4, be the semiconductor device structure sketch map behind the formation tagma, wherein, 301 is the epitaxial loayer of semiconductor wafer, concrete can be N -～N +The type structure; 302 is gate oxide, and 303 is the grid region that forms behind the polysilicon gate etching, and 304 is the grid region figure in the photoresist layer; 305 is that this step intermediate ion injects the tagma that the back forms, and X is the preseting length of side, grid region than the grid region figure indentation in the photoresist layer.
Behind the polysilicon gate etching; The side, grid region that forms than the grid region figure indentation in the photoresist layer preseting length; The tagma of this step forms in the processing procedure; Because of its ion injects is that grid region figure with photoresist layer is a mask, so the tagma end points that obtains can be away from the grid region that forms, and then can reduce tagma and grid region overlapping area.
Step S104 removes photoresist layer, and removes the gate oxide of preset active area regions.
After forming the tagma; The photoresist layer of the semiconductor wafer surface that coating forms among the step S102 is die on; Need it be removed fully, concrete, can adopt wet-etching technology to remove the photoresist layer of semiconductor wafer surface; Can photoresist layer be placed the chemical solution that removes photoresist, the photoresist dissolving is peeled off.
Step S105 forms the source region in said tagma.
In the tagma that step S103 forms, inject ion, form the source region.Before the source region ion injects, can also the gate oxide etching of preset active area regions be removed.Semiconductor device structure sketch map behind the formation source region as shown in Figure 5, wherein, 301 is the epitaxial loayer of semiconductor wafer, concrete can be N -～N +The type structure, 302 is gate oxide, 303 is the grid region that forms behind the polysilicon gate etching; 304 is the grid region figure in the photoresist layer, and 305 is the tagma, and 306 is the source region; A is grid region and the regional length of source region coincidence in the prior art, and B is the length in grid region among the present invention and coincidence zone, source region, and X is that the present invention contrasts the length that overlaps the zone that can reduce with prior art; K is the end points of tagma groove among the present invention, the K of dashed region 1Be the end points of tagma groove in the prior art, position that K is ordered and ion concentration have determined the size of this device threshold voltage.
In the present embodiment, the type of device is depended on than the setting of the grid region figure indentation length in the photoresist layer in the side, grid region of formation, and its upper limit depends on the threshold voltage of producing required acquisition, and lower limit can be by the precision decision of producing and measuring.
As shown in Figure 6; Be the tagma of semiconductor structure cell section under the different indentation length and the spread function sketch map in source region; Wherein, Dotted line is indentation length that the embodiment of the invention the provides curve when being 0.5 micron, the curve when the actual situation line is 0.5 micron for indentation length, and solid line is for using the curve that the prior art mode obtains.The AB zone is the tilting zone of tagma impurity branch, and the BC zone is the concentration high gradient regions in tagma.
Can know by Fig. 6; Have an appointment 1 micron initial tilt zone of tagma profile of impurities profile; Intersect with the concentration high gradient regions, the centre of the profile tilting zone in tagma receives the attraction in source region, so the right side of the end points K of tagma groove; The tagma tilting section that is about 0.5 micron is arranged, and the concentration of the tagma impurity of the end points of groove has directly determined the threshold voltage of metal oxide semiconductor field effect tube in the tagma.
The polysilicon grid region has caused under the constant situation of source region impurity profile than the indentation of photoresist figure distance; Tagma Impurity Distribution section is away from the grid region, and in this case, tagma groove end points is along with the tagma impurity profile moves; When being 0.5 micron, K shifts to the tilting zone end; When greater than 0.5 micron, then shift to the high gradient regions of tagma impurity, when K is positioned at the high gradient regions of tagma impurity, then can significantly reduce the repeatability of metal oxide semiconductor field effect tube threshold voltage.
From the above, the method that present embodiment provides can make in the metal oxide semiconductor field effect tube of generation, and tagma and grid region overlapping area obviously reduce, and therefore can reduce the input capacitance of device, improves its dynamic characteristic, improves its yields.
Embodiment two:
The difference of present embodiment and embodiment one is, before forming gate oxide and polysilicon layer, can also in semiconductor wafer, be formed for protecting the conductive protection zone of device realization device isolation, and its concrete implementation can comprise:
On the epi-layer surface of semiconductor wafer substrate, form protective oxide film;
Form the conductive protection regional graphics through photoetching process at protective oxide film;
The ion injection in the conductive protection zone, impurity push away trap, form well region;
Remove protective oxide film.
Wherein, protective oxide film can be in the high-temperature technology chamber aerating oxygen, obtain with silicon generation oxidation reaction; Mainly as the oxide screen; In the control ion implantation process, impurity injects the scope and the degree of depth, and the protection epi-layer surface is avoided staiing; Prevent in ion implantation process, to the silicon chip excessive damage.
In addition,, after above-mentioned removal protective oxide film, form before grid oxide layer and the polysilicon layer, can also comprise in order in a semiconductor wafer, to define a plurality of active areas respectively:
The epi-layer surface of oxide-semiconductor wafer substrates;
Photoetching is formed with the source region figure in the oxide of epi-layer surface;
The oxide of erosion removal epi-layer surface.
Can be implemented in a plurality of active areas of formation in the semiconductor wafer through above-mentioned steps, and then form a plurality of semiconductor device.
The method that the embodiment of the invention provided after forming the source region, can also comprise:
On the epi-layer surface of semiconductor wafer substrate, form dielectric layer;
In dielectric layer, form the contact hole that leads to grid region, source region respectively;
Metallize, obtain grid, source electrode.
In addition, after forming the source region, also comprise:
Form drain electrode at the semiconductor wafer substrate back side.
Specifically can be referring to the structural representation of semiconductor wafer shown in Figure 7, wherein, 301 is the epitaxial loayer of semiconductor wafer; 302 is gate oxide, and 303 is the grid region that forms behind the polysilicon gate etching, and 305 is the tagma; 306 is the source region; 309 is the drain region, and 307 is dielectric layer, and 308 for being filled with the through hole of metal material.
Concrete, said epitaxial loayer is to be N -～N +The type doped structure, said source region 306 is to be N +Type mixes, and said tagma 305 can be P -Type mixes, and is formed by following mode: with the grid region figure in the photoresist layer is mask, injects the boron ion, and carries out impurity and push away trap, forms P -The tagma that type mixes.
Use the technical scheme that the embodiment of the invention provided, behind polysilicon gate etching, the side, grid region of formation is than the grid region figure indentation preseting length in the photoresist layer; Therefore follow-up tagma forms in the processing procedure, is that grid region figure with photoresist layer is a mask because of its ion injects, so the tagma end points that obtains can be away from the grid region that forms; And then reduce tagma and grid region overlapping area; Reduce the input capacitance of device, improve its dynamic characteristic, improve its yields.
Each embodiment adopts the mode of going forward one by one to describe in this specification, and what each embodiment stressed all is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be conspicuous concerning those skilled in the art, and defined General Principle can realize under the situation that does not break away from the spirit or scope of the present invention in other embodiments among this paper.Therefore, the present invention will can not be restricted to these embodiment shown in this paper, but will meet and principle disclosed herein and features of novelty the wideest corresponding to scope.

Claims (9)

1. a metal oxide semiconductor field effect tube manufacturing approach is characterized in that, comprising:
On the epi-layer surface of semiconductor wafer, form gate oxide and polysilicon layer successively;
Accomplish the coating photoresist layer successively, in photoresist layer mint-mark grid region figure, polysilicon gate etching, form the technology in grid region, wherein, behind the said polysilicon gate etching, the side, grid region of formation is than the grid region figure indentation preseting length in the photoresist layer;
With the photoresist layer is mask, pushes away trap through ion injection and impurity, forms the tagma;
Remove photoresist layer, and remove the gate oxide of preset active area regions;
In said tagma, form the source region.
2. method according to claim 1 is characterized in that:
Said preseting length is 0.1 micron to 0.5 micron.
3. method according to claim 1 is characterized in that:
Adopt isotropic plasma etching polysilicon gate.
4. according to any described method of claim 1 to 3, it is characterized in that, before forming gate oxide and polysilicon layer, also comprise:
On the epi-layer surface of semiconductor wafer substrate, form protective oxide film;
Form the conductive protection regional graphics through photoetching process at protective oxide film;
The ion injection in the conductive protection zone, impurity push away trap, form well region;
Remove protective oxide film.
5. method according to claim 4 is characterized in that, after removing protective oxide film, also comprises:
The epi-layer surface of oxide-semiconductor wafer substrates;
Photoetching is formed with the source region figure in the oxide of epi-layer surface;
The oxide of erosion removal epi-layer surface.
6. method according to claim 1 is characterized in that, after forming the source region, also comprises:
On the epi-layer surface of semiconductor wafer substrate, form dielectric layer;
In dielectric layer, form the contact hole that leads to grid region, source region respectively;
Metallize, obtain grid, source electrode.
7. method according to claim 1 is characterized in that, after forming the source region, also comprises:
Form drain electrode at the semiconductor wafer substrate back side.
8. method according to claim 1 is characterized in that:
Said epitaxial loayer mixes for the N type, mixes for the P type in said tagma, mixes for the N type in said source region.
9. method according to claim 1 is characterized in that, the said injection with impurity through ion pushes away trap, and the formation tagma is specially:
With the grid region figure in the photoresist layer is mask, injects the boron ion, and carries out impurity and push away trap, forms the tagma that the P type mixes.
CN2010105645813A 2010-11-29 2010-11-29 Preparation method of metal oxide semiconductor field-effect transistor Pending CN102479714A (en)

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CN2010105645813A CN102479714A (en) 2010-11-29 2010-11-29 Preparation method of metal oxide semiconductor field-effect transistor
PCT/CN2011/082419 WO2012071990A1 (en) 2010-11-29 2011-11-18 Method for manufacturing metal-oxide-semiconduct or field-effect transistors
JP2013540225A JP2014501042A (en) 2010-11-29 2011-11-18 Method for manufacturing metal oxide semiconductor field effect transistor

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