CN107256892B - The memory of semiconductor devices, its production method and its making - Google Patents
The memory of semiconductor devices, its production method and its making Download PDFInfo
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- CN107256892B CN107256892B CN201710543550.1A CN201710543550A CN107256892B CN 107256892 B CN107256892 B CN 107256892B CN 201710543550 A CN201710543550 A CN 201710543550A CN 107256892 B CN107256892 B CN 107256892B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 103
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 150000002500 ions Chemical class 0.000 claims abstract description 64
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 57
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 55
- 238000002955 isolation Methods 0.000 claims abstract description 52
- 229920005591 polysilicon Polymers 0.000 claims abstract description 52
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 51
- 230000005611 electricity Effects 0.000 claims abstract description 43
- 238000005530 etching Methods 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000002347 injection Methods 0.000 claims abstract description 10
- 239000007924 injection Substances 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims description 60
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- 230000001154 acute effect Effects 0.000 description 5
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- 229920002120 photoresistant polymer Polymers 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
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- 238000001020 plasma etching Methods 0.000 description 2
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
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- 239000010937 tungsten Substances 0.000 description 2
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- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Abstract
The present invention provides a kind of semiconductor devices, its production method and its memory of making, the production method of the semiconductor devices and includes：One Semiconductor substrate comprising isolation structure and active area is provided, the first groove is formed on the active area, the deposit polycrystalline silicon layer on the first groove, angle-tilt ion injection is carried out to the polysilicon layer along a first direction, ion implanting is avoided in certain positions of the first groove, then polysilicon layer is aoxidized and removes the silicon oxide layer with ion implanting, then the first groove is performed etching using remaining silicon oxide layer as mask, the brilliant pipe U-shaped channel of electricity for being eventually formed in active area is unsymmetric structure, the semiconductor devices being consequently formed has asymmetrical active area channel, so as to fulfill the control to active area electric current, improve junction leaky, improve the electric property of semiconductor devices.
Description
Technical field
The present invention relates to electronic technology fields, and in particular to a kind of semiconductor devices with integrated circuit, its making side
Method and its memory of making.
Background technology
IC designer's manufacture is faster and a kind of mode of smaller integrated circuit is to form integrated electricity by reducing
Separation distance between each element on road.The technique of the density of circuit element on this increase substrate commonly referred to as improves device
Part integrated horizontal.In the technique for designing the integrated circuit with more highly integrated level, improved device trenches are had been developed that
Manufacturing method.
One example of common integrated circuit component is transistor.Transistor is used for many different types of integrated electricity
Road includes memory device and processor.Typical transistor includes being formed in source electrode, the drain and gate at substrate surface.
At present, vertical transistor constructions, the less substrate " effective area " of consumption are had been developed for, and therefore helps to improve device
Integrated horizontal.
The construction of transistor needs to continuously improve junction caused by known drawbacks common, particularly electric field change and leaks electricity
(junction leakage) phenomenon uses this performance for improving final semiconductor devices.
Invention content
It is a primary object of the present invention to provide the memory of a kind of semiconductor devices, its production method and its making, lead to
It crosses and asymmetric active area is set to achieve the purpose that control active area electric current, to improve junction electric leakage (junction leakage)
Phenomenon.
To achieve the above object, the present invention provides a kind of production method of semiconductor devices, including：
Semi-conductive substrate is provided, forms isolation structure on the semiconductor substrate, the isolation structure will it is described partly
Conductor substrate is isolated into multiple active areas；
A mask layer is formed, the mask layer covers the Semiconductor substrate；
One first groove is formed in the active area, and is removed adjacent along a first direction with first groove
The mask layer on the isolation structure, first groove two sides opposite along the first direction are adjacent thereto
The side of the isolation structure overlaps；
Form a polysilicon layer, the polysilicon layer covers the mask layer, the isolation structure and described first recessed
Slot；
Angle-tilt ion injection is carried out to the polysilicon layer along the first direction；
The polysilicon layer is aoxidized, to form silicon oxide layer；
The silicon oxide layer of the removal with ion doping；And
Using the remaining silicon oxide layer and the mask layer as mask, to the active area below first groove
It performs etching to form the second groove, position of second groove in the active area is formed as the brilliant pipe of electricity of unsymmetric structure
U-shaped channel.
Optionally, the active area is in strip, and the width direction of the active area is the first direction, the active area
Length direction for a second direction, the first direction and second direction are mutually perpendicular to；The unsymmetric structure includes described
Electric crystalline substance pipe U-shaped channel is along first direction both sides gradient difference positioned opposite, the brilliant pipe U-shaped channel of the electricity parallel described
Two parallel upward bottom depth of second direction are different and said combination one of them.
Optionally, the step of forming second groove includes：
First time etching is carried out to the active area below first groove using remaining silicon oxide layer as mask；With
And
Using the mask layer as mask to the active area below first groove and with the first groove edge
The adjacent isolation structure carries out second of etching on the first direction, and described second is formed in the active area region
Groove, and the remaining silicon oxide layer is entirely removed.
Optionally, it is formed after second groove, further included：
A gate dielectric layer, a first metal layer and a second metal layer are sequentially formed in second groove.
Optionally, it is formed after the gate dielectric layer, the first metal layer and the second metal layer, further included：
The first metal layer and the gate dielectric layer carve.
Optionally, the first time etching and second of etching are dry etching, and the first time etching is to the oxygen
The etching selection ratio of SiClx layer and the mask layer is more than 5:1.
Correspondingly, the present invention also provides a kind of semiconductor devices, including：
Semi-conductive substrate, be formed in the Semiconductor substrate isolation structure and by the isolation structure carry out every
From multiple active areas；And
An at least groove penetrates through the isolation structure and the active area, and the groove is at the position of the active area Inner
Be formed as the brilliant pipe U-shaped channel of electricity of unsymmetric structure.
Optionally, the active area is in strip, and the width direction of the active area is a first direction, the active area
Length direction is a second direction, and the first direction and second direction are mutually perpendicular to；The unsymmetric structure includes the electricity
Brilliant pipe U-shaped channel is along the first direction both sides gradient positioned opposite is different, the brilliant pipe U-shaped channel of electricity is parallel described the
The two parallel upward bottom depth in two directions are different and said combination one of them.
Optionally, the semiconductor devices further includes：
The gate structure being formed in the groove.
Optionally, the gate structure includes being sequentially located at gate dielectric layer in the groove, the first metal layer and the
Two metal layers, the apical side height of the second metal layer relative to the gate dielectric layer and the first metal layer lateral margin height
It is more nearly the opening of the groove.
Correspondingly, the present invention also provides a kind of memory, including semiconductor devices as described above.
Compared with prior art, the memory of semiconductor devices provided by the invention, its production method and its making has
Following advantageous effect：
1st, the present invention redeposited polysilicon layer after the first groove is formed, ion implanting is carried out to polysilicon layer, due to
It is that angle-tilt ion injection is carried out to the polysilicon layer along the first direction, ion note is avoided in certain positions of the first groove
Enter, then polysilicon layer is aoxidized and remove the silicon oxide layer with ion doping, thus in some positions of the first groove
The place of putting is formed with silicon oxide layer, is then mask to the using remaining silicon oxide layer there is no silicon oxide layer at other positions
One groove performs etching, and position of finally formed second groove in the active area is formed as the brilliant pipe of electricity of unsymmetric structure
U-shaped channel, the semiconductor devices being consequently formed has asymmetrical active area, so as to fulfill the control to active area electric current, with
This improves junction leaky, improves the electric property of semiconductor devices；
2nd, after the present invention sequentially forms gate dielectric layer, the first metal layer and second metal layer in the second groove, also
Including to the gate dielectric layer and the first metal layer carve so that the apical side height of second metal layer is relative to gate dielectric layer
The opening of second groove is highly more nearly with the lateral margin of the first metal layer, so as to further improve semiconductor devices due to
Junction leaky caused by electric field change.
Description of the drawings
The flow chart of the production method for the semiconductor devices that Fig. 1 is provided by one embodiment of the invention；
Fig. 2 is vertical view of the semiconductor devices during its execution step S100 in one embodiment of the invention；
Fig. 3 a-3c are the semiconductor devices in one embodiment of the invention shown in Fig. 2 during it performs step S100
Along AA ', BB ', CC ' directions diagrammatic cross-section；
Fig. 4 a-4c be semiconductor devices in one embodiment of the invention during it performs step S200 along AA ', BB ',
The diagrammatic cross-section in CC ' directions；
Fig. 5 a-5c be semiconductor devices in one embodiment of the invention during it performs step S300 along AA ', BB ',
The diagrammatic cross-section in CC ' directions；
Fig. 6 a-6c be semiconductor devices in one embodiment of the invention during it performs step S400 along AA ', BB ',
The diagrammatic cross-section in CC ' directions；
Fig. 7 is vertical view of the semiconductor devices during its execution step S500 in one embodiment of the invention；
Fig. 8 a- Fig. 8 c are that the semiconductor devices in one embodiment of the invention shown in Fig. 7 performs step S500 processes at it
It is middle along AA ', BB ', CC ' directions diagrammatic cross-section；
Fig. 9 a-9c be semiconductor devices in one embodiment of the invention during it performs step S600 along AA ', BB ',
The diagrammatic cross-section in CC ' directions；
Figure 10 a-10c be semiconductor devices in one embodiment of the invention during it performs step S700 along AA ',
BB ', the diagrammatic cross-section in CC ' directions；
Figure 11 a-11c, Figure 12 a-12c, Figure 13 a-13b are that the semiconductor devices in one embodiment of the invention performs step at it
During rapid S800 along AA ', BB ', CC ' directions diagrammatic cross-section；
The vertical view for the semiconductor devices that Figure 14 is provided by one embodiment of the invention；
Figure 15 is diagrammatic cross-section of the semiconductor devices in one embodiment of the invention shown in Figure 14 in DD ' directions.
Wherein, reference numeral is as follows：
10- Semiconductor substrates；
11- isolation structures；
12- active areas；
13- mask layers；
The patterned photoresist layers of 14-；
The first grooves of 15-；
16- polysilicon layers；The 16 '-polysilicon layer with Doped ions；
17- silicon oxide layers；The 17 '-silicon oxide layer with Doped ions；
The second grooves of 18-；
19- gate dielectric layers；
20- the first metal layers；
21- second metal layers
22- gate structures；
M- wordline forming regions；
N- ion implanted regions；
α-ion implantation angle；
β-ion implantation angle.
Specific embodiment
To make present disclosure more clear and easy to understand, below in conjunction with Figure of description, present disclosure is done into one
Walk explanation.Certainly the invention is not limited to the specific embodiment, and general replacement well known to the skilled artisan in the art is also contained
Lid is within the scope of the present invention.
Secondly, the present invention has carried out detailed statement using schematic diagram, when present example is described in detail, for the ease of saying
Bright, schematic diagram is not partially enlarged in proportion to the general scale, should not be to this restriction as the present invention.
The present invention provides a kind of production method of semiconductor devices, as shown in Figure 1, the manufacturing method of the semiconductor devices
Including：
Step S100 provides semi-conductive substrate, forms isolation structure, the isolation structure on the semiconductor substrate
The Semiconductor substrate is isolated into multiple active areas；
Step S200, forms a mask layer, and the mask layer covers the Semiconductor substrate；
Step S300 forms one first groove in the active area, and removes with first groove along a first party
The mask layer on the adjacent isolation structure upwards, first groove two sides opposite along the first direction
The side of the isolation structure adjacent thereto overlaps；
Step S400, forms a polysilicon layer, and the polysilicon layer covers the mask layer, the isolation structure and institute
State the first groove；
Step S500 carries out angle-tilt ion injection along the first direction to the polysilicon layer；
Step S600 aoxidizes the polysilicon layer, to form silicon oxide layer；
Step S700, the silicon oxide layer of the removal with ion doping；And
Step S800, using the remaining silicon oxide layer and the mask layer as mask, below first groove
The active area performs etching to form the second groove, and position of second groove in the active area is formed as unsymmetrical knot
The brilliant pipe U-shaped channel of electricity of structure.
In the production method of semiconductor devices provided by the invention, the redeposited polysilicon layer after the first groove is formed,
Ion implanting is carried out to polysilicon layer, due to being to carry out angle-tilt ion injection to the polysilicon layer along the first direction,
Certain positions of first groove avoid ion implanting, and then polysilicon layer is aoxidized and removes the oxygen with ion implanting
Thus SiClx layer is formed with silicon oxide layer at some positions of the first groove, there is no silicon oxide layers at other positions, connect
It using remaining silicon oxide layer as mask and the first groove is performed etching, finally formed second groove is in the active area
Position is formed as the brilliant pipe U-shaped channel of electricity of unsymmetric structure, and the semiconductor devices being consequently formed has asymmetrical active area, from
And realize the control to active area electric current, junction leaky is improved with this, improves the electric property of semiconductor devices.
The production method of semiconductor devices provided by the present invention is described in further detail below in conjunction with attached drawing.
Fig. 2 is the semiconductor devices in one embodiment of the invention in its vertical view during performing step S100, Fig. 3 a-
Fig. 3 c be semiconductor devices in one embodiment of the invention shown in Fig. 2 during it performs step S100 along AA ', BB ',
The diagrammatic cross-section in CC ' directions.
In the step s 100, with specific reference to shown in Fig. 2 and Fig. 3 a~3c, semi-conductive substrate 10 is provided, is partly led described
Isolation structure 11 is formed in body substrate 10, the Semiconductor substrate 10 is isolated into multiple active areas 12 by the isolation structure 11,
Multiple 12 array arrangements of active area (for simplicity, three regularly arranged in the Y direction active areas 12 are only illustrated in Fig. 2).
The material of the Semiconductor substrate 10 can be monocrystalline silicon, polysilicon, unformed silicon, silicon Germanium compound or silicon-on-insulator
(SOI) etc. doped region can also or other materials well known by persons skilled in the art, be formed in the Semiconductor substrate 10
Or other semiconductor structures, the present invention do not limit this.The isolation structure 11 is used to implement multiple active areas 12
Electric isolution, the isolation structure 11 be preferably fleet plough groove isolation structure (STI).The material of the isolation structure 11 can be oxygen
It is one or more in the insulating materials such as SiClx and silicon nitride.
The active area 12 can be in strip, and the width direction of the active area 12 is the first direction (in Fig. 2
Y-direction), the length direction of the active area 12 is a second direction (X-direction in such as Fig. 2), the first direction and second
Direction is mutually perpendicular to.The active area 12 has defined size, such as in the present embodiment, the active area 12 is in X-direction
On length for H1, width in the Y direction is H2, and height in z-direction is H3.Multiple 12 rule rows of the active area
Row, and multiple active areas 12 form straight line (not shown) along its longitudinal direction (X-direction).Wherein, X, Y, Z mutually hang down
Directly.
In fig. 2, region M (includes being located on active area 12 in wordline forming region for subsequent wordline forming region
Grid and the conductive layer being integrally formed on isolation structure 11 with grid), the wordline forming region (Y along the first direction
Direction) extend, in the present embodiment, the direction where the length of the active area 12 is vertically arranged with the wordline forming region M
(angle i.e. therebetween is 90 degree).In other embodiments, the direction where the length of the active area 12 and the word
Angle between line forming region M can be less than 90 degree, such as the angle is preferably 18 degree ± 1 degree or 30 degree ± 1 degree.
Fig. 4 a- Fig. 4 c be semiconductor devices in one embodiment of the invention during it performs step S200 along AA ',
BB ', the diagrammatic cross-section in CC ' directions.As shown in Fig. 4 a- Fig. 4 c, in step s 200, one is formed over the semiconductor substrate 10 and is covered
Film layer 13, the mask layer 13 cover the Semiconductor substrate 10, i.e., described mask layer 13 cover the active area 12 with it is described
Isolation structure 11.The mask layer 13 is, for example, insulating materials, and material is preferably silica or silicon nitride, the mask layer 13
Resistivity be 2*1011Ω m~1*1025Ωm；Atomic deposition (Atomic Layer may be used in the mask layer 13
Deposition, ALD) or plasma vapor deposition (Chemical Vapor Deposition) forms or people in the art
Other methods known to member are formed, and the thickness of the mask layer 13 is preferably 3nm~500nm.
Fig. 5 a- Fig. 5 c be semiconductor devices in one embodiment of the invention during it performs step S300 along AA ',
BB ', the diagrammatic cross-section in CC ' directions.As shown in Fig. 5 a- Fig. 5 c, in step S300, one the is formed in each active area 12
One groove 15, and remove and the mask layer on first the groove 15 along the first direction upper adjacent isolation structure
13, the side of first groove 15 two sides opposite in (Y-direction) isolation structure 11 adjacent thereto along the first direction
Face overlaps.The size of i.e. described first groove 15 in the Y direction is equal with the width of the active area 12 in the Y direction, described
The size of first groove 15 in the Y direction is H2, and the size of first groove 15 in the X direction exists less than the active area 12
Size in X-direction, the size of first groove 15 in the X direction are equal to subsequently in the wordline of wordline forming region formation
Width.Removed simultaneously during etching forms first groove 15 in the Y direction adjacent first groove 15 it
Between the isolation structure 11 on mask layer 13, i.e., etching formed the first groove 15 during simultaneously remove the wordline
The mask layer 13 on isolation structure 11 in forming region.Preferably, the specific method of the first groove 15 of etching formation can be
Plasma etching.
Specifically, in step S300, a photoresist layer is coated in the Semiconductor substrate 10 first, then passes through exposure
Light and developing process form patterned photoresist layer 14, the patterned photoresist layer 14 expose it is follow-up it is predetermined formed it is recessed
Mask layer 13 in the region of slot, and the mask layer 13 between the groove for making a reservation for be formed in the Y direction is exposed simultaneously.Then lead to
The mask layer 13 that the removal of over etching technique exposes, the segment thickness then exposed by etching technics removal are partly led
Body substrate 10 forms the first groove 15 in the active area 12, finally removes the patterned photoresist layer 14.Described
(two sides parallel with X-direction are arranged along wordline forming region width direction for one opposite two sides of one groove 15
Two sides) two sides (with X-direction parallel two sides) opposite with the one of the isolation structure 11 overlap, i.e., in Y
On direction, first groove 15 is alternately arranged with the isolation structure 11.
Fig. 6 a- Fig. 6 c be semiconductor devices in one embodiment of the invention during it performs step S400 along AA ',
BB ', the diagrammatic cross-section in CC ' directions.As shown in Fig. 6 a- Fig. 6 c, in step S400, a polysilicon layer 16 is deposited, it is described more
Crystal silicon layer 16 covers the mask layer 13, the bottom of the isolation structure 11 and first groove 15 and side wall.Described
One polysilicon layer 16 may be used the depositing operations such as atomic deposition or plasma vapor deposition and deposit or art technology
Other methods are formed known to personnel, and 16 thickness of the first polysilicon layer is preferably 3nm~500nm.
Fig. 7 is the semiconductor devices in one embodiment of the invention in its vertical view during performing step S500, Fig. 8 a-
Fig. 8 c be semiconductor devices in one embodiment of the invention shown in Fig. 7 during it performs step S500 along AA ', BB ',
The diagrammatic cross-section in CC ' directions.
In step S500, with specific reference to shown in Fig. 7 and Fig. 8 a~8c, along the first direction to the polysilicon layer 16
Carry out angle-tilt ion injection.The direction of the ion implanting is in first direction (Y-direction or wordline forming region length direction)
One acute angle, i.e., between 0 degree and 90 degree, can cause the side in the both sides of first groove 15 along the first direction formed from
Sub- injection region (such as close to the ion implanted region N of C sides in Fig. 7), due to ion implanting direction, in first groove
Opposite side (such as close to C ' sides in Fig. 7) in 15 both sides along the first direction is not injected into ion, so described first
The opposite side of groove 15 does not form ion implanted region.Preferably, the ion of injection can be specifically boron element.Therefore, it is described
Privileged site in first groove 15 reaches the selection of the processing procedures such as oxidation, etching and modifies effect than the surface characteristic of change.
As shown in Fig. 7 and Fig. 8 a, on AA ' directions, polysilicon layer 16, first groove 15 on the mask layer 13
The polysilicon layer 16 of bottom receives ion implanting, forms the polysilicon layer 16 ' with Doped ions, first groove 15
For side wall then without receiving ion implanting, the side wall of first groove 15 is still (i.e. undoped more for original polysilicon layer 16
Crystal silicon layer).
As shown in Fig. 7 and Fig. 8 b, on BB ' directions, the polysilicon layer 16 on the mask layer 13 receives ion implanting, shape
Into the polysilicon layer 16 ' with ion doping, the bottom of first groove 15 and side wall, due to the direction and angle of ion implanting
The reason of spending does not receive ion implanting, is still original polysilicon layer 16 (i.e. undoped polysilicon layer).
As shown in Fig. 7 and Fig. 8 c, on CC ' directions, ion implanting direction is with Y-direction in an acute angle, the isolation structure
The polysilicon layer 16 of side receives ion implanting on 11, forms the polysilicon layer 16 ' with Doped ions, and opposite side does not receive
Ion implanting.Specifically, the side wall and bottom reception ion implanting in the left side (close to C sides in Fig. 7) of first groove 15, shape
Into the polysilicon layer 16 ' with Doped ions, the side wall and bottom on the right side (close to C ' sides in Fig. 7) of first groove 15 do not have
Ion implanting is received, is still polysilicon layer 16 (i.e. undoped polysilicon layer).Wherein, the bottom of first groove 15
The division for receiving ion implanting and the region without receiving ion implanting is come determining, ion note according to the angle of ion implanting
Enter that angle is big, then the region for receiving ion implanting is big, and ion implantation angle is small, then the region for receiving ion implanting is small, with from
The increase of sub- implant angle, the region of the bottom reception ion implanting of first groove 15 increase therewith.The ion implanting
Angle can determine according to actual needs between 0 degree and 90 degree.
It should be noted that the ion implanting can be by both direction, the side of ion implanting direction and Y-direction is in one
Acute angle or the opposite side of ion implanting direction and Y-direction are in an acute angle.As shown in Figure 8 c, it is formed on the left of groove with Y-direction
α angles, ranging from 0 degree to 90 degree of the α angles, alternatively, on the right side of groove with Y-direction composition β angles, the range at the β angles
Also it is 0 degree to 90 degree.The direction of the ion implanting and angle are determined by practical process conditions and demand.
Fig. 9 a- Fig. 9 c be semiconductor devices in one embodiment of the invention during it performs step S600 along AA ',
BB ', the diagrammatic cross-section in CC ' directions.As shown in Fig. 9 a- Fig. 9 c, in step S600, to the polysilicon layer 16 and have
The polysilicon layer 16 ' of ion doping carries out oxidation and forms silicon oxide layer 17 and the silicon oxide layer 17 ' with ion doping, described
The oxidation of polysilicon layer 16 forms silicon oxide layer 17, and the oxidation of polysilicon layer 16 ' with ion doping is formed mixes with ion
Miscellaneous silicon oxide layer 17 ', the silicon oxide layer 17 is from the silicon oxide layer 17 ' with ion doping with different selective etchings
Than.In the present embodiment, it is passed through oxygen in the chamber or ozone carries out oxidation technology, the temperature range of the oxidation technology is 300
~1200 degree of degree, such as the temperature of the oxidation technology is 300 degree, 600 degree, 900 degree or 1200 degree.
Figure 10 a- Figure 10 c be semiconductor devices in one embodiment of the invention during it performs step S700 along AA ',
BB ', the diagrammatic cross-section in CC ' directions.As shown in Figure 10 a- Figure 10 c, in step S700, oxidation of the removal with ion doping
Silicon layer 17 ' forms the figure as shown in Figure 10 a- Figure 10 c.Specifically, wet etching may be used, preferably with hydrofluoric acid (HF)
Solution is etching agent, is more than the etch rate to silicon oxide layer 17 to the etch rate of the silicon oxide layer 17 ' with ion doping,
The final removal silicon oxide layer 17 ' with ion doping, retains the silicon oxide layer 17.
Figure 11 a- Figure 11 c, Figure 12 a- Figure 12 c are that the transistor in one embodiment of the invention performs step S800 processes at it
It is middle along AA ', BB ', CC ' directions diagrammatic cross-section.In step S800, with remaining silicon oxide layer 17 and the mask layer 13
For mask, the active area 12 of 15 lower section of the first groove is performed etching to form the second groove 18, second groove 18 exists
Position in the active area 12 is formed as the brilliant pipe U-shaped channel of electricity of unsymmetric structure.As shown in Figure 11 a- Figure 11 c, first with
The remaining silicon oxide layer 17 carries out first time etching for mask to the active area 12 of 15 lower section of the first groove, due to not
It is different with the remaining silicon oxide layer 17 in region, since the mask of the silicon oxide layer 17 acts on, so the depth of etching active area 12
Degree also differs.Specifically, it please refers to Fig.1 shown in 0a and 11a, on AA ' directions, can directly remove the first groove 15 of etching
The active area 12 of lower section, so its active area 12 etching is relatively deep.It please refers to Fig.1 shown in 0b and 11b, on BB ' directions, due to
First groove, 15 bottom has silicon oxide layer 17, first needs to etch away the silicon oxide layer 17 of 15 bottom of the first groove, then goes etching the
The active area 12 of one groove, 15 lower section, so its active area 12 etching is shallower.It please refers to Fig.1 shown in 0c and 11c, in CC ' sides
Upwards, since 15 bottom of the first groove of left side (close to C sides) does not retain silicon oxide layer 17, and the of right side (close to C ' sides)
One groove, 15 bottom remains with silicon oxide layer 17, so the bottom active area 12 in the left side of the first groove 15 etches more, and right side
Bottom active area 12 etch it is less.Also that is, the second groove 18 that the active area 12 of 15 bottom of the first groove is formed after etching is
The brilliant pipe U-shaped channel of electricity of unsymmetric structure, the unsymmetric structure include the brilliant pipe U-shaped channel of the electricity along the first direction phase
The brilliant pipe U-shaped channel of different to the both sides gradient of arrangement, described electricity is deep in two parallel upward bottoms of the parallel second direction
One of them of degree difference and said combination.Preferably, the unsymmetric structure includes the brilliant pipe U-shaped channel of the electricity described in
The first direction both sides gradient positioned opposite is different and the brilliant pipe U-shaped channel of electricity is in the two flat of the parallel second direction
The upward bottom depth of row is different, so that is be subsequently formed has the brilliant pipe of electricity of unsymmetric structure U-shaped channel in the ratio of slope
It is larger, and there is higher driving current at the deep position of depth, control to active area electric current is realized with this, improves knot
Face leaky.
Specifically, in the first time etches, select the silicon oxide layer 17 that there is high selection to the mask layer 13
Than (e.g. more than 5:1) gas is as etching gas so that etching is to etch based on the silicon oxide layer 17 for the first time, example
As the selection ratio can be with 6:1、7:1、8:1、9:1 or 10:1 or it is well known by persons skilled in the art other selection ratios, it is described
Etching gas is gas based on halogen, such as chlorine (Cl), bromine gas (Br) etc., is formed and existed with plasma.
Then, with the mask layer 13 for mask to the active area 12 of first groove, 15 lower section and with described first
Upper adjacent isolation structure 11 carries out second of etching to groove 15 along the first direction, as shown in Figure 12 a- Figure 12 c.It is carved at second
In erosion, increase the etching gas to the silicon oxide layer 17, preferably carbon tetrafluoride (CF4), fluoroform (CHF3) etc., to
The isolation structure 11 between the active area 12 of the lower section of one groove 15 and first groove 15 in the Y direction carries out the
It is secondarily etched, form the second groove 18.It please be shown in comparison diagram 12a and 12b, and with reference to second in Figure 11 a and Figure 11 b, Figure 12 b
Depth of groove is less than the second depth of groove in Figure 12 a, and depth difference is between 0.01nm and 100nm, i.e., described second groove
18 position in the active area 12 is formed as the brilliant pipe U-shaped channel of electricity of unsymmetric structure, and the brilliant pipe U-shaped channel of electricity is flat
Two parallel upward bottom depth of the row second direction (X-direction) are different.It please refers to shown in Figure 12 c, due to second of quarter
The isolation structure 11 for protecting no mask layer 13 is lost also to be etched, and due to silicon oxide layer described in Figure 10 c
17 reservation is formed as unsymmetric structure in part of second groove 18 in the active area 12.Specifically, described second is recessed
Position of the slot 18 in the active area 12 is formed as the brilliant pipe U-shaped channel of electricity of unsymmetric structure, and the brilliant pipe U-shaped channel of electricity exists
The first direction (Y-direction) the both sides gradient positioned opposite is different (i.e. different curvature), horizontal direction in the gradient
The difference of (corresponding Y-direction) is between 0.01nm and 100nm, that is, the difference of H4 and H5 are between 0.01nm and 100nm.
It is found that in the bottom of second groove 18, in a second direction in (X-direction), the brilliant pipe U-shaped channel of electricity exists
Two parallel upward bottom depth of the parallel second direction are different, in a first direction in (Y-direction), the brilliant pipe U-shaped of electricity
Channel is different along the first direction both sides gradient positioned opposite, the brilliant pipe U-shaped channel of electricity of unsymmetric structure is consequently formed, most
End form is into the semiconductor devices with asymmetric active area, such as includes the brilliant pipe of electricity of the U-shaped channel of asymmetric channels, so as to
It realizes the control to channel current, improves junction leaky, improve the electric property of semiconductor devices.
As shown in Figure 13 a- Figure 13 b, formed after the second groove 18, the production method of the semiconductor devices is additionally included in
Wordline is formed in the wordline forming region, the wordline is by the grid in the second groove and the conductive layer on isolation structure 11
It forms.The grid is, for example, the combination of gate dielectric layer and grid conducting layer.The conductive layer be, for example, the first metal layer and
The combination of second metal layer.It can be formed in the following way：First, gate dielectric layer 19 is formed over the semiconductor substrate 10, it is described
Gate dielectric layer 19 covers the mask layer 13, the second groove 18 and the isolated area 11, then performs etching technique, only retains
Gate dielectric layer 19 in second groove, the gate dielectric layer 19 cover side wall and the bottom of second groove；Then, it is partly leading
Conductive layer (such as the first metal layer 20 and second metal layer 21) is formed in body substrate 10, the conductive layer covers the mask layer
13rd, then the gate dielectric layer 19 and the isolated area 11 perform etching technique, retain the first metal layer in the second groove
20 and second metal layer 21 as 20 He of the first metal layer in isolated area in grid conducting layer and reserved word line forming region
Second metal layer 21.The first metal layer 20 covers the gate dielectric layer 19, and it is small to form a depth in second groove
In the groove of the second groove, the full groove of the filling of second metal layer 21.The gate dielectric layer 19 can be silica
Etc. traditional gate dielectric material, or high K dielectric material, preferably, gate dielectric layer 19 described in the present embodiment
Material be silica.The gate dielectric layer 19 can pass through the depositing operations shape such as atomic deposition or plasma vapor deposition
Into.The material of the first metal layer 20 and the second metal layer 21 is tungsten, titanium, nickel, aluminium, platinum, titanium nitride, N-type polycrystalline silicon
Or p-type polysilicon, resistivity 2*10-8Ω m~1*102Ωm；The first metal layer 20 is with second metal layer 21 using former
Son deposition or plasma vapor deposit.
Further, plasma etching industrial also can be used to 19 and first metal of the gate dielectric layer in second groove
Layer 20 carve, and returns during carving and is higher than the etching speed to second metal layer 21 using the etch rate to the first metal layer 20
The gas of rate carries out back carving to realize to the gate dielectric layer 19 with the first metal layer 20 so that the top of the second metal layer 21
Face height is highly more nearly second groove 18 relative to the lateral margin of the gate dielectric layer 19 and the first metal layer 20
Opening, height difference H 6 is the 0.01%~15% of the height H3 of the active area 12.The second metal layer 21 with it is described
Gate dielectric layer 19, the first metal layer 20 are compared, and the feature that height protrudes can improve semiconductor devices by electric field change institute
The leakage current of generation further improves the electric property of semiconductor devices.
The vertical view for the semiconductor devices that Figure 14 is provided by one embodiment of the invention, Figure 15 are the present invention shown in Figure 14
Semiconductor devices in one embodiment is in the diagrammatic cross-section in DD ' directions.As shown in Figure 14 and Figure 15, use is of the present invention
The finally formed semiconductor devices of production method of semiconductor devices includes Semiconductor substrate 10, is formed in Semiconductor substrate 10
Isolation structure 11, the Semiconductor substrate 10 is isolated into multiple active areas 12 by the isolation structure 11；It further includes and is formed in
Wordline 22 on active area 12.It should be noted that Figure 14 and Figure 15 be it is simply illustrative go out some of semiconductor devices
Structure, for illustrating technical solutions according to the invention.It can be seen from fig. 15 that in DD ' on direction, in the active area 12
Interior, 12 both sides of active area have the different gradients, i.e., described active area 12 two sides positioned opposite on DD ' directions
The gradient it is different, the semiconductor devices with asymmetric active area is consequently formed, so as to fulfill to semiconductor devices interior raceway groove electricity
The control of stream achievees the purpose that improve performance of semiconductor device.
And it is seen from figure 14 that the angle between the active area 12 and the wordline 22 is acute angle.And Fig. 2~
Figure 13 is illustrated using the angle as right angle, is for better illustrating the system of semiconductor devices of the present invention
Make method.In the present invention, the angle is not limited fixed, can be determined according to actual process condition or actual demand.Such as
Upper described, the optimized angle of the angle is 18 degree ± 1 degree or 30 degree ± 1 degree.
Correspondingly, the present invention also provides a kind of semiconductor devices, using the production method making of above-mentioned semiconductor device
Into.It please refers to Fig.1 shown in 2a~Figure 12 c and Figure 13 a~Figure 13 b, the semiconductor devices includes：
Semi-conductive substrate 10, the isolation structure 11 being formed in the Semiconductor substrate 10 and by the isolation junction
Multiple active areas 12 that structure 11 is isolated；And
At least one second groove 18 penetrates through the isolation structure 11 and the active area 12, and second groove 18 is in institute
The position for stating 12 Inner of active area is formed as the brilliant pipe U-shaped channel of electricity of unsymmetric structure.
The active area 12 is in strip, and the width direction of the active area 12 is a first direction (i.e. Y-direction), described to have
The length direction of source region 12 is a second direction (i.e. X-direction), and the first direction and second direction are mutually perpendicular to；It is described non-right
Structure is claimed to include the brilliant pipe U-shaped channel of the electricity along first direction both sides gradient difference positioned opposite, the brilliant pipe U-shaped of the electricity
Channel two parallel upward bottom depth of the parallel second direction are different and said combination one of them.In this reality
It applies in example, the unsymmetric structure includes the brilliant pipe U-shaped channel of electricity along the first direction both sides gradient positioned opposite not
The same and described brilliant pipe U-shaped channel of electricity is different in two parallel upward bottom depth of the parallel second direction.
Specifically, it please refers to Fig.1 shown in 2a and Figure 12 b, in a first direction (i.e. in Y-direction), in second groove
18 bottoms, the brilliant pipe U-shaped channel of the electricity both sides gradient positioned opposite is different, and the difference of horizontal distance is (in Y in the gradient
Difference on direction, such as the H4 and H5 in figure) between 0.01nm and 100nm.It please refers to Fig.1 shown in 2c, in second direction side
Upwards (i.e. in X-direction), in the bottom of second groove 18, the depth of the brilliant pipe U-shaped channel side of electricity is higher than opposite side
Depth, i.e., the described brilliant pipe U-shaped channel of electricity is different in two parallel upward bottom depth of the parallel second direction, and height
Difference is between 0.01nm and 100nm.
It please refers to Fig.1 shown in 3a and Figure 13 b, the semiconductor devices further includes：The grid being formed in second groove
Pole structure.The gate structure include being sequentially formed in gate dielectric layer 19 in second groove, the first metal layer 20 and
Second metal layer 21.Meanwhile further include the source electrode for the active area 12 for being formed in gate structure both sides and drain electrode (not shown).
Wherein, the apical side height of the second metal layer 21 is relative to the lateral margin of the gate dielectric layer 19 and the first metal layer 20 height
Degree is more nearly the opening of second groove 18, and difference in height is the 0.01%~15% of the height H3 of the active area 12.
The material of the gate dielectric layer 19 is preferably silica, and the first metal layer 20 and the material of the second metal layer 21 are
Tungsten, titanium, nickel, aluminium, platinum, titanium nitride, N-type polycrystalline silicon or p-type polysilicon, resistivity 2*10-8Ω m~1*102Ωm。
While formation gate dielectric layer 19, the first metal layer 20 in second groove and second metal layer 21,
Conductive layer is formed on isolation structure 11 (on first direction) between second groove.Grid knot in second groove
Conductive layer composition wordline on structure and isolation structure 11.Direction (second direction) where 12 length of active area with it is described
The angle between direction where the length of wordline is 0 degree to 90 degree, preferably：18 degree ± 1 degree or 30 degree ± 1 degree.
Correspondingly, the present invention also provides a kind of memory, including semiconductor devices as described above.
In conclusion semiconductor devices provided by the invention and preparation method thereof, memory and preparation method thereof, are forming
Redeposited polysilicon layer after first groove, carries out ion implanting, due to being to described along the first direction to polysilicon layer
Polysilicon layer carry out angle-tilt ion injection, avoid ion implanting in certain positions of the first groove, then to polysilicon layer into
Row aoxidizes and removes the silicon oxide layer with ion doping, is thus formed with silicon oxide layer at some positions of the first groove,
There is no silicon oxide layers at other positions, then the first groove are performed etching using remaining silicon oxide layer as mask, finally
Position of the second groove formed in the active area is formed as the brilliant pipe U-shaped channel of electricity of unsymmetric structure, is consequently formed
Semiconductor devices has asymmetrical active area, so as to fulfill the control to active area electric current, improves junction leaky with this,
Improve the electric property of semiconductor devices.
Further, the present invention sequentially forms gate dielectric layer, the first metal layer and second metal layer in the second groove
Later, further include and quarter carried out back to the gate dielectric layer and the first metal layer so that the apical side height of second metal layer relative to
The lateral margin of gate dielectric layer and the first metal layer is highly more nearly the opening of second groove, so as to further improve semiconductor
Device is due to junction leaky caused by electric field change.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (10)
1. a kind of production method of semiconductor devices, which is characterized in that including：
Semi-conductive substrate is provided, forms isolation structure on the semiconductor substrate, the isolation structure is by the semiconductor
Substrate is isolated into multiple active areas；
A mask layer is formed, the mask layer covers the Semiconductor substrate；
In the active area formed one first groove, and remove with first groove it is adjacent along a first direction described in
The mask layer on isolation structure, described in first groove two sides opposite along the first direction are adjacent thereto
The side of isolation structure overlaps；
A polysilicon layer is formed, the polysilicon layer covers the mask layer, the isolation structure and first groove；
Angle-tilt ion injection is carried out to the polysilicon layer along the first direction；
The polysilicon layer is aoxidized, to form silicon oxide layer；
The silicon oxide layer of the removal with ion doping；And
Using the remaining silicon oxide layer and the mask layer as mask, the active area below first groove is carried out
Etching forms the second groove, and second groove is formed as the brilliant pipe U-shaped of electricity of unsymmetric structure at the position of the active area Inner
Channel.
2. the production method of semiconductor devices as described in claim 1, which is characterized in that the active area is in strip, described
The width direction of active area is the first direction, and the length direction of the active area is a second direction, the first direction
It is mutually perpendicular to second direction；It is positioned opposite along the first direction that the unsymmetric structure includes the brilliant pipe U-shaped channel of the electricity
The both sides gradients is different, the brilliant pipe U-shaped channel of electricity the parallel second direction two parallel upward bottom depth it is different,
Or said combination.
3. the production method of semiconductor devices as claimed in claim 2, which is characterized in that the step of forming second groove
Including：
First time etching is carried out to the active area below first groove using the remaining silicon oxide layer as mask；With
And
Using the mask layer as mask to the active area below first groove and with first groove along described in
The adjacent isolation structure carries out second of etching on first direction, and it is recessed that described second is formed in the active area region
Slot, and the remaining silicon oxide layer is entirely removed.
4. the production method of semiconductor devices as claimed in claim 3, which is characterized in that it is formed after second groove,
It further includes：
A gate dielectric layer, a first metal layer and a second metal layer are sequentially formed in second groove.
5. the production method of semiconductor devices as claimed in claim 4, which is characterized in that form the gate dielectric layer, described
After the first metal layer and the second metal layer, further include：
The first metal layer and the gate dielectric layer carve.
6. the production method of semiconductor devices as claimed in claim 3, which is characterized in that the first time etching and second
Etching is dry etching, and the first time etching is more than 5 to the etching selection ratio of the silicon oxide layer and the mask layer:1.
7. a kind of semiconductor devices, which is characterized in that including：
Semi-conductive substrate is formed with isolation structure in the Semiconductor substrate and is isolated by the isolation structure
Multiple active areas；And
An at least groove, penetrates through the isolation structure and the active area, and the groove is formed at the position of the active area Inner
The brilliant pipe U-shaped channel of electricity for unsymmetric structure；
Wherein, the active area is in strip, and the width direction of the active area is first direction, the length direction of the active area
For a second direction, the first direction and second direction are mutually perpendicular to, and the unsymmetric structure includes the brilliant pipe U-shaped of the electricity and leads to
Road is along first direction both sides gradient difference positioned opposite, the brilliant pipe U-shaped channel of the electricity in the parallel second direction
Two parallel upward bottom depth differences or said combination.
8. semiconductor devices as claimed in claim 7, which is characterized in that the semiconductor devices further includes：
The gate structure being formed in the groove.
9. semiconductor devices as claimed in claim 8, which is characterized in that the gate structure includes being sequentially located at the groove
Interior gate dielectric layer, the first metal layer and second metal layer, the apical side height of the second metal layer are situated between relative to the grid
The lateral margin of matter layer and the first metal layer is highly more nearly the opening of the groove.
10. a kind of memory, which is characterized in that including semiconductor devices as claimed in claim 7.
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| CN101154660A (en) * | 2006-09-30 | 2008-04-02 | 海力士半导体有限公司 | Semiconductor device for preventing reciprocal influence between neighboring gates and method for manufacturing the same |
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