CN102468301B - 半导体元件结构 - Google Patents
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
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- H01L21/76832—Multiple layers
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Abstract
一种半导体元件结构,其包含有基底,其上包含有晶体管;多层接触蚀刻停止层结构,覆盖住晶体管,多层接触蚀刻停止层结构包含有第一蚀刻停止层以及第二蚀刻停止层;以及介电层,设于第二蚀刻停止层上;其中,第一蚀刻停止层与第二蚀刻停止层由不同材料所构成,而第二蚀刻停止层与介电层由不同材料所构成。本发明提供的半导体元件结构中的蚀刻停止层可做为等离子放电层,以转导等离子处理程序中产生的等离子诱发电荷,避免其下的元件遭受到电压差的损害,因此可提升元件的可靠度,且可降低临界电压偏移的数值。
Description
技术领域
本发明属于半导体工艺领域。特别是关于一种具有多层接触蚀刻停止层(contact etch stop layer,CESL)的半导体元件,用以降低半导体工艺对集成电路所产生的电荷伤害。
背景技术
已知,等离子工艺会引起损害,是因为电荷累积造成的结果。在等离子工艺中,浮动导体会收集电荷,因此扮演着如同天线的角色。一般而言,绝缘层,如位于导体基板以及晶圆表面的被绝缘的导电电极(栅极)之间的栅极氧化层,会被存在于表面电极以及基板间的电位差所驱使的电流流经该绝缘层,因而造成损害。已知,在晶圆处理过程中,整体等离子密度与/或电子温度的不均匀性会导致晶圆等级的电位差。
对于厚氧化层元件,因为栅极氧化层厚度较厚,在等离子处理程序中,不会产生明显的隧穿(tunneling)漏电现象,但却使得电荷积聚在栅极电极,使得电位上升,最终造成氧化层或介电堆叠层崩溃故障。在某些情况下,其可能为重度崩溃故障,使得元件完全丧失其效能,在其他情形下,则是在栅极堆叠氧化层中产生潜在的缺陷,因而缩短元件的使用寿命。
在半导体晶圆的集成电路中,为了降低等离子处理程序对集成电路所造成的电荷伤害,可在晶圆制造流程时对晶圆上的切割线(scribelines)进行处理,在集成电路制造流程中,这些切割线可以帮助引导电流,使电流流动至基板或从基板内流出,避免电流流经重要的集成电路元件。然而,上述的现有技术仍未健全。
承上所述,就晶圆良率以及可靠度而言,等离子处理程序诱发损害造成大量的成本损耗,因此有必要发展出一种能解决现有技术缺点以及缺失的改良式半导体元件结构。
发明内容
为了解决现有技术中等离子处理程序对电路造成损害的技术问题,本发明提供一种新的半导体元件结构。
为达到上述目的,根据本发明的较佳实施方式,提供一种半导体元件结构,其包含有基底,其上包含有晶体管;多层接触蚀刻停止层结构,覆盖住晶体管,多层接触蚀刻停止层结构包含有第一蚀刻停止层以及第二蚀刻停止层;以及介电层,设在第二蚀刻停止层上;其中,第一蚀刻停止层与第二蚀刻停止层由不同材料所构成,而第二蚀刻停止层与介电层由不同材料所构成。
根据本发明的另一较佳实施方式,提供一种半导体元件结构,其包含有基底,其上包含有NMOS晶体管以及PMOS晶体管;多层接触蚀刻停止层结构,覆盖住NMOS晶体管及PMOS晶体管,多层接触蚀刻停止层结构包含有第一蚀刻停止层以及第二蚀刻停止层;以及介电层,设于第二蚀刻停止层上;其中,第一蚀刻停止层与第二蚀刻停止层由不同材料所构成,而第二蚀刻停止层与介电层由不同材料所构成。
本发明提供的半导体元件结构中的蚀刻停止层可做为等离子放电层,以转导等离子处理程序中产生的等离子诱发电荷,避免其下的元件遭受到电压差的损害,因此可提升元件的可靠度,且可降低临界电压偏移的数值。
附图说明
图1至图5所描绘的是根据本发明较佳实施方式制备的具有多层接触蚀刻停止层的改良式半导体元件的方法剖面示意图。
具体实施方式
在说明书及权利要求书当中使用了某些词汇来称呼特定的元件。本领域的技术人员应可理解,硬件制造商可能会用不同的名词来称呼同一个元件。本说明书及权利要求书并不以名称的差异来作为区分元件的方式,而是以元件在功能上的差异来作为区分的准则。在通篇说明书及权利要求书当中所提及的“包含”是开放式的用语,故应解释成“包含但不限定于”。此外,“耦接”一词在此是包含任何直接及间接的电气连接手段。因此,若文中描述第一装置耦接于第二装置,则代表第一装置可直接电气连接于第二装置,或通过其它装置或连接手段间接地电气连接到第二装置。
根据本发明的具体实施方式所描绘的图式仅为示意图,并未按照原比例绘制。而为了更明确地表达本发明的发明特征,一些图式中的尺寸会被加以放大。在下文中,揭露多个具体实施方式,这些具体实施方式具有一些相同的特征。为了简洁起见,在不同具体实施方式中出现的相同或类似的特征,以相同的元件符号表示。
图1至图5是根据本发明较佳实施方式所描绘的制备具有多层接触蚀刻停止层的半导体元件的方法剖面示意图。如图1所示,提供半导体基底10,其上包含有NMOS晶体管102以及PMOS晶体管104。此处需特别强调,本具体实施方式所述的金属氧化物半导体晶体管仅作为解说的用途,本发明仍可适用其他类型的晶体管。此外,虽然在本发明的较佳实施方式中包含两个晶体管,本发明也可实施于一个或多个晶体管结构。而且,本发明可应用于P型晶体管、N型晶体管或是上述两者。半导体基底10可包含但不限于硅基底、具有外延晶层(epitaxial)的硅基底、包含有内嵌绝缘层的硅绝缘基底、砷化镓(GaAs)基底、磷砷化镓(GaAsP)基底、磷化铟(InP)基底、砷化镓铝(GaAlAs)基底、或磷化铟镓(InGaP)基底。
根据本发明的较佳实施方式,半导体基底10可为P型硅基底。浅沟槽绝缘(shallow trench isolation,STI)区12可形成于半导体基底10的主要表面,使NMOS晶体管102与PMOS晶体管104相隔绝。
NMOS晶体管102可包含覆盖于半导体基底10主动区域之上的栅极电极22、介于栅极电极22以及半导体基底10之间的栅极介电层24、位于半导体基底10内的N型源极重掺杂区26a,其中N型源极重掺杂区26a位于栅极电极22的一侧、以及位于半导体基底10内的N型漏极重掺杂区26b,其中N型漏极重掺杂区26b位于栅极电极22的另一侧。侧壁间隙壁(sidewall spacer)222可形成于栅极电极22的侧壁。
同样地,PMOS晶体管104可包含覆盖于半导体基底10主动区域之上的栅极电极42、介于栅极电极42以及半导体基底10之间的栅极介电层44、位于半导体基底10内的P型源极重掺杂区46a,其中P型源极重掺杂区46a位于栅极电极42的一侧、以及位于半导体基底10内的P型漏极重掺杂区46b,其中P型漏极重掺杂区46b位于栅极电极42的另一侧。侧壁间隙壁422可形成于栅极电极42的侧壁。此处需特别强调,本具体实施方式所述的NMOS晶体管102以及PMOS晶体管104仅作为解说的用途,本发明仍可适用其他结构的半导体元件,例如,其他结构的晶体管。
如图2所示,第一蚀刻停止层120可通过包覆的方式,顺形地沉积于半导体基底10之上。第一蚀刻停止层120可覆盖于NMOS晶体管102、浅沟槽绝缘区12、以及PMOS晶体管104之上。此外,第一蚀刻停止层120可包覆位于NMOS晶体管102内的源极重掺杂区26a、间隙壁222、栅极电极22以及漏极重掺杂区26b,也可包覆位于PMOS晶体管104内的源极重掺杂区46a、间隙壁422、栅极电极42以及漏极重掺杂区46b。根据本发明的较佳实施方式,第一蚀刻停止层120可包含有氮化硅、氧化硅、氮氧化硅或上述组合,但不限于此。
根据本发明的较佳实施方式,第一蚀刻停止层120可以是氮化硅层。第一蚀刻停止层120的厚度与工艺技术有关。举例而言,第一蚀刻停止层120的厚度可为数十至数百埃米。第一蚀刻停止层120可为能转移应力的应力层,举例而言,伸张应力层或压缩应力层,根据本发明的较佳实施方式,第一蚀刻停止层120能转移应力至第一蚀刻停止层120下的基底,更重要的是,能转移应力至晶体管中的载子通道,使得载子的迁移率得以提升。目前,已有许多不同的方法可用来形成位于半导体基底10上的第一蚀刻停止层120,举例而言,等离子辅助化学气相沉积(plasma-enhanced CVD,PECVD)或低压化学气相沉积(low-pressure CVD,LPCVD)。
如图3所示,在形成或沉积第一蚀刻停止层120之后,可接着形成或沉积第二蚀刻停止层122,铺展于第一蚀刻停止层120上。第二蚀刻停止层122的厚度与工艺技术有关。举例而言,第二蚀刻停止层122的厚度可为数十至数百埃米。第二蚀刻停止层122能顺形地覆盖第一蚀刻停止层120,因此构成本发明的多层蚀刻停止层结构200。根据本发明的较佳实施方式,第二蚀刻停止层122与第一蚀刻停止层120由不同材料所构成。举例而言,第一蚀刻停止层120可为氮化硅层而第二蚀刻停止层122可为氮氧化硅层。
根据本发明的较佳实施方式,第二蚀刻停止层122可包含有氮化硅、氧化硅、氮氧化硅、碳化硅或上述组合,但不限于此。根据本发明的较佳实施方式,第二蚀刻停止层122可做为等离子放电层,等离子放电层能转导等离子处理程序中产生的等离子诱发电荷,避免其下的元件遭受到电压差的损害,因此可提升元件的可靠度,且可降低临界电压(threshold voltage,Vt)偏移的数值。
为了有效转导等离子诱发电荷,第二蚀刻停止层122较第一蚀刻停止层具有较强的等离子耐受性。已知第二蚀刻停止层122可为能转移应力的应力层,举例而言,伸张应力层或压缩应力层,用以增进元件的效能。
紧接着,参照图4,形成介电层,例如,层间介电(inter-layerdielectric,ILD)层132,覆于半导体基底10上。此处须注意,层间介电层132可直接形成在第二蚀刻停止层122之上,且覆盖于NMOS晶体管102以及PMOS晶体管104之上。介电层132可包含有未掺杂硅玻璃(USG)、硼硅玻璃(BSG)、硼磷硅玻璃(BPSG)或上述组合,但不限于此。且可采用不同种类的介电材料,用来形成介电层132,介电层132可能为一层或多层介电层。根据本发明的较佳实施方式,第二蚀刻停止层122与介电层132是由不同材料所构成。介电层132可通过传统的工艺而形成,举例而言,等离子辅助化学气相沉积或低压化学气相沉积。
如图5所示,接着,进行传统的微影蚀刻(lithographic and etching)工艺,以在介电层132与多层蚀刻停止层结构200内形成多个接触洞134。举例而言,蚀刻可以分成两步骤进行。在第一蚀刻步骤中,可蚀刻接触洞的上部至介电层132内,并且使接触洞的底部停止在多层蚀刻停止层结构200的上表面或是第二蚀刻停止层122的表面。第一蚀刻步骤可能为较激烈的干式蚀刻且具有较快的蚀刻速率。在第二蚀刻步骤,施行在较温和的蚀刻条件下以及具有较缓慢的蚀刻速率,用以蚀刻残留的多层蚀刻停止层结构200,暴露出位于下层的扩散区,例如,源极区或漏极区。
根据本发明的其他实施方式,多层蚀刻停止层结构可包含两层以上的多层蚀刻停止层。多层蚀刻停止层结构可至少由两种不同材料所构成,即,位于多层蚀刻停止层结构中的至少一蚀刻停止层的材料不同于位于多层蚀刻停止层结构中的另一蚀刻停止层的材料。此外,位于多层蚀刻停止层结构最上层的蚀刻停止层材料不同于位于蚀刻停止层之上的介电层材料。
本领域中技术人员应能理解,在不脱离本发明的精神和范围的情况下,可对本发明做许多更动与改变。因此,上述本发明的范围具体应以后附的权利要求界定的范围为准。
Claims (18)
1.一种半导体元件结构,包含有:
基底,其上包含有晶体管;
两层接触蚀刻停止层结构,覆盖住上述晶体管,上述两层接触蚀刻停止层结构包含有第一蚀刻停止层以及第二蚀刻停止层,其中,上述第二蚀刻停止层接触上述第一蚀刻停止层;上述第一蚀刻停止层接触上述基底和上述晶体管;上述第二蚀刻停止层为等离子放电层;以及
介电层,设于上述第二蚀刻停止层上,上述介电层接触上述第二蚀刻停止层;
其中,上述第一蚀刻停止层与上述第二蚀刻停止层由不同材料所构成,而上述第二蚀刻停止层与上述介电层由不同材料所构成;上述第二蚀刻停止层较上述第一蚀刻停止层具有较强的等离子耐受性。
2.如权利要求1所述的半导体元件结构,其特征在于,上述第一蚀刻停止层包含有氮化硅、氧化硅、氮氧化硅或上述组合。
3.如权利要求1所述的半导体元件结构,其特征在于,上述第二蚀刻停止层包含有氮化硅、氧化硅、氮氧化硅、碳化硅或上述组合。
4.如权利要求1所述的半导体元件结构,其特征在于,上述第一蚀刻停止层为氮化硅所构成,上述第二蚀刻停止层为氮氧化硅所构成。
5.如权利要求1所述的半导体元件结构,其特征在于,上述介电层包含有未掺杂硅玻璃、硼硅玻璃、硼磷硅玻璃或上述组合。
6.如权利要求1所述的半导体元件结构,其特征在于,上述第一蚀刻停止层为应力层。
7.如权利要求6所述的半导体元件结构,其特征在于,上述第一蚀刻停止层为伸张应力层。
8.如权利要求1所述的半导体元件结构,其特征在于,上述第二蚀刻停止层为应力层。
9.一种半导体元件结构,包含有:
基底,其上包含有NMOS晶体管以及PMOS晶体管;
两层接触蚀刻停止层结构,覆盖住上述NMOS晶体管及上述PMOS晶体管,上述两层接触蚀刻停止层结构包含有第一蚀刻停止层以及第二蚀刻停止层,其中,上述第二蚀刻停止层接触上述第一蚀刻停止层;上述第一蚀刻停止层接触上述基底、上述NMOS晶体管和上述PMOS晶体管;上述第二蚀刻停止层为等离子放电层;以及
介电层,设于上述第二蚀刻停止层上;上述介电层接触上述第二蚀刻停止层;
其中,上述第一蚀刻停止层与上述第二蚀刻停止层由不同材料所构成,而上述第二蚀刻停止层与上述介电层由不同材料所构成;上述第二蚀刻停止层较上述第一蚀刻停止层具有较强的等离子耐受性。
10.如权利要求9所述的半导体元件结构,其特征在于,上述第一蚀刻停止层包含有氮化硅、氧化硅、氮氧化硅或上述组合。
11.如权利要求9所述的半导体元件结构,其特征在于,上述第二蚀刻停止层包含有氮化硅、氧化硅、氮氧化硅、碳化硅或上述组合。
12.如权利要求9所述的半导体元件结构,其特征在于,上述第一蚀刻停止层为氮化硅所构成,上述第二蚀刻停止层为氮氧化硅所构成。
13.如权利要求9所述的半导体元件结构,其特征在于,上述介电层包含有未掺杂硅玻璃、硼硅玻璃、硼磷硅玻璃或上述组合。
14.如权利要求9所述的半导体元件结构,其特征在于,上述第一蚀刻停止层为应力层。
15.如权利要求14所述的半导体元件结构,其特征在于,上述第一蚀刻停止层为伸张应力层。
16.如权利要求14所述的半导体元件结构,其特征在于,上述第一蚀刻停止层为压缩应力层。
17.如权利要求9所述的半导体元件结构,其特征在于,上述第二蚀刻停止层为应力层。
18.如权利要求9所述的半导体元件结构,其特征在于,上述介电层直接设于上述第二蚀刻停止层上,并同时覆盖上述NMOS晶体管及上述PMOS晶体管。
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