CN102437577B - Control circuit used in active power filter (APF) - Google Patents
Control circuit used in active power filter (APF) Download PDFInfo
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- CN102437577B CN102437577B CN201110438335.8A CN201110438335A CN102437577B CN 102437577 B CN102437577 B CN 102437577B CN 201110438335 A CN201110438335 A CN 201110438335A CN 102437577 B CN102437577 B CN 102437577B
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Classifications
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
- Y02E40/20—Active power filtering [APF]
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Abstract
The invention relates to an active filter, and in particular relates to a control circuit used in an active power filter (APF). The control circuit comprises a master control board (1), sampling boards (2), a display board (3), an optical fiber board (5), an input/output board (6) and a touch screen (4), wherein, the master control board (1) is respectively and electrically connected with the first sampling board, the second sampling board, the input/output board (6) and the optical fiber board (5) through a bus interface (7), and the master control board (1) is electrically connected with a display and the touch screen (4) through a display bus; the sampling boards (2) acquire three-phase current and voltage signals and transmit the signals to the master control board (1) and the display board (3); the master control board (1) performs algorithm processing and sends a control signal which needs to be output to the optical fiber board (5), the display board (3) and the input/output board (6); the optical fiber board (5) sends out the IGBT (insulated gate bipolar transistor) control signal through optical fiber; the input/output board (6) sends out a switching value through a relay; and the display board (3) and the touch screen (4) directly perform data transmission, and the display board feeds the information received by the touch screen (4) back to the master control board (1).
Description
Technical field
The present invention relates to a kind of active filter, especially for the control circuit of active power filter.
Background technology
Existing active filter generally includes master control borad, display panel, sampling plate (module), input and output plate, fibre optic plate, sampling module adopts the pattern of signal adjusting module+sampling module mostly, wherein signal condition module is for the treatment of the interference in signal, and sampling module carries out signals collecting to the signal of nursing one's health.Analog input card circuit complexity, dismounting is inconvenient, space is large, is not easy to measure debugging.
Existing fibre optic plate show light signal strength a little less than, although make power consumption lower, higher for stabilized fiber qualitative requirement, in the time that optical fiber rocks, very easily occur that the problem of beating appears in acknowledge(ment) signal, and use chip be external import, expensive.
Summary of the invention
The object of this invention is to provide a kind of easy to maintenancely, performance safety is reliably for the control circuit of active power filter.
The object of the present invention is achieved like this, for the control circuit of active power filter, it comprises: master control borad, sampling plate, display panel, fibre optic plate, input and output plate and touch-screen, master control borad is electrically connected with the first sampling plate, the second sampling, input and output plate and fibre optic plate respectively by bus interface, and master control borad is electrically connected by show bus with display and touch-screen; Sampling plate gathers three-phase current, voltage signal is delivered to master control borad and display panel, master control borad carries out algorithm process, the control signal of needs output is sent to fibre optic plate, display panel and input and output plate, fibre optic plate sends IGBT control signal by optical fiber, input and output plate sends switching value by relay, display panel and touch-screen directly carry out transfer of data, and the information that touch-screen is received feeds back to master control borad.
The signal of sampling plate enters after differential amplifier, amplifies by differential amplifier, and differential amplifier adopts AD620, and differential amplifier, by outputing to A/D chip after amplification, converts analog quantity to digital quantity by A/D chip; A/D chip is electrically connected with RAM and CPLD respectively, RAM is connected with sampling plate bus interface with CPLD, under master board control, complete sequential operation by CPLD, making A/D chip convert analog quantity to digital quantity deposits in RAM, CPLD controls stored data and to sampling plate bus interface output data, the DSP of master control borad sends an order to CPLD, and CPLD can put forward automatic data acquisition and output task.
Sampling plate comprises the first sampling plate and the second sampling plate, and they have identical circuit framework, and the curtage signal of electric power system is gathered, and also can separately complete the collection of electric current and voltage.
Sampling plate sampling resistor uses large encapsulation straight cutting precision resistance, and unified order welding, makes resistance one end exceed circuit board.
The AD620 of sampling plate is preamplifier, between signal input part and floating ground and between the earth, have respectively two groups of capacitor C 1, C2, C3, wherein C3, C1 to cabinet externally, are connected with casing by double-screw bolt in plate, C3, C2 are connected in series to systematically, and capacitor C 3 is as service message appearance use altogether; Two groups of electric capacity carry out signal filtering and electromagnetic shielding to input signal; AD620 sample circuit adopts positive-negative power supply, and at positive-negative power serial connection voltage-stabiliser tube D3 and D6, the tie point of D3 and D6 is electrically connected with the in-phase end of AD620, forms signal clamping circuit; Capacitor C 7 between input pickup resistance R3 and in-phase end one end of oppisite phase forms input filter, and the resistance R 9 between the pin one and 8 of AD620 is multiplying power regulating resistance; The clutter being used for more than filtering setpoint frequency, again reduces entering plate and disturbs; R9 and R1 are sample resistance, and output R11 and C9 carry out secondary filtering.
Master control borad comprises that DSP, CPLD, RAM and bus form bus circuit and connect, display panel comprises display driver, LCD display, display random access memory, DSP, CPLD are electrically connected the RAM of master control borad RAM and display panel simultaneously, and the display driver of display panel is electrically connected with RAM and LCD display respectively.
Input and output plate comprises optocoupler and electromagnetic relay, opens or output signal by being electrically connected with electromagnetic relay optical coupling after optocoupler, and by optocoupler, OP1 isolates, and can prevent that impact and overvoltage that external electromagnetic interference causes from entering plate; The line of described electromagnetic relay is surrounded by a parallel connected in reverse phase diode D1, for line bag is protected, and the surge voltage while reducing action.
Fibre optic plate comprises optical fiber emitting head circuit, and the HFBR-1527 in optical fiber emitting head circuit is optical fiber emitting head circuit, and it is integrated with 8 pins, and 2 pin are transmitting terminal, and 2 pin are divided into three tunnels, and the first via connects power supply by pull-up resistor R19, and pull-up resistor selects 10K resistance; The second tunnel is electrically connected with 4.7UF electric capacity and a resistance respectively by capacitor C 12, forms filter circuit, and the resistance other end is electrically connected with 1 pin of HFBR-1527, and electric capacity is electrically connected with 3,4,5,8 of HFBR-1527, forms common-base circuit; Third Road is electrically connected with the emitter of positive-negative-positive three utmost points, transistor collector ground connection, and base stage receives and sends control end.
The present invention is made up of master control borad, sampling plate, display panel, fibre optic plate, input and output plate and touch-screen, master control borad is electrically connected with the first sampling plate, the second sampling, input and output plate and fibre optic plate respectively by bus interface, and master control borad is electrically connected by show bus with display and touch-screen; Sampling plate gathers three-phase current, voltage signal is delivered to master control borad and display panel, master control borad carries out algorithm process, the control signal of needs output is sent to fibre optic plate, display panel and input and output plate, fibre optic plate sends IGBT control signal by optical fiber, input and output plate sends switching value by relay, display panel and touch-screen directly carry out transfer of data, and the information that touch-screen is received feeds back to master control borad.It has easy to maintenance, the reliable feature of performance safety.
Brief description of the drawings
Below in conjunction with embodiment accompanying drawing, the invention will be further described:
Fig. 1 is embodiment of the present invention circuit block diagram;
Fig. 2 is sampling plate circuit block diagram;
Fig. 3 is signal amplification circuit figure;
Fig. 4 is master control borad and display panel electrical schematic diagram;
Fig. 5 is input and output plate electrical schematic diagram;
Fig. 6 is fibre optic plate electrical schematic diagram.
In figure, 1, master control borad; 2, sampling plate; 3, display panel; 4, touch-screen; 5, fibre optic plate; 6, input and output plate; 7, bus interface.
Embodiment
As shown in Figure 1, it comprises: master control borad 1, sampling plate 2, display panel 3, fibre optic plate 5, input and output plate 6 and touch-screen 4, master control borad 1 is electrically connected with the first sampling plate, the second sampling, input and output plate 6 and fibre optic plate 5 respectively by bus interface 7, and master control borad 1 is electrically connected by show bus with display and touch-screen 4.Sampling plate 5(comprises: the first sampling plate, the second sampling or accelerate as required) gather three-phase current, voltage signal and be delivered to master control borad 1 and display panel 3, master control borad 1 carries out algorithm process, the control signal of needs output is sent to fibre optic plate 5, display panel 3 and input and output plate 6, fibre optic plate 5 sends IGBT control signal by optical fiber, input and output plate 6 sends switching value by relay, display panel 3 directly carries out transfer of data with touch-screen 4, and the information that touch-screen 4 is received feeds back to master control borad 1.
As shown in Figure 2, provide the circuit block diagram of sampling plate 1, signal enters after differential amplifier 201, amplify by differential amplifier 201, differential amplifier 201 adopts AD620, it is the measuring amplifier of a low noise, low-power consumption, and differential amplifier 201, by outputing to A/D chip 202 after amplification, converts analog quantity to digital quantity by A/D chip 202.A/D chip 202 is electrically connected with RAM203 and CPLD204 respectively, RAM203 is connected with sampling plate bus interface 205 with CPLD204, under master board control, complete sequential operation by CPLD204, make A/D chip 202 convert analog quantity to digital quantity and deposit in RAM203.CPLD204 is the Programmable Logic Controller with EEPROM, and it has electronically written and modify feature more easily than FPGA, utilizes real time modifying and input parameter.CPLD204 controls stored data and exports data to sampling plate bus interface 205.In this process, the DSP of master control borad does not participate in controlling, completed by CPLD204 completely, as long as the DSP of master control borad sends an order to CPLD204, CPLD204 can put forward automatic data acquisition and output task, save the time of the DSP of master control borad, for better processes and displays and other operation high to real-time.
Sampling plate 1 comprises the first sampling plate and the second sampling plate in figure, and they have identical circuit framework, can complete identical task, as the curtage signal to electric power system gathers, also can separately complete the collection of electric current and voltage.
Sampling plate 1 sampling resistor uses large encapsulation straight cutting precision resistance, and unified order welding, makes resistance one end exceed circuit board more, articulates oscilloscope test pencil when being convenient to machine debugging.
It is simple that sampling plate of the present invention analog input card similar with market compared circuit, and convenient disassembly, saving space, be convenient to measure debugging, can reach equally the sample effect of expection.
Fig. 3 is the circuit theory diagrams that AD620 carries out preposition amplification.Sampling plate 1 AD620 carries out preposition amplification, In1 is signal input part, between signal input part and floating ground and between the earth, there are respectively two groups of capacitor C 1, C2, C3, wherein C3, C1 to cabinet externally, are connected with casing by double-screw bolt in plate, so can allow cover copper into Ban Chu and be connected with outside cabinet, cover herein and in copper and plate, cover copper and isolate mutually, play shielding action, C3, C2 are connected in series to systematically, and capacitor C 3 is as service message appearance use altogether.Two groups of electric capacity carry out signal filtering and electromagnetic shielding to input signal; Sample circuit adopts positive-negative power supply, and at positive-negative power serial connection voltage-stabiliser tube D3 and D6, the tie point of D3 and D6 be electrically connected with the in-phase end of AD620, formation signal clamping circuit, for the protection of sample circuit because spread of voltage causes the damage of employing circuit; Capacitor C 7 between input R3 and in-phase end one end of oppisite phase forms input filter, and the resistance R 9 between the pin one and 8 of AD620R9 is multiplying power regulating resistance; The clutter being used for more than filtering setpoint frequency, again reduces entering plate and disturbs; R9 and R1 are sample resistance, and output R11 and C9 carry out secondary filtering; Reduce other circuit in plate and power supply is fed back to the signal fluctuation causing.
In the present invention, the ground connection at C1 place be cabinet externally, be connected with casing by double-screw bolt in plate, so can allow and cover copper into Ban Chu and be connected with outside cabinet, cover herein and in copper and plate, cover copper and isolate mutually, play shielding action, and enter partitioned signal by capacitor C 3, C1 the earth is connected, and plate is connected with cabinet by resistance R 4 interiorly, can reduce into plate and disturb.R3 and C7 composition RC filter resistance, and can determine amplifying circuit input and the phase angle difference of exporting by this circuit, to regulate and control in program.AD620 is differential amplifier, under the cooperation of anterior circuit, can reach enough filter effects, and the output waveform that is is safe and reliable.The wherein filter circuit of output R11 and C9 composition.
As shown in Figure 4, provide master control borad 1 and display panel 3 circuit block diagrams, master control borad 1 comprises that DSP101, CPLD102, RAM103 and bus 104 form bus circuit and connect, display panel 3 comprises display driver 301, LCD display 303, display random access memory 302, DSP101, CPLD102 are electrically connected the RAM302 of master control borad 1 RAM103 and display panel 3 simultaneously, and the display driver 301 of display panel 3 is electrically connected with RAM302 and LCD display 303 respectively.Adopt the workflow of DSP---CPLD---RAM and bus.DSP is fastest, and CPLD speed is adjustable, and RAM and bus speed are the slowest.DSP carries out main high speed signal processing, and data docking completes in RAM and bus by CPLD.In the time that DSP needs data, give in advance CPLD photos and sending messages, CPLD, from RAM or always line drawing data at a slow speed, extracts complete and carries out after simple format analysis processing, gives DPS signal, then in the total CPLD of DSP, extracts needed information.Utilize sequential to coordinate the object that reaches high speed processing.It is the same that DPS is outwards put the process of data.Master control borad and display panel are unanimous on the whole, are connected to become different functions by different interfaces.Master control borad and display panel adopt Information Sharing Mode in addition, and master control borad synchronize acceptance and storage data with the RAM in display panel, and the benefit of doing is like this: (1), in the time of one of them RAM damage, can extract data from other RAM; (2) under normal circumstances, reading out data the RAM in own plate all when this two plank usage datas, disturb than only having in the situation of a RAM (often having the plank of RAM to read the data in the RAM on another one plank by bus) to reduce bus, reduce error code, and can improve data operating speed (can take bus when only having a RAM).(3) CPLD in sampling plate and input and output plate works there is RAM, therefore each plank that needs transfer of data only just can take bus when needs are emitted data, improve circulation rate and total line use ratio, reduced the capacity requirement of the CPLD of master control and display panel simultaneously.RAM in each plate and bus are parallel-connection structures for CPLD, and necessary time, (RAM damage) CPLD can skip RAM directly from bus reading.But as the method can reduce circulation rate and total line use ratio, only as emergency plan.
As shown in Figure 5, input and output plate 6 comprises optocoupler 601 and electromagnetic relay 602, open into or output signal and be electrically connected with electromagnetic relay 602 optical coupling by after optocoupler 601, by optocoupler, OP1 isolates, and can prevent that impact and overvoltage that external electromagnetic interference causes from entering plate.The line of described electromagnetic relay 602 is surrounded by a parallel connected in reverse phase diode D1, for line bag is protected, and the surge voltage while reducing action.
As shown in Figure 6, HFBR-1527 is optical fiber emitting head circuit, and it is integrated optical fiber luminescent head and send out a transtation mission circuit is integrated with 8 pins, and 2 pin are transmitting terminal, and 2 pin are divided into three tunnels, and the first via connects power supply by pull-up resistor R19, and pull-up resistor selects 10K resistance.The second tunnel is electrically connected with 4.7UF electric capacity and a resistance respectively by capacitor C 12, forms filter circuit, and the resistance other end is electrically connected with 1 pin of HFBR-1527, and electric capacity is electrically connected with 3,4,5,8 of HFBR-1527, forms common-base circuit.Third Road is electrically connected with the emitter of positive-negative-positive three utmost points, transistor collector ground connection, and base stage receives and sends control end.Increase the optical fiber emitting head peripheral circuit of positive-negative-positive three utmost points, have and measure conveniently compared with intersil recommended typical circuit, signal power is adjustable, the features such as signal stabilization.
The build-out resistor that master control borad 1, sampling plate 2, display panel 3, fibre optic plate 5, input and output plate 6 all add before bus is entered plate, the fluctuation at edge while being used for eliminating into plate, reduces bus simultaneously and disturbs.
Claims (5)
1. for the control circuit of active power filter, it is characterized in that: it comprises: master control borad (1), sampling plate (2), display panel (3), fibre optic plate (5), input and output plate (6) and touch-screen (4), master control borad (1) is electrically connected with the first sampling plate, the second sampling plate, input and output plate (6) and fibre optic plate (5) respectively by bus interface (7), and master control borad (1) is electrically connected by show bus with display and touch-screen (4); Fibre optic plate (5) gathers three-phase current and voltage signal is delivered to master control borad (1) and display panel (3), master control borad (1) carries out algorithm process, the control signal of needs output is sent to fibre optic plate (5), display panel (3) and input and output plate (6), fibre optic plate (5) sends IGBT control signal by optical fiber, input and output plate comprises optocoupler and electromagnetic relay, opening or output signal is electrically connected with electromagnetic relay optical coupling by after optocoupler, by optocoupler, OP1 isolates, and prevents that impact and overvoltage that external electromagnetic interference causes from entering plate; The line of described electromagnetic relay is surrounded by a parallel connected in reverse phase diode D1, for line bag is protected, and the surge voltage while reducing action; Input and output plate (6) sends switching value by relay, display panel (3) directly carries out transfer of data with touch-screen (4), and the information that touch-screen (4) is received feeds back to master control borad (1); Fibre optic plate comprises optical fiber emitting head circuit, and optical fiber emitting head circuit adopts HFBR-1527 optical fiber emitting head circuit, and it is integrated with 8 pins, and 2 pin are transmitting terminal, and 2 pin are divided into three tunnels, and the first via connects power supply by pull-up resistor R19, and pull-up resistor selects 10K resistance; The second tunnel be electrically connected with 4.7UF electric capacity and a resistance respectively by capacitor C 12, forms filter circuit, and the resistance other end is electrically connected with 1 pin of HFBR-1527, and 3,4,5,8 the chip pin of 4.7UF electric capacity and HFBR-1527 is electrically connected, formation common-base circuit; Third Road is electrically connected with the emitter of positive-negative-positive triode, transistor collector ground connection, and base stage receives and sends control end.
2. the control circuit for active power filter according to claim 1, it is characterized in that: the signal of sampling plate enters after differential amplifier, amplify by differential amplifier, differential amplifier adopts AD620, differential amplifier outputs to A/D chip after signal is amplified, and converts analog quantity to digital quantity by A/D chip; A/D chip is electrically connected with RAM and CPLD respectively, RAM is connected with sampling plate bus interface with CPLD, under master board control, complete sequential operation by CPLD, making A/D chip convert analog quantity to digital quantity deposits in RAM, CPLD controls stored data and to sampling plate bus interface output data, the DSP of master control borad sends an order to CPLD, and CPLD can automatic data acquisition and output task.
3. the control circuit for active power filter according to claim 1, it is characterized in that: sampling plate comprises the first sampling plate and the second sampling plate, they have identical circuit framework, curtage signal to electric power system gathers, and also can separately complete the collection of electric current and voltage.
4. the control circuit for active power filter according to claim 1, is characterized in that: sampling plate sampling resistor uses large encapsulation straight cutting precision resistance, and unified order welding, makes resistance one end exceed circuit board.
5. the control circuit for active power filter according to claim 1, it is characterized in that: master control borad is made up of DSP, CPLD, RAM and bus, display panel comprises display driver, LCD display and display random access memory, DSP and CPLD are electrically connected the RAM of master control borad RAM and display panel simultaneously, and the display driver of display panel is electrically connected with RAM and LCD display respectively.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110438335.8A CN102437577B (en) | 2011-12-24 | 2011-12-24 | Control circuit used in active power filter (APF) |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110438335.8A CN102437577B (en) | 2011-12-24 | 2011-12-24 | Control circuit used in active power filter (APF) |
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| CN102437577A CN102437577A (en) | 2012-05-02 |
| CN102437577B true CN102437577B (en) | 2014-10-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201110438335.8A Expired - Fee Related CN102437577B (en) | 2011-12-24 | 2011-12-24 | Control circuit used in active power filter (APF) |
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| CN (1) | CN102437577B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106773910B (en) * | 2016-11-22 | 2019-05-21 | 天津航空机电有限公司 | A kind of high linearity difference isolation sample circuit |
| CN112118052B (en) * | 2019-06-21 | 2021-12-17 | 华为技术有限公司 | Optical receiving module, optical transmitting and receiving module, optical module and optical network equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101291059A (en) * | 2007-08-28 | 2008-10-22 | 东南大学 | Electricity quality analyzer oriented to digitalized electrical system and electricity quality analysis method |
| CN201466737U (en) * | 2009-04-02 | 2010-05-12 | 保定天威集团有限公司 | High-voltage static var compensation device based on minimum system |
| CN201608532U (en) * | 2010-02-10 | 2010-10-13 | 南京亚派科技实业有限公司 | Active power filter system |
| CN202602286U (en) * | 2011-12-24 | 2012-12-12 | 西安天虹电器有限公司 | Control device for power active filter |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6297980B1 (en) * | 1999-08-06 | 2001-10-02 | The Regents Of The University Of California | Unified constant-frequency integration control of three-phase power corrected rectifiers, active power filters, and grid-connected inverters |
-
2011
- 2011-12-24 CN CN201110438335.8A patent/CN102437577B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101291059A (en) * | 2007-08-28 | 2008-10-22 | 东南大学 | Electricity quality analyzer oriented to digitalized electrical system and electricity quality analysis method |
| CN201466737U (en) * | 2009-04-02 | 2010-05-12 | 保定天威集团有限公司 | High-voltage static var compensation device based on minimum system |
| CN201608532U (en) * | 2010-02-10 | 2010-10-13 | 南京亚派科技实业有限公司 | Active power filter system |
| CN202602286U (en) * | 2011-12-24 | 2012-12-12 | 西安天虹电器有限公司 | Control device for power active filter |
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| CN102437577A (en) | 2012-05-02 |
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