CN102437036A

CN102437036A - Gate etching method capable of enhancing performance of floating body dynamic random access memory unit

Info

Publication number: CN102437036A
Application number: CN2011102653117A
Authority: CN
Inventors: 俞柳江
Original assignee: Shanghai Huali Microelectronics Corp
Current assignee: Shanghai Huali Microelectronics Corp
Priority date: 2011-09-08
Filing date: 2011-09-08
Publication date: 2012-05-02
Anticipated expiration: 2031-09-08
Also published as: CN102437036B

Abstract

The invention relates to a gate etching method capable of enhancing performance of a floating body dynamic random access memory unit, and the method comprises the following steps: exposing a photoresist, carrying out primary etching on polycrystalline silicon uncovered by the photoresist, and thinning the etched polycrystalline silicon to form a residual polycrystalline silicon layer; carrying out a reduction technique on the photoresist, so that the area of the photoresist subjected to the reduction technique is less than that of the polycrystalline silicon gate; and after the photoresist reduction technique, etching the polycrystalline silicon gate again to gradually remove the polycrystalline silicon gate under the etching action of the part of polycrystalline silicon gate uncovered by the photoresist, and stopping etching when the previously formed residual polycrystalline silicon layer is completely removed, wherein the thickness of the residual polycrystalline silicon gate uncovered by the photoresist is less than that of the polycrystalline silicon gate covered by the photoresist. The method provided by the invention be used for effectively utilizing the reduced thickness of the polycrystalline silicon gate adjacent to the source and drain ends, so that the intensity of the longitudinal electric field in the channel between the two ends of the source and drain is increased when a voltage is applied to the polycrystalline silicon gate, thereby enhancing the write-in capacity of the floating body effect memory unit.

Description

A kind of grid lithographic method that improves buoyancy aid DRAM cell performance

Technical field

The present invention relates to a kind of technique processing method, relate in particular to a kind of grid lithographic method that improves buoyancy aid DRAM cell performance.

Background technology

The development of embedded dynamic memory technology has made big capacity dynamic random access memory (Dynamic Random Access Memory is called for short DRAM) very general in present system level chip (System on a Chip is called for short SOC).The big embedded dynamic memory of capacity (Embedded Dynamic RAM is called for short EDRAM) has brought to SOC can only be through the various benefits that adopt embedded technology to realize such as improving bandwidth and reduction power consumption etc.

Each memory cell of the embedded dynamic memory of tradition (EDRAM) is except transistor; Also need a deep trench capacitor structure; The deep trench of capacitor makes that its width of aspect ratio of memory cell is a lot of greatly; Cause manufacturing process difficulty, and its manufacture craft and cmos vlsi technology are very incompatible, so limited its application in embedded system chip (SOC).

Floater effect memory cell (Floating Body Cell is called for short FBC) is a kind of dynamic memory that is hopeful to substitute EDRAM.FBC utilizes floater effect (Floating Body Effect; Abbreviation FBE) DRAM cell; Its principle is to utilize silicon-on-insulator (Silicon on Insulator; Abbreviation SOI) floater effect that the buffer action of oxygen buried regions (BOX) is brought in the device as memory node, is realized segregate buoyancy aid (Floating Body) one writing and is write " 0 ".

Fig. 1-2 is the operation principle sketch map of floater effect memory cell in the background technology of the present invention.As shown in Figure 1, be example with NMOS, with source electrode (S) 4 ground connection of device, grid (G) 12 and drain electrode (D) 3 ends add positive bias V (+), then this break-over of device; Because the transverse electric field effect, electronics near drain electrode 3 with silicon atom ionization by collision, generation electron hole pair; Part hole is swept substrate 14 by longitudinal electric field, forms substrate current, because the existence of aerobic buried regions 2; Substrate current can't discharge; Make the hole gather (△ Q) at buoyancy aid, be defined as first kind of store status, i.e. one writing; As shown in Figure 2, on grid (G) 12, apply positive bias, in drain electrode 3, apply back bias voltage, through the PN junction forward bias, launch from buoyancy aid in the hole, is defined as second kind of store status, promptly writes " 0 ".Because gathering of substrate electric charge can change the threshold voltage (Vt) of device, can cause the difference of threshold voltage through this two states of big or small perception of electric current, promptly realizes read operation.Because the floater effect memory cell has been removed the capacitor among traditional DRAM; Make its technological process fully and the CMOS process compatible; Simultaneously can the higher memory of component density, therefore be hopeful to substitute existing traditional E DRAM and be applied in the embedded system chip.

The floater effect memory cell is when one writing, and promptly charge carrier is in the process that substrate gathers, and the speed of one writing is by the decision of the size of substrate current.Improve the substrate current of floater effect memory cell, just can improve the writing speed of floater effect memory cell, thereby improve the performance of floater effect memory cell.

Summary of the invention

Disclosure of the Invention a kind of grid lithographic method that improves buoyancy aid DRAM cell performance, in order to improve the writing speed of floater effect memory cell.

For realizing above-mentioned purpose, the technical scheme that invention is adopted is:

A kind of grid lithographic method that improves buoyancy aid DRAM cell performance; Comprise: cover the aerobic buried regions on the substrate, and on the oxygen buried regions, be provided with drain electrode and source electrode, and the device channel that forms between drain electrode and the source electrode; Upper surface at said device channel, drain electrode and source electrode is equipped with polysilicon; The upper surface of said polysilicon is coated with photoresist, wherein, and process:

Step 1, making public, developing, the photoresist of the polysilicon gate of a formation covering device grid photoresist;

Step 2 to not carried out etching by the polysilicon that photoresist covered, and makes the polysilicon attenuation that is etched form the residual polysilicon layer of one deck;

Step 3 is subdued technology to said photoresist, makes the area of the area of the photoresist that carried out subduing technology less than polysilicon gate;

Step 4; Subduing after the technology through said photoresist; Once more polysilicon is carried out etching; Do not make to be removed gradually under etching by the polysilicon gate that photoresist covered, formed residual polysilicon layer stops etching after removing fully in step 2, and the formation residue is not thinner than the polysilicon gate thickness that is covered by photoresist by the polysilicon gate segment thickness that photoresist covers;

Step 5, the heavy doping injection, annealing, the silicide that after above step, carry out light dope injection, annealing, side wall formation, source electrode and drain electrode form, and interconnected technology.

Above-mentioned process, wherein, to not carried out etching by the polysilicon that photoresist covered, the degree of depth of institute's etching was controlled by the time in the said step 2.

Above-mentioned process, wherein, in the said step 4, residue is the residual polysilicon layer thickness that step 2 forms not by the polysilicon gate segment thickness of photoresist covering and by the thickness difference between the polysilicon gate thickness that photoresist covered.

Above-mentioned process, wherein, formed side wall is covered in the part substrate of polysilicon sidewall and contiguous polysilicon in the said step 5.

The grid lithographic method of raising buoyancy aid DRAM cell performance of the present invention, its effect is:

1, the polycrystalline silicon etching process after improving, attenuate the polysilicon thickness that is close to of source electrode and drain electrode end;

2, because the polysilicon of source electrode and drain electrode end is thinner, when voltage was added in polysilicon and extremely goes up, the longitudinal electric field intensity in the source electrode and the two ends raceway groove that drains can increase;

3, in the device channel, the hole-electron pair that ionization by collision produces under the transverse electric field effect, charge carrier is swept substrate by stronger longitudinal electric field, makes substrate current strengthen, thereby has improved the write capability of floater effect memory cell.

Description of drawings

Through the detailed description that reading is done non-limiting example with reference to following accompanying drawing, the further feature of invention, it is more obvious that purpose and advantage will become.

The operation principle sketch map of floater effect memory cell in Fig. 1-2 background technology of the present invention;

Fig. 3 the present invention is a kind of to improve the schematic cross-section behind the resist exposure of grid lithographic method of buoyancy aid DRAM cell performance.

The first time of the grid lithographic method that Fig. 4 improves buoyancy aid DRAM cell performance for the present invention is a kind of schematic cross-section after to etching polysilicon;

The grid lithographic method that Fig. 5 improves buoyancy aid DRAM cell performance for the present invention is a kind of subdue the schematic cross-section behind the photoresist;

Fig. 6 is a kind of sketch map that the second time polysilicon is carried out etching that improves the grid lithographic method of buoyancy aid DRAM cell performance of the present invention;

The device schematic cross-section of the final completion of the grid lithographic method that Fig. 7 improves buoyancy aid DRAM cell performance for the present invention is a kind of.

Referring to scheming preface: bottom silicon 1, oxygen buried regions 2, drain electrode 3, source electrode 4, device channel 5, polysilicon 6, photoresist 7, residual polysilicon layer 8, side wall 9, silicide 10, grid oxygen 11, grid (G) 12, substrate 14, polysilicon gate 20.

Embodiment

For technological means that invention is realized, create characteristic, reach purpose and effect and be easy to understand and understand that following combinations specifically illustrates, and further sets forth the present invention.

Please referring to shown in Figure 3, a kind of grid lithographic method that improves buoyancy aid DRAM cell performance comprises: cover aerobic buried regions 2 on the bottom silicon 1; And on oxygen buried regions 2, being provided with shallow trench (STI), the shallow trench bottom joins with oxygen buried regions 2, is substrate 14 between the shallow trench; Be equipped with grid oxygen 11 at substrate 14 and shallow trench upper surface, grid oxygen 11 upper surfaces are equipped with polysilicon 6, and the upper surface of polysilicon 6 is coated with photoresist 7; Wherein, process:

Step 1, to making public of photoresist 7, and the photoresist 7 of the polysilicon 6 of a formation covering device grid;

As shown in Figure 4, step 2 is carried out etching to the polysilicon 6 that is not covered by photoresist 7, and makes polysilicon 6 attenuation that are etched form the residual polysilicon layer 8 of one deck, and the polysilicon 6 that is covered by photoresist 7 forms polysilicon gate 20 after etching;

As shown in Figure 5, step 3 is subdued technology to photoresist 7, makes the area of the area of the photoresist 7 that carried out subduing technology less than polysilicon gate 20;

As shown in Figure 6; Step 4; Through the subduing after the technology of photoresist 7, once more polysilicon gate 20 and residual polysilicon layer 8 are carried out etching, the polysilicon gate 20 that is not covered by photoresist 7 is removed under etching with residual polysilicon layer 8 gradually; Formed residual polysilicon layer 8 stops etching after removing fully in step 2, and forms residue is not thinner than the polysilicon gate 20 that is covered by photoresist 7 by the polysilicon thickness of the polysilicon gate 20 of photoresist 7 coverings polysilicon thickness;

As shown in Figure 7, step 5, the heavy doping injection, annealing, the silicide 10 that after above step, carry out light dope injection, annealing, side wall 9 formation, source electrode 4 and drain electrode 3 form, and interconnected technology.

Wherein shown in Fig. 3-7, further, in the step 2 polysilicon 6 that is not covered by photoresist 7 is carried out etching, the degree of depth of institute's etching was controlled by the time.

Further, in the step 4, the thickness difference between the thickness of the thickness of the polysilicon gate 20 that residue is not covered by photoresist 7 and the polysilicon gate 20 that covered by photoresist 7 is the thickness of residual polysilicon layer 8.

Further, formed side wall 9 is covered in the sidewall of polysilicon gate 20 and the part substrate of contiguous polysilicon gate 20 in the said step 5.

In specific embodiment of the present invention, for example, in 0.3 micron buoyancy aid dynamic random access memory technology; The thickness of polysilicon is 180 nanometers, at first is that polysilicon is carried out etching technics, etches away the polysilicon of 150 nanometers; And make the polysilicon attenuation that is etched form the residual polysilicon layer of one deck; Utilize then and subdue technology, 10 nanometers are subdued on the every limit of photoresist, make and carried out subduing the area of the photoresist area of technology less than polysilicon gate; Pass through the second time then to polysilicon gate etching, the residual polysilicon layer of the formed one deck of original polysilicon attenuation is etched away.Can polysilicon gate near source electrode and drain region 10 nanometer range in; Formation is than the polysilicon gate zone of thin about 30 nanometers in center; Drain electrode is able to strengthen with the longitudinal electric field of source electrode in this zone; Charge carrier is swept substrate under stronger electric field, thereby has increased substrate current, has improved the write performance that attaches body dynamic random memory cell.

In sum; Invent a kind of grid lithographic method that improves buoyancy aid DRAM cell performance; The polysilicon gate thickness that effectively utilized attenuate source electrode and drain electrode end is contiguous; When making voltage be added on the polysilicon gate, the longitudinal electric field intensity in source electrode and the drain electrode two ends raceway groove increases, thereby has improved the write capability of floater effect memory cell.

More than to the invention specific embodiment be described.It will be appreciated that invention is not limited to above-mentioned specific implementations, equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Those skilled in the art can make various distortion or modification within the scope of the claims, and this does not influence the essence of an invention content.

Claims

1. grid lithographic method that improves buoyancy aid DRAM cell performance; Comprise: cover the aerobic buried regions on the substrate, and on the oxygen buried regions, be provided with drain electrode and source electrode, and the device channel that forms between drain electrode and the source electrode; Upper surface at said device channel, drain electrode and source electrode is equipped with polysilicon; The upper surface of said polysilicon is coated with photoresist, it is characterized in that process:

2. process according to claim 1 is characterized in that, to not carried out etching by the polysilicon that photoresist covered, the degree of depth of institute's etching was controlled by the time in the said step 2.

3. process according to claim 1; It is characterized in that; In the said step 4, residue is the residual polysilicon layer thickness that step 2 forms not by the polysilicon gate segment thickness of photoresist covering and by the thickness difference between the polysilicon gate thickness that photoresist covered.

4. process according to claim 1 is characterized in that the part substrate that formed side wall is covered in the polysilicon sidewall and is close to polysilicon in the said step 5.