CN102437036B

CN102437036B - Gate etching method capable of enhancing performance of floating body dynamic random access memory unit

Info

Publication number: CN102437036B
Application number: CN201110265311.7A
Authority: CN
Inventors: 俞柳江
Original assignee: Shanghai Huali Microelectronics Corp
Current assignee: Shanghai Huali Microelectronics Corp
Priority date: 2011-09-08
Filing date: 2011-09-08
Publication date: 2014-03-12
Anticipated expiration: 2031-09-08
Also published as: CN102437036A

Abstract

The invention relates to a gate etching method capable of enhancing performance of a floating body dynamic random access memory unit, and the method comprises the following steps: exposing a photoresist, carrying out primary etching on polycrystalline silicon uncovered by the photoresist, and thinning the etched polycrystalline silicon to form a residual polycrystalline silicon layer; carrying out a reduction technique on the photoresist, so that the area of the photoresist subjected to the reduction technique is less than that of the polycrystalline silicon gate; and after the photoresist reduction technique, etching the polycrystalline silicon gate again to gradually remove the polycrystalline silicon gate under the etching action of the part of polycrystalline silicon gate uncovered by the photoresist, and stopping etching when the previously formed residual polycrystalline silicon layer is completely removed, wherein the thickness of the residual polycrystalline silicon gate uncovered by the photoresist is less than that of the polycrystalline silicon gate covered by the photoresist. The method provided by the invention be used for effectively utilizing the reduced thickness of the polycrystalline silicon gate adjacent to the source and drain ends, so that the intensity of the longitudinal electric field in the channel between the two ends of the source and drain is increased when a voltage is applied to the polycrystalline silicon gate, thereby enhancing the write-in capacity of the floating body effect memory unit.

Description

A kind of grid lithographic method that improves buoyancy aid DRAM cell performance

Technical field

The present invention relates to a kind of technique processing method, relate in particular to a kind of grid lithographic method that improves buoyancy aid DRAM cell performance.

Background technology

The development of embedded Dynamic Access Technology has made large capacity dynamic random access memory (Dynamic Random Access Memory is called for short DRAM) very general in current system level chip (System on a Chip is called for short SOC).The large embedded dynamic memory of capacity (Embedded Dynamic RAM is called for short EDRAM) has brought to SOC can only be by the various benefits that adopt embedded technology realize such as improving bandwidth and reduction power consumption etc.

Each memory cell of the embedded dynamic memory of tradition (EDRAM) is except transistor, also need a deep trench capacitor structure, the deep trench of capacitor makes its width of aspect ratio of memory cell much larger, cause manufacturing process difficulty, and its manufacture craft and cmos vlsi technique are very incompatible, so limited its application in embedded system chip (SOC).

Floater effect memory cell (Floating Body Cell is called for short FBC) is a kind of dynamic memory that is hopeful to substitute EDRAM.FBC utilizes floater effect (Floating Body Effect, abbreviation FBE) DRAM cell, its principle is to utilize silicon-on-insulator (Silicon on Insulator, abbreviation SOI) floater effect that in device, the buffer action of oxygen buried regions (BOX) is brought, using segregate buoyancy aid (Floating Body) as memory node, realize one writing and write " 0 ".

Fig. 1-2 is the operation principle schematic diagram of floater effect memory cell in background technology of the present invention.As shown in Figure 1, take NMOS as example, by the source electrode of device (S) 4 ground connection, grid (G) 12 and drain electrode (D) 3 ends add positive bias V(+), this break-over of device; Due to transverse electric field effect, electronics drain electrode 3 near and silicon atom ionization by collision, produce electron hole pair, part hole is swept substrate 14 by longitudinal electric field, forms substrate current, due to the existence of aerobic buried regions 2, substrate current cannot discharge, make hole at buoyancy aid, gather (△ Q), be defined as the first store status, i.e. one writing; As shown in Figure 2, on grid (G) 12, apply positive bias, in drain electrode 3, apply back bias voltage, by PN junction forward bias, launch from buoyancy aid in hole, is defined as the second store status, writes " 0 ".Due to gathering of substrate electric charge, can change the threshold voltage (Vt) of device, can by this two states of big or small perception of electric current, cause the difference of threshold voltage, realize read operation.Because floater effect memory cell has been removed the capacitor in traditional DRAM, make its technological process completely and CMOS process compatible, simultaneously can the higher memory of component density, be therefore hopeful to substitute existing traditional E DRAM and be applied in embedded system chip.

Floater effect memory cell is when one writing, and in the process that charge carrier gathers at substrate, the speed of one writing is to be determined by the size of substrate current.Improve the substrate current of floater effect memory cell, just can improve the writing speed of floater effect memory cell, thereby improve the performance of floater effect memory cell.

Summary of the invention

Disclosure of the invention a kind of grid lithographic method that improves buoyancy aid DRAM cell performance, in order to improve the writing speed of floater effect memory cell.

For achieving the above object, the technical scheme that invention adopts is:

A kind of grid lithographic method that improves buoyancy aid DRAM cell performance, comprise: on substrate, cover aerobic buried regions, and on oxygen buried regions, be provided with drain electrode and source electrode, and the device channel forming between drain electrode and source electrode, upper surface at described device channel, drain electrode and source electrode is equipped with polysilicon, the upper surface of described polysilicon is coated with photoresist, wherein, and process:

Step 1, exposing, developing, the photoresist of the polysilicon gate of a formation covering device grid photoresist;

Step 2, to not carried out etching by the polysilicon that photoresist covered, and makes the polysilicon attenuation being etched form the residual polysilicon layer of one deck;

Step 3, subdues technique to described photoresist, and the area that makes to carry out to subdue the photoresist of technique is less than the area of polysilicon gate;

Step 4, through described photoresist subdue technique after, again polysilicon is carried out to etching, make by the polysilicon gate that photoresist covered, under etching, not to be removed gradually, until formed residual polysilicon layer stops etching after removing completely in step 2, and formation residue polysilicon gate segment thickness not covered by photoresist is thinner than the polysilicon gate thickness being covered by photoresist;

Step 5, the heavy doping injection, annealing, the Formation of silicide that after above step, carry out light dope injection, annealing, side wall formation, source electrode and drain electrode, and interconnected technique.

Above-mentioned process, wherein, in described step 2, to not carried out etching by the polysilicon that photoresist covered, the degree of depth of institute's etching was controlled by the time.

Above-mentioned process, wherein, in described step 4, remains polysilicon gate segment thickness not covered by photoresist and is the residual polysilicon layer thickness that step 2 forms by the thickness difference between the polysilicon gate thickness that photoresist covered.

Above-mentioned process, wherein, in described step 5, formed side wall is covered in the part substrate of polysilicon sidewall and contiguous polysilicon.

The grid lithographic method of raising buoyancy aid DRAM cell performance of the present invention, its effect is:

1, the polycrystalline silicon etching process after improving, attenuate the polysilicon thickness that is close to of source electrode and drain electrode end;

2,, because the polysilicon of source electrode and drain electrode end is thinner, when voltage is added in polysilicon and extremely goes up, source electrode can increase with the longitudinal electric field intensity in the raceway groove of drain electrode two ends;

3, in device channel, the hole-electron pair that ionization by collision produces under transverse electric field effect, charge carrier is swept substrate by stronger longitudinal electric field, and substrate current is strengthened, thereby has improved the write capability of floater effect memory cell.

Accompanying drawing explanation

By reading the detailed description of non-limiting example being done with reference to following accompanying drawing, the further feature of invention, it is more obvious that object and advantage will become.

The operation principle schematic diagram of floater effect memory cell in Fig. 1-2 background technology of the present invention;

Schematic cross-section after a kind of photoresist that improves the grid lithographic method of buoyancy aid DRAM cell performance of Fig. 3 the present invention exposes.

Fig. 4 be a kind of grid lithographic method that improves buoyancy aid DRAM cell performance of the present invention for the first time to the schematic cross-section after etching polysilicon;

Fig. 5 is the schematic cross-section after photoresist of subduing of a kind of grid lithographic method that improves buoyancy aid DRAM cell performance of the present invention;

Fig. 6 be a kind of grid lithographic method that improves buoyancy aid DRAM cell performance of the present invention for the second time polysilicon is carried out the schematic diagram of etching;

Fig. 7 is a kind of device schematic cross-section finally completing that improves the grid lithographic method of buoyancy aid DRAM cell performance of the present invention.

Referring to figure order: bottom silicon 1, oxygen buried regions 2, drain 3, source electrode 4, device channel 5, polysilicon 6, photoresist 7, residual polysilicon layer 8, side wall 9, silicide 10, grid oxygen 11, grid (G) 12, substrate 14, polysilicon gate 20.

Embodiment

For technological means that invention is realized, create feature, reach object and effect is easy to understand, lower combination specifically illustrates, and further sets forth the present invention.

Please refer to shown in Fig. 3, a kind of grid lithographic method that improves buoyancy aid DRAM cell performance, comprise: on bottom silicon 1, cover aerobic buried regions 2, and on oxygen buried regions 2, be provided with shallow trench (STI), shallow trench bottom joins with oxygen buried regions 2, it between shallow trench, is substrate 14, at substrate 14 and shallow trench upper surface, be equipped with grid oxygen 11, grid oxygen 11 upper surfaces are equipped with polysilicon 6, and the upper surface of polysilicon 6 is coated with photoresist 7, wherein, process:

Step 1, to exposing of photoresist 7, and the photoresist 7 of the polysilicon 6 of a formation covering device grid;

As shown in Figure 4, step 2, carries out etching to the polysilicon 6 not covered by photoresist 7, and makes polysilicon 6 attenuation that are etched form the residual polysilicon layer 8 of one deck, and the polysilicon 6 being covered by photoresist 7 forms polysilicon gate 20 after etching;

As shown in Figure 5, step 3, subdues technique to photoresist 7, and the area that makes to carry out to subdue the photoresist 7 of technique is less than the area of polysilicon gate 20;

As shown in Figure 6, step 4, through photoresist 7 subdue technique after, again polysilicon gate 20 and residual polysilicon layer 8 are carried out to etching, the polysilicon gate 20 and the residual polysilicon layer 8 that by photoresist 7, are not covered are removed gradually under etching, until formed residual polysilicon layer 8 stops etching after removing completely in step 2, and the polysilicon thickness that forms the polysilicon gate 20 that residue do not cover by photoresist 7 is thinner than the polysilicon thickness of the polysilicon gate 20 being covered by photoresist 7;

As shown in Figure 7, step 5, the heavy doping injection, annealing, the silicide 10 that after above step, carry out light dope injection, annealing, side wall 9 formation, source electrode 4 and drain electrode 3 form, and interconnected technique.

Wherein, as shown in Fig. 3-7, further, in step 2, the polysilicon 6 not covered by photoresist 7 is carried out to etching, the degree of depth of institute's etching was controlled by the time.

Further, in step 4, the thickness difference between the thickness of the polysilicon gate 20 that residue is not covered by photoresist 7 and the thickness of the polysilicon gate 20 being covered by photoresist 7 is the thickness of residual polysilicon layer 8.

Further, in described step 5, formed side wall 9 is covered in the sidewall of polysilicon gate 20 and the part substrate of contiguous polysilicon gate 20.

In specific embodiments of the invention, for example, in 0.3 micron of buoyancy aid dynamic random access memory technique, the thickness of polysilicon is 180 nanometers, first be that polysilicon is carried out to etching technics, etch away the polysilicon of 150 nanometers, and make the polysilicon attenuation being etched form the residual polysilicon layer of one deck, then utilize and subdue technique, 10 nanometers are subdued in the every limit of photoresist, the photoresist area that makes to carry out to subdue technique is less than the area of polysilicon gate, then pass through for the second time to polysilicon gate etching, the residual polysilicon layer of the formed one deck of original polysilicon attenuation is etched away.Can polysilicon gate near source electrode and drain region 10 nanometer range in, formation is than the polysilicon gate region of thin approximately 30 nanometers in center, in this region, drain electrode is strengthened with the longitudinal electric field of source electrode, charge carrier is swept substrate under stronger electric field, thereby increased substrate current, improved the write performance of attached body dynamic random memory cell.

In sum, invent a kind of grid lithographic method that improves buoyancy aid DRAM cell performance, the polysilicon gate thickness that the source electrode that effectively utilized attenuate and drain electrode end are contiguous, while making voltage be added on polysilicon gate, source electrode increases with the longitudinal electric field intensity in the raceway groove of drain electrode two ends, thereby has improved the write capability of floater effect memory cell.

Above the specific embodiment of invention is described.It will be appreciated that, invention is not limited to above-mentioned specific implementations, and the equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Those skilled in the art can make various distortion or modification within the scope of the claims, and this does not affect essence of an invention content.

Claims

1. a grid lithographic method that improves buoyancy aid DRAM cell performance, comprise: on substrate, cover aerobic buried regions, and on oxygen buried regions, be provided with drain electrode and source electrode, and the device channel forming between drain electrode and source electrode, upper surface at described device channel, drain electrode and source electrode is equipped with polysilicon, the upper surface of described polysilicon is coated with photoresist, it is characterized in that process:

2. the grid lithographic method of raising buoyancy aid DRAM cell performance according to claim 1, is characterized in that, in described step 2, to not carried out etching by the polysilicon that photoresist covered, the degree of depth of institute's etching was controlled by the time.

3. the grid lithographic method of raising buoyancy aid DRAM cell performance according to claim 1, it is characterized in that, in described step 4, remain polysilicon gate segment thickness not covered by photoresist and be the residual polysilicon layer thickness that step 2 forms by the thickness difference between the polysilicon gate thickness that photoresist covered.

4. the grid lithographic method of raising buoyancy aid DRAM cell performance according to claim 1, is characterized in that the part substrate that in described step 5, formed side wall is covered in polysilicon sidewall and is close to polysilicon.