CN102437124B

CN102437124B - Method for increasing writing speed of floating body effect storage unit and semiconductor device

Info

Publication number: CN102437124B
Application number: CN201110366188.8A
Authority: CN
Inventors: 俞柳江; 周军
Original assignee: Shanghai Huali Microelectronics Corp
Current assignee: Shanghai Huali Microelectronics Corp
Priority date: 2011-11-17
Filing date: 2011-11-17
Publication date: 2014-01-08
Anticipated expiration: 2031-11-17
Also published as: CN102437124A

Abstract

The invention provides a method for increasing the writing speed of a floating body effect storage unit and an intermediate transitional semiconductor device, belonging to the technical field of semiconductor manufacturing. The core of the invention is as follows: when a side wall material is deposited, an included angle between the introduction direction of reactant plasma and the surface of a substrate in a source position is less than 90 DEG, and an included angle between the introduction direction of the reactant plasma and the surface of a substrate in a drain position is more than 90 DEG; the side wall material is etched, side walls are formed at two sides of a gate, and the width of the side wall close to a source is more than that of the side wall close to a drain; taking the side walls as masks, heavy doping and annealing processes are carried out to form the source and the drain, and a distance between doped ions of the drain and a channel is closer and a distance between doped ions of the source and the channel as well as the substrate is further. According to the invention, on the one hand, the longitudinal electric field in the drain channel is enhanced and the substrate current is increased, on the other hand, the leakage speed of accumulated carriers from the source is reduced, and therefore the writing speed of the floating body effect storage unit is increased.

Description

Improve method and the semiconductor device of floater effect memory cell writing speed

Technical field

The present invention relates to technical field of manufacturing semiconductors, especially a kind of manufacture method and middle transition semiconductor device that can improve floater effect memory cell writing speed.

Background technology

The development of embedded Dynamic Access Technology has made jumbo dynamic random access memory (Dynamic Random Access Memory, i.e. DRAM) very general in current system level chip (System on a Chip, i.e. SoC).Large capacity embedded type dynamic random access memory has brought to SoC can only be by the various benefits that adopt embedded technology realize such as improving bandwidth and reduction power consumption etc.Tradition embedded type dynamic random access memory (embbeded Dynamic Random Access Memory, be eDRAM) each memory cell except transistor, also need a deep trench capacitor structure, the deep trench of capacitor makes its width of aspect ratio of memory cell much larger, causes the manufacturing process difficulty.Its manufacture craft and cmos vlsi technique are very incompatible, have limited its application in embedded system chip (SoC).

Floater effect memory cell (Floating Body Cell, i.e. FBC) is a kind of dynamic random access memory that is hopeful to substitute eDRAM.FBC utilizes floater effect (Floating Body Effect, be FBE) DRAM cell, its principle is to utilize silicon-on-insulator (Silicon on Insulator, be SOI) buffer action of oxygen buried regions (BOX) is brought in device floater effect, using segregate buoyancy aid (Floating Body) as memory node, realize one writing and write " 0 ".

Figure 1A～1B is the operation principle schematic diagram of FBC.Take NMOS as example in Figure 1A, at grid (G) and drain electrode (D) end, add positive bias, break-over of device, due to the transverse electric field effect, electronics the drain electrode near with the silicon atom ionization by collision, the generation electron hole pair, a part of hole is swept substrate by longitudinal electric field, form substrate current, due to the existence of aerobic buried regions, substrate current can't discharge, and makes hole gather at buoyancy aid, be defined as the first store status, may be defined as one writing.Write the situation of " 0 " as shown in Figure 1B, apply positive bias on grid, in drain electrode, apply back bias voltage, by the PN junction forward bias, launch from buoyancy aid in hole, is defined as the second store status.Due to gathering of substrate electric charge, can change the threshold voltage (Vt) of device, can cause the difference of threshold voltage by this two states of big or small perception of electric current, realize read operation.Because the floater effect memory cell has been removed the capacitor in traditional DRAM, make its technological process fully and the CMOS process compatible, simultaneously can the higher memory of component density, therefore be hopeful to substitute existing traditional eDRAM and be applied in embedded system chip.

The floater effect memory cell is when one writing, and charge carrier gathers at substrate on one side, on one side can be from source electrode leakage slowly, the inventor thinks, the speed that writes (" 1 ") of floater effect memory cell need to improve.

Summary of the invention

The objective of the invention is to improve the writing speed of floater effect memory cell.

At first the present invention proposes a kind of manufacture method that can improve the writing speed of floater effect memory cell, comprises the following steps:

Step 1: bottom silicon is provided, be formed with oxygen buried layer on described bottom silicon, be formed with substrate on described oxygen buried layer, be formed with successively gate oxide and grid on described substrate, form raceway groove in the substrate of described grid below, in described grid and gate oxide surface and substrate surface deposition spacer material, in the process of spacer material deposition, the angle of the substrate surface of the incoming direction of reactant plasma and source electrode position is less than 90 degree, and be greater than 90 degree with the angle of drain locations substrate surface, make near the spacer material thickness on the gate lateral wall of source electrode position and surpass near the spacer material on the gate lateral wall of drain locations,

Step 2: spacer material is carried out to etching, at grid and gate oxide both sides, form side wall, and the width of the side wall of close source electrode position is greater than the width near the side wall of drain locations;

Step 3: take described side wall as mask, carry out heavy doping and annealing process, form source electrode and drain electrode in the substrate of grid both sides.

Secondly the present invention also proposes a kind of intermediate semiconductor device of floater effect memory cell, comprise bottom silicon, be formed on the oxygen buried layer on bottom silicon, be formed on the substrate on oxygen buried layer, be formed on successively gate oxide and grid on substrate, be deposited on the spacer material of grid and gate oxide surface and substrate surface, wherein: surpass near the spacer material on the gate lateral wall of drain locations near the spacer material thickness on the gate lateral wall of source electrode position.

The present invention is by the spacer material deposition process, the reactant plasma is introduced at oblique angle, make post-depositional film, spacer material on the drain terminal sidewall is thinner, spacer material on the source sidewall is thicker, make after the side wall etching technics, the lateral wall width of drain terminal reduces, and the lateral wall width of source increases, after heavy doping injection and annealing process are leaked in ensuing source, the doping ion of drain terminal is furthered from channel distance, the distance of the doping ion of source and raceway groove and substrate is zoomed out, improved on the one hand the longitudinal electric field in the drain terminal raceway groove, increased substrate current, reduced on the other hand and gathered the leakage rate of charge carrier from source, thereby improved the writing speed of floater effect memory cell.

The accompanying drawing explanation

By the more specifically explanation of the preferred embodiments of the present invention shown in accompanying drawing, above-mentioned and other purpose of the present invention, Characteristics and advantages will be more clear.In whole accompanying drawings, identical Reference numeral is indicated identical part.Deliberately by actual size equal proportion convergent-divergent, do not draw accompanying drawing, focus on illustrating purport of the present invention.

Figure 1A is the process to floater effect memory cell one writing;

Figure 1B is for writing the process of " 0 " to the floater effect memory cell;

The side wall forming process schematic diagram that Fig. 2 A～2C is traditional floater effect memory cell;

The side wall forming process schematic diagram that Fig. 3 A～3C is floater effect memory cell of the present invention.

Embodiment

Usually in technique, the side wall of floater effect memory cell forms (deposition and etching) process as shown in Fig. 2 A～2C.

At first be the spacer material deposition, after deposition, the cross section of device as shown in Figure 2 A.Floater effect memory cell in figure comprises bottom silicon 10, and described bottom silicon 10 is for example silicon-on-insulator; Be formed on oxygen buried layer 20 on bottom silicon 10; Be formed on the substrate 30 on oxygen buried layer 20, described substrate 30 can be silicon substrate, and certainly under some occasion, germanium substrate, silicon-Germanium substrate or other semi-conducting material also can be suitable for; Be formed on the shallow ditch non-intercommunicating cells 31 (shallow trench isolation, i.e. STI) in substrate 30, for each floater effect memory cell is kept apart; Be formed on successively gate oxide 41 and grid 42 on substrate 30, be arranged in the raceway groove of the substrate 30 of grid 42 belows; Be formed on source electrode light doping section 43 and drain electrode light doping section 45 in the substrate 30 of grid 42 both sides; Be deposited on the spacer material 470 on described grid 42 and gate oxide 41 surfaces and substrate 30 surfaces, described spacer material 470 is symmetrically distributed in two relative sides of grid 42.

Next, adopt anisotropic dry etch process, spacer material 470 is returned to quarter, return after having carved the symmetrical side wall 47 of formation on the side relative with two of gate oxide 41 at grid 42, as shown in Fig. 2 B.

Then be source, leak heavy doping and annealing process, the described side wall 47 of take is mask, and substrate 30 is carried out to heavy doping, forms source electrode 44 and drain electrode 46, as shown in Figure 2 C.In the present embodiment, the doping ionic distance device channel in source electrode 44 and drain electrode 46 apart from d, by the width of side wall 47, determined.

Return Figure 1A, the known speed to floater effect memory cell one writing is to be determined from the speed of source leakage is common by the size of substrate current and the charge carrier that gathers.By improving the substrate current of floater effect memory cell, just can improve the writing speed of floater effect memory cell.In addition, the charge carrier that the minimizing substrate gathers, from source leakage, also can reach the purpose that improves floater effect memory cell writing speed.Based on above theory, the inventor proposes to improve to existing floater effect memory cell, makes it have the drain electrode lateral wall width and the source electrode lateral wall width of increase reduced, and then raising memory cell writing speed.The technological process adopted is as shown in Fig. 3 A～3C.

At first, step 1, preparation middle transition device, comprise bottom silicon 10, be formed on the oxygen buried layer 20 on bottom silicon 10, be formed on the substrate 30 on oxygen buried layer 20, be formed on the shallow ditch non-intercommunicating cells 31 (optional) in substrate 30, be formed on successively gate oxide 41 and grid 42 on substrate 30, be arranged in the raceway groove of the substrate 30 of grid 42 belows, be formed on source electrode light doping section 43 and drain electrode light doping section 45 (optional) in the substrate 30 of grid 42 both sides.

Referring to Fig. 3 A, above-mentioned intermediary device is carried out to spacer material 470 depositions.As shown in the figure, in the process of spacer material deposition, the reactant plasma is introduced at oblique angle, and the angle on substrate 30 surfaces of the incoming direction of reactant plasma and source electrode position is less than 90 degree, and is greater than 90 degree with the angle on drain locations substrate 30 surfaces.The incoming direction of plasma is to the source electrode inclined position, therefore near forming thicker spacer material 470 on the gate lateral wall of source electrode position, simultaneously near forming thinner spacer material 470 on the gate lateral wall of drain locations.

Next, step 2, carry out dry etching to spacer material 470, and the plasma that etching adopts is vertical with substrate surface, in grid 42 and the both sides of gate oxide 41, forms side wall 471,472, and after etching, the cross section of device as shown in Figure 3 B.Because the spacer material 470 of the gate lateral wall of drain locations is thinner, near side wall 472 width of drain locations, can reduce; Because the spacer material 470 on the gate lateral wall of source electrode position is thicker, side wall 471 width of close source electrode position can increase.Be about 1.1～3 times near the width of the side wall 472 of drain locations near side wall 471 width of source electrode position, corresponding, in step 1, the angle on substrate 30 surfaces of the incoming direction of reactant plasma and source electrode position is that 30 degree～85 are spent.

Then, step 3, the described side wall 471,472 of take is mask, carries out heavy doping and annealing process, forms source electrode 44 and drain 46 in the substrate 30 of grid 42 both sides.Because the width apart from by side wall of doping ion and device channel is determined, therefore after heavy doping, the distance of the doping ion of drain electrode 46 and device channel is furthered, the distance of the doping ion of source electrode 44 and device channel is zoomed out, be that the doping ion of source electrode and the distance between substrate are also zoomed out, as shown in Figure 3 C.

Therefore, shown in figure 3C, on the one hand, due to drain electrode 46 doping ion and device channel apart from being furthered, thereby improved the longitudinal electric field in the drain channel, the electron hole pair that the carrier impact of being accelerated by transverse electric field produces, hole can be swept substrate 30 under stronger longitudinal electric field effect, has increased substrate current; On the other hand, the distance of the doping ion of source electrode 44 and device substrate 30 is zoomed out, thereby reduced, gathers the leakage rate of charge carrier from source electrode 44.So the present invention forms technique by improving side wall, has improved the writing speed of floater effect memory cell.

Although the present invention with preferred embodiment openly as above; but it is not for limiting claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that the claims in the present invention were defined.

Claims

1. a manufacture method that improves floater effect memory cell writing speed comprises the following steps:

2. the method for claim 1, is characterized in that: in step 1, also form shallow ditch non-intercommunicating cells in described substrate.

3. the method for claim 1, is characterized in that: in step 1, also form source electrode light doping section and drain electrode light doping section in the substrate of grid both sides.

4. the method for claim 1 is characterized in that: in step 1, the angle of the substrate surface of the incoming direction of reactant plasma and source electrode position is 30 degree～85 degree.

5. the method for claim 1 is characterized in that: in step 2, and 1.1～3 times of the width of the side wall that the width of the described side wall near the source electrode position be close drain locations.

6. a semiconductor device, comprise bottom silicon, be formed on the oxygen buried layer on bottom silicon, be formed on the substrate on oxygen buried layer, be formed on successively gate oxide and grid on substrate, be deposited on the spacer material of grid and gate oxide surface and substrate surface, it is characterized in that: surpass near the spacer material on the gate lateral wall of drain locations near the spacer material thickness on the gate lateral wall of source electrode position.