CN102437124A

CN102437124A - Method for increasing writing speed of floating body effect storage unit and semiconductor device

Info

Publication number: CN102437124A
Application number: CN2011103661888A
Authority: CN
Inventors: 俞柳江; 周军
Original assignee: Shanghai Huali Microelectronics Corp
Current assignee: Shanghai Huali Microelectronics Corp
Priority date: 2011-11-17
Filing date: 2011-11-17
Publication date: 2012-05-02
Anticipated expiration: 2031-11-17
Also published as: CN102437124B

Abstract

The invention provides a method for increasing the writing speed of a floating body effect storage unit and an intermediate transitional semiconductor device, belonging to the technical field of semiconductor manufacturing. The core of the invention is as follows: when a side wall material is deposited, an included angle between the introduction direction of reactant plasma and the surface of a substrate in a source position is less than 90 DEG, and an included angle between the introduction direction of the reactant plasma and the surface of a substrate in a drain position is more than 90 DEG; the side wall material is etched, side walls are formed at two sides of a gate, and the width of the side wall close to a source is more than that of the side wall close to a drain; taking the side walls as masks, heavy doping and annealing processes are carried out to form the source and the drain, and a distance between doped ions of the drain and a channel is closer and a distance between doped ions of the source and the channel as well as the substrate is further. According to the invention, on the one hand, the longitudinal electric field in the drain channel is enhanced and the substrate current is increased, on the other hand, the leakage speed of accumulated carriers from the source is reduced, and therefore the writing speed of the floating body effect storage unit is increased.

Description

Improve the method and the semiconductor device of floater effect memory cell writing speed

Technical field

The present invention relates to technical field of manufacturing semiconductors, the especially a kind of manufacturing approach and middle transition semiconductor device that can improve floater effect memory cell writing speed.

Background technology

The development of embedded dynamic memory technology has made jumbo dynamic random access memory (Dynamic Random Access Memory, i.e. DRAM) very general in present system level chip (System on a Chip, i.e. SoC).Big capacity embedded type dynamic random access memory has brought to SoC can only be through the various benefits that adopt embedded technology to realize such as improving bandwidth and reduction power consumption etc.Tradition embedded type dynamic random access memory (embbeded Dynamic Random Access Memory; Be eDRAM) each memory cell except transistor; Also need a deep trench capacitor structure; The deep trench of capacitor makes that its width of aspect ratio of memory cell is a lot of greatly, causes the manufacturing process difficulty.Its manufacture craft and cmos vlsi technology are very incompatible, have limited its application in embedded system chip (SoC).

Floater effect memory cell (Floating Body Cell, i.e. FBC) is a kind of dynamic random access memory that is hopeful to substitute eDRAM.FBC utilizes floater effect (Floating Body Effect; Be FBE) DRAM cell; Its principle is to utilize silicon-on-insulator (Silicon on Insulator; Be SOI) buffer action of oxygen buried regions (BOX) is brought in the device floater effect, segregate buoyancy aid (Floating Body) as memory node, is realized one writing and write " 0 ".

Figure 1A～1B is the operation principle sketch map of FBC.In Figure 1A, be example with NMOS, add positive bias at grid (G) and drain electrode (D) end, break-over of device is because the transverse electric field effect; Electronics the drain electrode near with the silicon atom ionization by collision, the generation electron hole pair, a part of hole is swept substrate by longitudinal electric field; Form substrate current, because the existence of aerobic buried regions, substrate current can't discharge; Make the hole gather, be defined as first kind of store status, may be defined as one writing at buoyancy aid.The situation of writing " 0 " applies positive bias on grid shown in Figure 1B, in drain electrode, apply back bias voltage, and through the PN junction forward bias, launch from buoyancy aid in the hole, is defined as second kind of store status.Because gathering of substrate electric charge can change the threshold voltage (Vt) of device, can cause the difference of threshold voltage through this two states of big or small perception of electric current, promptly realizes read operation.Because the floater effect memory cell has been removed the capacitor among traditional DRAM; Make its technological process fully and the CMOS process compatible; Simultaneously can the higher memory of component density, therefore be hopeful to substitute existing traditional eDRAM and be applied in the embedded system chip.

The floater effect memory cell is when one writing, and charge carrier gathers at substrate on one side, on one side can be from source electrode leakage slowly, the inventor thinks that the speed that writes (" 1 ") of floater effect memory cell is still waiting to improve.

Summary of the invention

The objective of the invention is to improve the writing speed of floater effect memory cell.

The present invention at first proposes a kind of manufacture method that can improve the writing speed of floater effect memory cell, may further comprise the steps:

Step 1: bottom silicon is provided; Be formed with oxygen buried layer on the said bottom silicon, be formed with substrate on the said oxygen buried layer, be formed with gate oxide and grid on the said substrate successively; Form raceway groove in the substrate of said grid below; In said grid and gate oxide surface and substrate surface deposition spacer material, in the process of spacer material deposition, the angle of the substrate surface of the incoming direction of reactant plasma and source electrode position is less than 90 degree; And spend greater than 90 with the angle of drain locations substrate surface, make to surpass near the spacer material on the gate lateral wall of drain locations near the spacer material thickness on the gate lateral wall of source electrode position;

Step 2: spacer material is carried out etching, forms side wall in grid and gate oxide both sides, and near the width of the side wall of source electrode position greater than width near the side wall of drain locations;

Step 3: with said side wall is mask, carries out heavy doping and annealing process, in the substrate of grid both sides, forms source electrode and drain electrode.

Secondly the present invention also proposes a kind of intermediate semiconductor device of floater effect memory cell; Comprise bottom silicon; Be formed on the oxygen buried layer on the bottom silicon, be formed on the substrate on the oxygen buried layer, be formed on gate oxide and grid on the substrate successively; Be deposited on the spacer material of grid and gate oxide surface and substrate surface, wherein: surpass near the spacer material on the gate lateral wall of drain locations near the spacer material thickness on the gate lateral wall of source electrode position.

The present invention is through in the spacer material deposition process, and the reactant plasma is introduced at the oblique angle, makes post-depositional film; Spacer material on the drain terminal sidewall is thinner, and the spacer material on the distolateral wall in source is thicker, makes through behind the side wall etching technics; The lateral wall width of drain terminal reduces, and the lateral wall width of source end increases, after heavy doping injection and annealing process are leaked in ensuing source; The dopant ion of drain terminal is furthered from channel distance; The distance of the dopant ion of source end and raceway groove and substrate is zoomed out, and has improved the longitudinal electric field in the drain terminal raceway groove on the one hand, has increased substrate current; Reduced the leakage rate that gathers charge carrier end on the other hand, thereby improved the writing speed of floater effect memory cell from the source.

Description of drawings

Through the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, characteristic and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by actual size equal proportion convergent-divergent.

Figure 1A is the process to floater effect memory cell one writing;

Figure 1B is for writing the process of " 0 " to the floater effect memory cell;

Fig. 2 A～2C is the side wall forming process sketch map of traditional floater effect memory cell;

Fig. 3 A～3C is the side wall forming process sketch map of floater effect memory cell of the present invention.

Embodiment

Usually in the technology, the side wall of floater effect memory cell forms (deposition and etching) process shown in Fig. 2 A～2C.

At first be the spacer material deposition, the cross section of deposition back device is shown in Fig. 2 A.Floater effect memory cell among the figure comprises bottom silicon 10, and said bottom silicon 10 for example is silicon-on-insulator; Be formed on oxygen buried layer 20 on the bottom silicon 10; Be formed on the substrate 30 on the oxygen buried layer 20, described substrate 30 can be silicon substrate, and certainly under some occasion, germanium substrate, silicon-Germanium substrate or other semi-conducting material also can be suitable for; Be formed on the shallow ditch non-intercommunicating cells 31 (shallow trench isolation, i.e. STI) in the substrate 30, be used for each floater effect memory cell is kept apart; Be formed on gate oxide 41 and grid 42 on the substrate 30 successively, be arranged in the raceway groove of the substrate 30 of grid 42 belows; Be formed on source electrode light doping section 43 and drain electrode light doping section 45 in the substrate 30 of grid 42 both sides; Be deposited on the spacer material 470 on said grid 42 and gate oxide 41 surfaces and substrate 30 surfaces, said spacer material 470 is symmetrically distributed in two relative sides of grid 42.

Next, adopt anisotropic dry etch process, spacer material 470 is returned quarter, return the side wall 47 that on two relative sides of grid 42 and gate oxide 41, forms symmetry after accomplishing quarter, shown in Fig. 2 B.

Being the source then, leaking heavy doping and annealing process, is mask with said side wall 47, and substrate 30 is carried out heavy doping, forms source electrode 44 and drain electrode 46, shown in Fig. 2 C.In this execution mode, the dopant ion in source electrode 44 and the drain electrode 46 apart from device channel apart from d, determine by the width of side wall 47.

Return Figure 1A, can know that the speed to floater effect memory cell one writing is to be determined from the speed of source leakage is common by the size of substrate current and the charge carrier that gathers.Through improving the substrate current of floater effect memory cell, just can improve the writing speed of floater effect memory cell.In addition, the charge carrier that the minimizing substrate gathers also can reach the purpose that improves floater effect memory cell writing speed from source leakage.Based on above theory, the inventor proposes to improve to existing floater effect memory cell, makes it have the drain electrode lateral wall width and the source electrode lateral wall width of increase that reduces, and then raising memory cell writing speed.The technological process of being adopted is shown in Fig. 3 A～3C.

At first, step 1, preparation middle transition device; Comprise bottom silicon 10, be formed on the oxygen buried layer 20 on the bottom silicon 10, be formed on the substrate 30 on the oxygen buried layer 20; Be formed on the shallow ditch non-intercommunicating cells 31 (optional) in the substrate 30; Be formed on gate oxide 41 and grid 42 on the substrate 30 successively, be arranged in the raceway groove of the substrate 30 of grid 42 belows, be formed on source electrode light doping section 43 and drain electrode light doping section 45 (optional) in the substrate 30 of grid 42 both sides.

Referring to Fig. 3 A, above-mentioned intermediary device is carried out spacer material 470 depositions.As shown in the figure, in the process that spacer material deposits, the reactant plasma is introduced at the oblique angle, and the angles on substrate 30 surfaces of the incoming direction of reactant plasma and source electrode position are spent less than 90, and spend greater than 90 with the angles on drain locations substrate 30 surfaces.The incoming direction of plasma is to the source electrode inclined position, therefore near forming thicker spacer material 470 on the gate lateral wall of source electrode position, simultaneously near forming thin spacer material 470 on the gate lateral wall of drain locations.

Next, step 2 is carried out dry etching to spacer material 470, and the plasma that etching adopts is vertical with substrate surface, and at the both sides formation side wall 471,472 of grid 42 with gate oxide 41, the cross section of device is shown in Fig. 3 B after the etching.Because the spacer material 470 of the gate lateral wall of drain locations is thinner, can reduce near side wall 472 width of drain locations; Because the spacer material 470 on the gate lateral wall of source electrode position is thicker, can increase near side wall 471 width of source electrode position.Be about 1.1～3 times near the width of the side wall 472 of drain locations near side wall 471 width of source electrode position, corresponding, in the step 1, the angles on substrate 30 surfaces of the incoming direction of reactant plasma and source electrode position are that 30 degree～85 are spent.

Then, step 3 is a mask with said side wall 471,472, carries out heavy doping and annealing process, in the substrate 30 of grid 42 both sides, forms source electrode 44 and drains 46.Because the distance of dopant ion and device channel is determined by the width of side wall; Therefore after the heavy doping; The dopant ion of drain electrode 46 and the distance of device channel are furthered; The dopant ion of source electrode 44 and the distance of device channel are zoomed out, and promptly the dopant ion of source electrode and the distance between the substrate are also zoomed out, shown in Fig. 3 C.

Therefore; Shown in figure 3C, on the one hand, because the dopant ion of drain electrode 46 and the distance of device channel are furthered; Thereby improved the longitudinal electric field in the drain channel; The electron hole pair that the carrier impact of being quickened by transverse electric field produces, the hole can be swept substrate 30 under stronger longitudinal electric field effect, increased substrate current; On the other hand, the distance of the dopant ion of source electrode 44 and device substrate 30 is zoomed out, and gathers the leakage rate of charge carrier from source electrode 44 thereby reduced.So the present invention forms technology through improving side wall, has improved the writing speed of floater effect memory cell.

Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting claim; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.

Claims

1. manufacturing approach that improves floater effect memory cell writing speed may further comprise the steps:

2. the method for claim 1 is characterized in that: in the step 1, also form shallow ditch non-intercommunicating cells in the said substrate.

3. the method for claim 1 is characterized in that: in the step 1, also form source electrode light doping section and drain electrode light doping section in the substrate of grid both sides.

4. the method for claim 1 is characterized in that: in the step 1, the angle of the substrate surface of the incoming direction of reactant plasma and source electrode position is 30 degree～85 degree.

5. the method for claim 1 is characterized in that: in the step 2, the width of said side wall near the source electrode position is 1.1～3 times near the width of the side wall of drain locations.

6. semiconductor device; Comprise bottom silicon; Be formed on the oxygen buried layer on the bottom silicon, be formed on the substrate on the oxygen buried layer, be formed on gate oxide and grid on the substrate successively; Be deposited on the spacer material of grid and gate oxide surface and substrate surface, it is characterized in that: surpass near the spacer material on the gate lateral wall of drain locations near the spacer material thickness on the gate lateral wall of source electrode position.