CN102446750A - Spacer etching method for increasing writing speed of floating body dynamic random memory unit - Google Patents
Spacer etching method for increasing writing speed of floating body dynamic random memory unit Download PDFInfo
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- CN102446750A CN102446750A CN2011102652824A CN201110265282A CN102446750A CN 102446750 A CN102446750 A CN 102446750A CN 2011102652824 A CN2011102652824 A CN 2011102652824A CN 201110265282 A CN201110265282 A CN 201110265282A CN 102446750 A CN102446750 A CN 102446750A
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- side wall
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 238000005530 etching Methods 0.000 title claims abstract description 33
- 125000006850 spacer group Chemical group 0.000 title abstract description 7
- 230000008569 process Effects 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000000137 annealing Methods 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 17
- 230000005684 electric field Effects 0.000 abstract description 6
- 150000002500 ions Chemical class 0.000 abstract 2
- 239000000969 carrier Substances 0.000 abstract 1
- 238000002513 implantation Methods 0.000 abstract 1
- 239000002019 doping agent Substances 0.000 description 12
- 239000002800 charge carrier Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000008280 blood Substances 0.000 description 2
- 210000004369 blood Anatomy 0.000 description 2
- 230000005685 electric field effect Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000008447 perception Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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Abstract
The invention discloses a spacer etching method for increasing a writing speed of a floating body dynamic random memory unit. In the spacer etching process, by adopting a method of introducing etching plasma with an oblique angle is adopted, the width of a spacer at an etched drain terminal is reduced, the width of the spacer at a source terminal is increased, after a subsequent source and drain highly-doped implantation and annealing process, the distance of doped ions at the drain terminal to a channel is reduced, the distance of doped ions at a source terminal to the channel and a substrate is increased, on the one hand, a longitudinal electric field in a drain terminal channel is increased, a substrate current is increased, on the other hand, the leakage speed of accumulated carriers through the source terminal is reduced, thus the writing speed of a floating body effect memory unit is increased.
Description
Technical field
The present invention relates to a kind of semiconductor technology, relate in particular to the side wall lithographic method that a kind of raising attaches body dynamic random memory cell writing speed.
Background technology
The development of embedded dynamic memory technology has made big capacity DRAM very general in present system level chip (SOC).The big embedded dynamic memory of capacity (eDRAM) has brought to SoC can only be through the various benefits that adopt embedded technology to realize such as improving bandwidth and reduction power consumption etc.Each memory cell of the embedded dynamic memory of tradition (eDRAM) also needs a deep trench capacitor structure except transistor, the deep trench of capacitor makes that its width of aspect ratio of memory cell is a lot of greatly, causes the manufacturing process difficulty.Its manufacture craft and cmos vlsi technology are very incompatible, have limited its application in embedded system chip (SOC).
Floater effect memory cell (Floating Body Cell, i.e. FBC) is a kind of dynamic memory that is hopeful to substitute eDRAM.FBC utilizes floater effect (Floating Body Effect; Be FBE) DRAM cell; Its principle is to utilize silicon-on-insulator (Silicon on Insulator; Be SOI) buffer action of oxygen buried regions (BOX) is brought in the device floater effect, segregate buoyancy aid (Floating Body) as memory node, is realized one writing and write " 0 ".With NMOS is example, adds positive bias at grid (G) and drain electrode (D) end, and break-over of device is because the transverse electric field effect; Electronics near drain electrode with the silicon atom ionization by collision, produce electron hole pair, a part of hole is swept substrate by longitudinal electric field, the formation substrate current; Because the existence of aerobic buried regions, substrate current can't discharge, and makes the hole gather at buoyancy aid, is defined as first kind of store status; May be defined as one writing, the situation of writing " 0 " does, on grid, applies positive bias, in drain electrode, applies back bias voltage; Through the PN junction forward bias, launch from buoyancy aid in the hole, is defined as second kind of store status.Because gathering of substrate electric charge can change the threshold voltage (Vt) of device, can cause the difference of threshold voltage through this two states of big or small perception of electric current, promptly realizes read operation.Because the floater effect memory cell has been removed the capacitor among traditional DRAM; Make its technological process fully and the CMOS process compatible; Simultaneously can the higher memory of component density, therefore be hopeful to substitute existing traditional eDRAM and be applied in the embedded system chip.
The floater effect memory cell is when one writing, and charge carrier gathers at substrate on one side, on one side can the end leakage slowly from the source.The speed of one writing is by the size of substrate current and the common decision of the charge carrier that the gathers speed that end leaks from the source.Improve the substrate current of floater effect memory cell, just can improve the writing speed of floater effect memory cell.In addition, reduce charge carrier end leakage that substrate gathers, also can reach the purpose that improves floater effect memory cell writing speed from the source.
Summary of the invention
The invention discloses the side wall lithographic method that a kind of raising attaches body dynamic random memory cell writing speed, in order to reach the technique effect that improves floater effect memory cell writing speed.
Above-mentioned effect of the present invention is to realize through following technical scheme:
A kind of raising attaches the side wall lithographic method of body dynamic random memory cell writing speed, on the SOI silicon substrate, is formed with at least one transistor, deposit one side wall layer on transistor; Wherein, may further comprise the steps:
Etching is removed the part side wall layer; The part side wall layer that only keeps the gate lateral wall that covers the first transistor is as gate lateral wall layer; Make the direction of plasma become the α angle in the etching process with vertical silicon chip surface direction; So that the side wall thicknesses of grid both sides is different after the etching, afterwards, carry out the drain-source doping process
Aforesaid raising attaches the side wall lithographic method of body dynamic random memory cell writing speed, wherein, makes after the etching near the width of the grid curb wall layer of drain terminal less than the width near the grid curb wall layer of source end.
Aforesaid raising attaches the side wall lithographic method of body dynamic random memory cell writing speed, wherein, carries out dopant ion and the channel distance of drain terminal behind drain-source doping process dopant ion and the channel distance less than the source end.
Aforesaid raising attaches the side wall lithographic method of body dynamic random memory cell writing speed, wherein, adopts anisotropic dry etching that side wall layer is carried out etching.
Aforesaid raising attaches the side wall lithographic method of body dynamic random memory cell writing speed, wherein, carries out annealing process behind the completion drain-source doping process.
Aforesaid raising attaches the side wall lithographic method of body dynamic random memory cell writing speed, and wherein, the angle at α angle is 15 °.
In sum; The present invention improve attach body dynamic random memory cell writing speed the side wall lithographic method in side wall (Spacer) etching technics, take the oblique angle to introduce the method for etching plasma, make that the lateral wall width of drain terminal reduces after the etching; And the lateral wall width of source end increases; After highly doped injection and annealing process were leaked in ensuing source, the dopant ion of drain terminal was furthered from channel distance, and the distance of the dopant ion of source end and raceway groove and substrate is zoomed out; Improved the longitudinal electric field in the drain terminal raceway groove on the one hand; Increased substrate current, reduced the leakage rate that gathers charge carrier end on the other hand, thereby improved the writing speed of floater effect memory cell from the source.
Description of drawings
Through reading the detailed description of non-limiting example being done with reference to following accompanying drawing, it is more obvious that the present invention and characteristic thereof, profile and advantage will become.Mark identical in whole accompanying drawings is indicated identical part.Painstakingly proportionally do not draw accompanying drawing, focus on illustrating purport of the present invention.
Fig. 1 is the post-depositional sketch map of side wall of the prior art;
Fig. 2 is the sketch map after the completion side wall etching in the prior art;
Fig. 3 is that the sketch map after forming is leaked in the source in the prior art;
Fig. 4 is the sketch map after the present invention improves the oblique angle etching side wall of the side wall lithographic method that attaches body dynamic random memory cell writing speed;
Fig. 5 is the sketch map after completion source that the present invention improves the side wall lithographic method that attaches body dynamic random memory cell writing speed leak to be injected.
Embodiment
Be further described below in conjunction with the accompanying drawing specific embodiments of the invention:
A kind of raising attaches the side wall lithographic method of body dynamic random memory cell writing speed, and Fig. 1 is the post-depositional sketch map of side wall of the prior art, sees also Fig. 1, on silicon substrate 10, is formed with at least one transistor, deposit one side wall layer on transistor; Wherein, may further comprise the steps:
Fig. 4 is the sketch map after the present invention improves the oblique angle etching side wall of the side wall lithographic method that attaches body dynamic random memory cell writing speed; See also Fig. 4, and with reference to Fig. 2, etching is removed the part side wall layer; The part side wall layer that only keeps grid 101 sidewalls that cover the first transistor is as gate lateral wall layer 102; Make the direction of plasma become the α angle in the etching process,, see also Fig. 2, Fig. 3 so that the side wall thicknesses of grid 101 both sides is different after the etching with vertical silicon chip surface direction; Different with prior art, the present invention makes the etching direction of plasma that certain inclination angle is arranged in the process of carrying out etching.
Can be among the present invention so that make after the etching near the width of grid 101 side wall layers of drain terminal less than width near grid 101 side wall layers of source end.
Can adopt anisotropic dry etching that side wall layer is carried out etching among the present invention.
Further, the angle at the α angle among the present invention can be 15 °, thereby reaches preferable technique effect.
Fig. 5 is the sketch map after completion source that the present invention improves the side wall lithographic method that attaches body dynamic random memory cell writing speed leak to be injected, and sees also Fig. 5, after the etching of accomplishing side wall layer, carries out the drain-source doping process;
Owing to make in the etching technics near the grid 101 side wall layer width of source end width greater than grid 101 side walls of drain terminal; So carry out dopant ion and the channel distance of drain terminal behind the drain-source doping process dopant ion and substrate distance less than the source end; Compared with prior art the dopant ion of drain terminal and channel distance are furthered; The dopant ion of source end and substrate distance are zoomed out, and after accomplishing the drain-source doping process, carry out annealing process.
Because the dopant ion of drain terminal and the distance of device channel are furthered; Thereby improved the longitudinal electric field in the drain terminal raceway groove, the electron hole pair that the carrier impact of being quickened by transverse electric field produces, charge carrier can be swept substrate under stronger longitudinal electric field effect; Increased substrate current; On the other hand, the dopant ion of source end and the distance of device substrate are zoomed out, thereby have reduced the leakage rate that gathers charge carrier end from the source.So the present invention has improved the writing speed of floater effect memory cell through improving the side wall etching technics.
In sum, owing to adopted technique scheme, the side wall lithographic method that the present invention's raising attaches body dynamic random memory cell writing speed is in side wall (Spacer) etching technics; Take the oblique angle to introduce the method for etching plasma; Make that the lateral wall width of drain terminal reduces after the etching, and the lateral wall width of source end increases, after highly doped injection and annealing process are leaked in ensuing source; The dopant ion of drain terminal is furthered from channel distance; The distance of the dopant ion of source end and raceway groove and substrate is zoomed out, and has improved the longitudinal electric field in the drain terminal raceway groove on the one hand, has increased substrate current; Reduced the leakage rate that gathers charge carrier end on the other hand, thereby improved the writing speed of floater effect memory cell from the source.
It should be appreciated by those skilled in the art that those skilled in the art combine prior art and the foregoing description can realize said variant, do not repeat them here.Such variant does not influence flesh and blood of the present invention, does not repeat them here.
More than preferred embodiment of the present invention is described.It will be appreciated that the present invention is not limited to above-mentioned specific implementations, equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention; Or being revised as the equivalent embodiment of equivalent variations, this does not influence flesh and blood of the present invention.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (6)
1. a raising attaches the side wall lithographic method of body dynamic random memory cell writing speed, on the SOI silicon substrate, is formed with at least one transistor, deposit one side wall layer on transistor; It is characterized in that, may further comprise the steps:
Etching is removed the part side wall layer; The part side wall layer that only keeps the gate lateral wall that covers the first transistor is as gate lateral wall layer; Make the direction of plasma become the α angle in the etching process with vertical silicon chip surface direction; So that the side wall thicknesses of grid both sides is different after the etching, afterwards, carry out the drain-source doping process.
2. raising according to claim 1 attaches the side wall lithographic method of body dynamic random memory cell writing speed, it is characterized in that, makes after the etching near the width of the grid curb wall layer of drain terminal less than the width near the grid curb wall layer of source end.
3. raising according to claim 1 attaches the side wall lithographic method of body dynamic random memory cell writing speed, it is characterized in that, carries out source region lateral wall width behind the drain-source doping process greater than the drain region lateral wall width.
4. raising according to claim 1 attaches the side wall lithographic method of body dynamic random memory cell writing speed, it is characterized in that, adopts anisotropic dry etching that side wall layer is carried out etching.
5. raising according to claim 1 attaches the side wall lithographic method of body dynamic random memory cell writing speed, it is characterized in that, carries out annealing process behind the completion drain-source doping process.
6. raising according to claim 1 attaches the side wall lithographic method of body dynamic random memory cell writing speed, it is characterized in that, the angle at α angle is 15 °.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011102652824A CN102446750A (en) | 2011-09-08 | 2011-09-08 | Spacer etching method for increasing writing speed of floating body dynamic random memory unit |
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| CN2011102652824A CN102446750A (en) | 2011-09-08 | 2011-09-08 | Spacer etching method for increasing writing speed of floating body dynamic random memory unit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102437125A (en) * | 2011-11-17 | 2012-05-02 | 上海华力微电子有限公司 | Method for improving writing speed of floating body effect storage unit, and floating body effect storage unit |
| CN102446770A (en) * | 2011-10-12 | 2012-05-09 | 上海华力微电子有限公司 | Method and structure for enhancing write-in speed of floating body dynamic random memory cell |
| CN106469713A (en) * | 2015-08-21 | 2017-03-01 | 台湾积体电路制造股份有限公司 | Semiconductor device and its manufacture method |
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| KR20040002204A (en) * | 2002-06-29 | 2004-01-07 | 주식회사 하이닉스반도체 | Semiconductor device and method for manufacturing the same |
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| US20080233691A1 (en) * | 2007-03-23 | 2008-09-25 | Kangguo Cheng | Method of forming asymmetric spacers and methods of fabricating semiconductor device using asymmetric spacers |
| US20100029082A1 (en) * | 2008-08-04 | 2010-02-04 | International Business Machines Corporation | Method and apparatus for angular high density plasma chemical vapor deposition |
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2011
- 2011-09-08 CN CN2011102652824A patent/CN102446750A/en active Pending
Patent Citations (5)
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| US6168999B1 (en) * | 1999-09-07 | 2001-01-02 | Advanced Micro Devices, Inc. | Method for fabricating high-performance submicron mosfet with lateral asymmetric channel and a lightly doped drain |
| KR20040002204A (en) * | 2002-06-29 | 2004-01-07 | 주식회사 하이닉스반도체 | Semiconductor device and method for manufacturing the same |
| US20040031996A1 (en) * | 2002-08-16 | 2004-02-19 | Brian Li Chi Nan | Semiconductor device and method for forming |
| US20080233691A1 (en) * | 2007-03-23 | 2008-09-25 | Kangguo Cheng | Method of forming asymmetric spacers and methods of fabricating semiconductor device using asymmetric spacers |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446770A (en) * | 2011-10-12 | 2012-05-09 | 上海华力微电子有限公司 | Method and structure for enhancing write-in speed of floating body dynamic random memory cell |
| CN102437125A (en) * | 2011-11-17 | 2012-05-02 | 上海华力微电子有限公司 | Method for improving writing speed of floating body effect storage unit, and floating body effect storage unit |
| CN106469713A (en) * | 2015-08-21 | 2017-03-01 | 台湾积体电路制造股份有限公司 | Semiconductor device and its manufacture method |
| CN106469713B (en) * | 2015-08-21 | 2019-03-26 | 台湾积体电路制造股份有限公司 | Semiconductor device and its manufacturing method |
| US10522464B2 (en) | 2015-08-21 | 2019-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnection structure and methods of fabrication the same |
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Application publication date: 20120509 |