CN102437022A - Method for manufacturing multilayer metal-oxide-metal (MOM) capacitor - Google Patents
Method for manufacturing multilayer metal-oxide-metal (MOM) capacitor Download PDFInfo
- Publication number
- CN102437022A CN102437022A CN2011103917343A CN201110391734A CN102437022A CN 102437022 A CN102437022 A CN 102437022A CN 2011103917343 A CN2011103917343 A CN 2011103917343A CN 201110391734 A CN201110391734 A CN 201110391734A CN 102437022 A CN102437022 A CN 102437022A
- Authority
- CN
- China
- Prior art keywords
- metal
- oxide
- low
- oxygen
- containing gas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The invention provides a method for manufacturing a multilayer metal-oxide-metal (MOM) capacitor. The method has the following beneficial effects: the multilayer MOM capacitor is formed by forming a mixed layer of a low-k dielectric and high-k silicon oxide, then utilizing the traditional photoetching and etching processes to form metal grooves in the low-k dielectric and filling metals into the metal grooves and repeating the previous steps; the MOM capacitor structure is realized in the high-k silicon oxide region and interconnection of the low-k dielectric is realized in other regions; and high-k silicon oxide is formed by circularly carrying out plasma enhanced chemical vapor deposition (PECVD) and oxygen-containing gas treatment so that the silicon-hydrogen bonds in silicon oxide can be effectively removed. Compared with the traditional single k dielectric structure, the method has the following advantages: not only can the capacitance of the capacitor in the layer be effectively improved, but also the electrical characteristics of the MOM capacitor such as breakdown voltage, leakage current and the like and the electrical uniformity among the components are improved.
Description
Technical field
The present invention relates to microelectronic, particularly relate to the manufacture method of a kind of multiple layer metal-oxide-metal capacitance.
Background technology
Capacitor is electronic devices and components commonly used in the integrated circuit, also is the important composition unit of integrated circuit, and it can be widely used in memory, microwave, and radio frequency, smart card is in the chips such as high pressure and filtering.At present, the capacitor that widely adopts in the chip is metal-insulator-metal type (MIM) capacitor that is parallel to silicon chip substrate.Wherein metal adopts the copper compatible mutually with metal interconnected technology, aluminium etc. usually; Mostly insulator is the dielectric substance silica or the silicon nitride of high-k (k); Plasma enhanced chemical vapor deposition method (PECVD, Plasma Enhanced Chemical Vapor Deposition) is because of the low thin film deposition that is widely used in the metal interconnected technology of its depositing temperature.Utilize residual a large amount of si-h bond (Si-H) in silica that the PECVD method makes or the silicon nitride film; Make and have more electric charge in it; This causes this silica or the silicon nitride film uniformity aspect electrical thickness relatively poor, and the MIM capacitor that utilizes this silica or silicon nitride film to make also can be corresponding relatively poor aspect each electrical characteristics such as puncture voltage, leakage current.
In addition, along with improving constantly of very lagre scale integrated circuit (VLSIC) integrated level, the continuous scaled down of device feature size, also corresponding the dwindling of capacitor sizes of making in the circuit, to the uniformity that electric capacity is made, coherence request is more strict.And along with the minimizing of device size, and performance is to the demand of big electric capacity, and how under limited area, obtaining highdensity electric capacity also becomes an attractive problem.
Publication number is that the Chinese patent of CN101577227A discloses a kind of method of improving aluminium-silicon nitride-tantalum thing capacitor performance; Handle silicon nitride film through oxygen-containing gas; The quantity of electric charge in the silicon nitride film that forms is less, has improved the electrical thickness of silicon nitride film and the uniformity of physical thickness, and the MIM electric capacity that adopts the method formation is in puncture voltage; Each electrical characteristics aspect such as leakage current makes moderate progress, but does not obtain highdensity electric capacity.Therefore, how under limited area, to obtain highdensity electric capacity and be still urgent problem in the present technical development.
Summary of the invention
Technical problem to be solved by this invention provides the formation method of a kind of multiple layer metal-oxide-metal capacitance; Under limited area, to obtain highdensity electric capacity; And can improve the electric capacity of layer inner capacitor effectively, improve each electrical characteristics such as puncture voltage, leakage current of metal-oxide-metal (MOM) capacitor and the electricity uniformity between each device thereof.
For addressing the above problem, the present invention provides the manufacture method of a kind of multiple layer metal-oxide-metal capacitance, may further comprise the steps:
Step 4, the mode of handling the circulation of two steps through plasma enhanced chemical vapor deposition and oxygen-containing gas forms silica in said opening;
Step 6, through photoetching be etched in the low k value dielectric layer and form first metallic channel and second metallic channel respectively, wherein, the bottom that first metallic channel is positioned at the silica top and first metallic channel is communicated to silica, and second metallic channel is used for follow-up formation and interconnects;
Step 7 is filled metal in first, second metallic channel;
Repeating step 2～step 7.
Preferable, the reacting gas that said plasma enhanced chemical vapor deposition adopts comprises silane and nitrous oxide.
Preferable; The flow of said silane is between 500sccm to 600sccm; The flow of said nitrous oxide is between 9000sccm to 15000sccm, and the flow-rate ratio of silane and nitrous oxide is 1: 15 to 1: 30, and rate of film build is between 1500 nm/minute to 5000 nm/minute.
Preferable, said oxygen-containing gas is handled the oxygen-containing gas that is adopted and is comprised nitric oxide, nitrous oxide, carbon monoxide or carbon dioxide.
Preferable, the oxygen-containing gas flow that said oxygen-containing gas processing is adopted is between 2000sccm to 6000sccm, and treatment temperature is between 300 degrees centigrade to 600 degrees centigrade.
Preferable, said mode through plasma enhanced chemical vapor deposition and oxygen-containing gas processing two steps circulation forms in the process of silica, and the silicon oxide thickness of each deposition is 1 nanometer to 10 nanometer.
The present invention is through forming the mixed layer of low k value medium and high k value silica; Then carry out the photoetching etching of traditional handicraft; Realize multilayer MOM structure in high k value region of silicon oxide, realize low k value interconnection in other zones, wherein; The mode that the formation of high k silica adopts PECVD deposition and oxygen-containing gas cycle of treatment to carry out can effectively be removed the si-h bond in the silica.Compare with traditional single k value dielectric structure, the present invention can effectively improve the electric capacity of layer inner capacitor, has improved each electrical characteristics such as puncture voltage, leakage current of MOM capacitor again, and the electricity uniformity between each device.Through adopting the vertical capacitor structure, can also effectively improve capacitor density, thereby in less chip area, realize big electric capacity.
Description of drawings
Fig. 1 forms the method flow diagram of multilayer MOM electric capacity for the embodiment of the invention;
Fig. 2 A～2L is the method sketch map that the embodiment of the invention forms multilayer MOM electric capacity.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
The present invention proposes the process of a kind of making multiple layer metal-oxide-metal (MOM) capacitor.Please, prepare the method flow diagram of multilayer MOM capacitor for the present invention with reference to Fig. 1.
Step 201: substrate 1 is provided; The substrate 1 that is provided in the present embodiment can be simple silicon substrate, also can form the silicon substrate of semiconductor device for the surface.
Step 202: shown in Fig. 2 A, the low k value dielectric layer 2 of deposition on substrate 1, said low k value dielectric layer 2 adopts chemical vapour deposition (CVD) or spin coating process to form, and dielectric constant is 2～3.
Step 203: shown in Fig. 2 B, through photoetching and etching, in said low k value dielectric layer 2, form an opening 2a, said opening 2a bottom-exposed goes out substrate 1 surface.
Step 204: shown in Fig. 2 C, in said opening, fill the oxide of high k value, the preferred silica 3 that adopts among the present invention.In order to improve silicon oxide film that conventional P ECVD method makes in the uniformity aspect the electrical thickness; The mode that adopts PECVD method cvd silicon oxide and oxygen-containing gas cycle of treatment to carry out among the present invention; After promptly depositing one deck silica, carry out oxygen-containing gas subsequently and handle, and then cvd silicon oxide; Carry out oxygen-containing gas again and handle, so circulation; The silicon oxide thickness of each deposition is 1 nanometer to 10 nanometer; Until the silica 3 of deposition reaches till the thickness that needs in the technology; Remove the unnecessary silica in low k value dielectric layer 2 surfaces through cmp then, form the mixed layer of low k value medium and silica.
Wherein, The reacting gas that PECVD adopts is silane and nitrous oxide; The process conditions of reaction are that the flow of silane is between 500sccm to 600sccm; The flow of nitrous oxide is between 9000sccm to 15000sccm, and the flow-rate ratio of silane and nitrous oxide is between 1: 15 to 1: 30, and rate of film build is between 1500 nm/minute to 5000 nm/minute; Oxygen-containing gas is handled the oxygen-containing gas that is adopted and is comprised nitric oxide, nitrous oxide, carbon monoxide or carbon dioxide, and the flow of oxygen-containing gas is between 2000 to 6000sccm, and treatment temperature is between 300 to 600 degrees centigrade.
And then silica through the deposition skim also carries out the oxygen-containing gas processing to it, can remove the si-h bond Si-H in the silicon oxide film fully, and so circulation can obtain the good silica of electrical thickness evenness.
Step 205: shown in Fig. 2 D, deposit low k value dielectric layer 2 once more to predetermined thickness on the said structure surface.
Step 206: shown in Fig. 2 E, in low k value dielectric layer 2, form the first metallic channel 4a and the second metallic channel 4b respectively, wherein, the first metallic channel 4a is positioned at silica 3 tops and is communicated to silica 3 surfaces, is used for the capacitor plate of follow-up formation multilayer MOM electric capacity.The first metallic channel 4a can evenly offer a plurality of, and the degree of depth of the first metallic channel 4a equals the thickness of the low k value dielectric layer in silica 3 surfaces, and promptly the bottom-exposed of the first metallic channel 4a goes out silica 3.The second metallic channel 4b is used for follow-up formation interconnection, and its degree of depth can be identical with the first metallic channel 4a, also can adjust number, size, the degree of depth of the second metallic channel 4b according to the actual process demand.
Step 207: shown in Fig. 2 F, in metallic channel, fill metal 5, promptly in first, second metallic channel, carry out the processing steps such as diffusion impervious layer deposition, copper platings, copper metal layer cmp of the copper of copper wiring technique, the filling of completion copper.
Then, repeating step 202 to 207 specifically comprises: shown in Fig. 2 G, at the low k value dielectric layer 2 of the deposition of the body structure surface shown in Fig. 2 F; Shown in Fig. 2 H,, in low k value dielectric layer 2, form opening 2b through photoetching and etching; Shown in Fig. 2 I, the mode cvd silicon oxide 3 in said opening 2b that adopts PECVD method and oxygen-containing gas cycle of treatment to carry out; Shown in Fig. 2 J, deposit low k value dielectric layer 2 once more at the body structure surface shown in Fig. 2 I; Shown in Fig. 2 K, in low k value dielectric layer 2, form first, second metallic channel 6a respectively, 6b, wherein the first metallic channel 6a is used for follow-up formation capacitor plate, and corresponding with the position of metallic channel 4a, and the second metallic channel 6b is used to form interconnection; Shown in Fig. 2 L, in metallic channel 6a, 6b, insert metal 5, thereby realize multilayer MOM capacitance structure in high k value region of silicon oxide, realize low k value interconnection in other zones.
Certainly, also can be as required once more or repeatedly repeating step 202 to 207 until reaching the required MOM electric capacity number of plies.
The present invention is when utilizing sketch map that the embodiment of the invention is detailed, and for the ease of explanation, the profile of expression device architecture is disobeyed general ratio and done local the amplification, should be with this as to qualification of the present invention.In addition, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (6)
1. the manufacture method of multiple layer metal-oxide-metal capacitance is characterized in that, may further comprise the steps:
Step 1 provides substrate;
Step 2, the low k value dielectric layer of deposition;
Step 3 through photoetching and etching, forms an opening that runs through said low k value dielectric layer in said low k value dielectric layer;
Step 4, the mode of handling the circulation of two steps through plasma enhanced chemical vapor deposition and oxygen-containing gas forms silica in said opening;
Step 5 deposits low k value dielectric layer once more on the said structure surface;
Step 6, through photoetching be etched in the low k value dielectric layer and form first metallic channel and second metallic channel respectively, wherein, the bottom that first metallic channel is positioned at the silica top and first metallic channel is communicated to silica, and second metallic channel is used for follow-up formation and interconnects;
Step 7 is filled metal in first, second metallic channel;
Repeating step 2～step 7.
2. the manufacture method of multiple layer metal-oxide as claimed in claim 1-metal capacitance is characterized in that, the reacting gas that said plasma enhanced chemical vapor deposition adopts comprises silane and nitrous oxide.
3. the manufacture method of multiple layer metal-oxide as claimed in claim 2-metal capacitance; It is characterized in that; The flow of said silane is between 500sccm to 600sccm; The flow of said nitrous oxide is between 9000sccm to 15000sccm, and the flow-rate ratio of silane and nitrous oxide is 1: 15 to 1: 30, and rate of film build is between 1500 nm/minute to 5000 nm/minute.
4. the manufacture method of multiple layer metal-oxide as claimed in claim 1-metal capacitance is characterized in that, said oxygen-containing gas is handled the oxygen-containing gas that is adopted and comprised nitric oxide, nitrous oxide, carbon monoxide or carbon dioxide.
5. the manufacture method of multiple layer metal-oxide as claimed in claim 1-metal capacitance; It is characterized in that; The oxygen-containing gas flow that said oxygen-containing gas processing is adopted is between 2000sccm to 6000sccm, and treatment temperature is between 300 degrees centigrade to 600 degrees centigrade.
6. the manufacture method of multiple layer metal-oxide as claimed in claim 1-metal capacitance; It is characterized in that; Said mode through plasma enhanced chemical vapor deposition and oxygen-containing gas processing two steps circulation forms in the process of silica, and the silicon oxide thickness of each deposition is 1 nanometer to 10 nanometer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110391734.3A CN102437022B (en) | 2011-11-30 | 2011-11-30 | Method for manufacturing multilayer metal-oxide-metal (MOM) capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110391734.3A CN102437022B (en) | 2011-11-30 | 2011-11-30 | Method for manufacturing multilayer metal-oxide-metal (MOM) capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102437022A true CN102437022A (en) | 2012-05-02 |
| CN102437022B CN102437022B (en) | 2014-04-16 |
Family
ID=45985019
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110391734.3A Active CN102437022B (en) | 2011-11-30 | 2011-11-30 | Method for manufacturing multilayer metal-oxide-metal (MOM) capacitor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102437022B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102664143A (en) * | 2012-04-20 | 2012-09-12 | 上海华力微电子有限公司 | Method for manufacturing capacitor comprising multilayer metal, silicon oxide and metal |
| CN102779736A (en) * | 2012-08-16 | 2012-11-14 | 上海华力微电子有限公司 | Preparation method of metal-silicon oxide-metal capacitor |
| CN102779732A (en) * | 2012-08-16 | 2012-11-14 | 上海华力微电子有限公司 | Manufacturing method of multi-layer metal-silicon oxide-metal capacitor |
| CN102779731A (en) * | 2012-08-16 | 2012-11-14 | 上海华力微电子有限公司 | Preparation method of multi-layer metal-silicon oxide-metal capacitor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030001188A1 (en) * | 2001-06-27 | 2003-01-02 | Nakagawa Osamu Samuel | High-dielectric constant metal-insulator metal capacitor in VLSI multi-level metallization systems |
| CN101577227A (en) * | 2008-05-05 | 2009-11-11 | 中芯国际集成电路制造(北京)有限公司 | Forming methods of silicon nitride film and MIM capacitor |
| CN101593689A (en) * | 2008-05-29 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | The formation method and the double mosaic structure manufacture method of photoengraving pattern |
| CN101593690A (en) * | 2008-05-30 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | The formation method of stacked dielectric layer and the formation method of before-metal medium layer |
| CN101736314A (en) * | 2008-11-06 | 2010-06-16 | 中芯国际集成电路制造(北京)有限公司 | Formation method of silicon oxide film and metal-insulator-metal capacitor |
-
2011
- 2011-11-30 CN CN201110391734.3A patent/CN102437022B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030001188A1 (en) * | 2001-06-27 | 2003-01-02 | Nakagawa Osamu Samuel | High-dielectric constant metal-insulator metal capacitor in VLSI multi-level metallization systems |
| CN101577227A (en) * | 2008-05-05 | 2009-11-11 | 中芯国际集成电路制造(北京)有限公司 | Forming methods of silicon nitride film and MIM capacitor |
| CN101593689A (en) * | 2008-05-29 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | The formation method and the double mosaic structure manufacture method of photoengraving pattern |
| CN101593690A (en) * | 2008-05-30 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | The formation method of stacked dielectric layer and the formation method of before-metal medium layer |
| CN101736314A (en) * | 2008-11-06 | 2010-06-16 | 中芯国际集成电路制造(北京)有限公司 | Formation method of silicon oxide film and metal-insulator-metal capacitor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102664143A (en) * | 2012-04-20 | 2012-09-12 | 上海华力微电子有限公司 | Method for manufacturing capacitor comprising multilayer metal, silicon oxide and metal |
| CN102779736A (en) * | 2012-08-16 | 2012-11-14 | 上海华力微电子有限公司 | Preparation method of metal-silicon oxide-metal capacitor |
| CN102779732A (en) * | 2012-08-16 | 2012-11-14 | 上海华力微电子有限公司 | Manufacturing method of multi-layer metal-silicon oxide-metal capacitor |
| CN102779731A (en) * | 2012-08-16 | 2012-11-14 | 上海华力微电子有限公司 | Preparation method of multi-layer metal-silicon oxide-metal capacitor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102437022B (en) | 2014-04-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102386064B (en) | Manufacturing method of metal-oxide-metal capacitor | |
| CN102394215B (en) | Manufacturing method of multilayer metal-silicon oxide-metal capacitor | |
| CN101577227B (en) | Forming methods of silicon nitride film and MIM capacitor | |
| CN102394216B (en) | Metal-oxide-metal capacitor manufacturing method | |
| CN102437022B (en) | Method for manufacturing multilayer metal-oxide-metal (MOM) capacitor | |
| CN102437023B (en) | Method for manufacturing multilayer metal-oxide-metal capacitor | |
| CN102394217B (en) | Manufacturing method of metal- silicon nitride-metal capacitor | |
| US9484297B2 (en) | Semiconductor device having non-magnetic single core inductor and method of producing the same | |
| US9373680B1 (en) | Integrated circuits with capacitors and methods of producing the same | |
| CN102437024B (en) | Method for manufacturing multilayer metal-silicon oxide-metal (MOM) capacitor | |
| CN102623306B (en) | Metal-multilayer insulator-metal capacitor, manufacture method for same and integrated circuit thereof | |
| CN102446709B (en) | A kind of manufacture method of metal-silicon nitride-metal capacitor | |
| CN102709154A (en) | Manufacture method of metal-multilayer insulator-metal capacitor | |
| CN102655079B (en) | Method for preparing multilayer metal-multilayer insulator-metal capacitor | |
| CN102637583B (en) | Preparation method of multilayer metal-monox-metal capacitor | |
| CN102779734A (en) | Manufacturing method of multi-layer metal-silicon oxide-metal capacitor | |
| CN102779733A (en) | Manufacturing method of metal-silicon oxide-metal capacitor | |
| CN102592968B (en) | Method for producing multilayer metal-silicon nitride-metal capacitor | |
| CN102446981B (en) | Multi-layer metal-silicon nitride-metal capacitor and manufacturing method thereof | |
| CN102655078A (en) | Manufacturing method of multi-layer metal-silicon oxide-metal capacitor | |
| CN102779735A (en) | Preparation method of multi-layer metal-silicon oxide-metal capacitor | |
| CN102779731A (en) | Preparation method of multi-layer metal-silicon oxide-metal capacitor | |
| CN102779732A (en) | Manufacturing method of multi-layer metal-silicon oxide-metal capacitor | |
| CN102779736A (en) | Preparation method of metal-silicon oxide-metal capacitor | |
| CN102446710B (en) | Method for manufacturing multilayer metal-silicon nitride-metal capacitor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |