CN102436365A - Method and device for transforming high-speed linear spectrum data to logarithm data - Google Patents
Method and device for transforming high-speed linear spectrum data to logarithm data Download PDFInfo
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- CN102436365A CN102436365A CN2011103215092A CN201110321509A CN102436365A CN 102436365 A CN102436365 A CN 102436365A CN 2011103215092 A CN2011103215092 A CN 2011103215092A CN 201110321509 A CN201110321509 A CN 201110321509A CN 102436365 A CN102436365 A CN 102436365A
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Abstract
The invention discloses a method and device for transforming high-speed linear spectrum data to logarithm data. The method comprises the following steps of: respectively transforming 10 bits binary decimal points to 16 bits table lookup data and storing the data in a memory; classifying 18 bits binary floating point data into high 8 bits index bit data and low 10 bits decimal point bit data; expanding 8 bits full-0 low 8 bits to the high 8 bits index bit data to form 16 bits expanding data; obtaining the 16 bits table lookup data corresponding to the low 10 bits decimal point bit by the table lookup memory; summing the 16 bits expanding data and 16 bits table lookup data and obtaining 16 bits binary fixed point number logarithm data. The invention implements the high-speed transformation of linear spectrum data to logarithm data on a field programmable gata array (FPGA) by flexibly utilizing the table lookup, bit number expansion and summing calculation; the operation treatment speed is faster; and the resource of a multiplier is saved.
Description
Technical field
The present invention relates to the spectrum analysis field, be specifically related to a kind of high-speed linear frequency spectrum data and convert method and device into logarithmic data.
Background technology
Spectrum analyzer is the instrument of research electric signal spectrum structure; Be used for the measurement of signal parameters such as signal distortion, percentage modulation spectral purity, frequency stability and crosstalk; Can be a kind of multiduty electronic measuring instrument also in order to some parameter of Circuits System such as measuring amplifier and wave filter.Spectrum analyzer generally is made up of several parts such as signal acquisition module, AD modular converter, FFT processing module and output display modules; Its principle of work is: signal acquisition module is gathered measured signal; The output signal of local oscillator and each frequency component in the measured signal are carried out the difference frequency conversion successively in frequency mixer; The intermediate-freuqncy signal that is produced is through amplifying, be transformed into digital signal by the AD modular converter then after, carry out the FFT Fourier analysis, to number conversion and be presented on the display screen.
The performance of spectrum analyzer depends primarily on FFT and to the performance of number conversion, become logarithmic relationship with number of sampling operation time, therefore; In high precision, high performance spectrum analyzer; Generally adopt digital signal processor (DSP) auxiliary process, to improve the FFT arithmetic speed, particularly in real time spectral analysis; Need DSP to adopt FPGA to do the FFT calculation process in real time, then FFT result is carried out number conversion and output.Wherein, for being an important step of frequency spectrum processing, its objective is relativity to the linear spectral data-switching for better shows signal to logarithmic data.Because the handling capacity of data is very high in to number conversion process, even the circumstances that DSP can't tackle can occur.Therefore, existing processing mode is that logarithm operation is resolved into power series, is satisfying on the basis of operational precision, and the first few items of exponentiation progression obtains through computing, like (1) formula:
And under the conversion accuracy of ± 0.05dB, the first six of power series with can satisfy accuracy requirement basically, therefore can (1) formula be reduced to:
Realize a such computing, take two kinds of methods at present, a kind of is that another kind is in FPGA, to utilize multiplier, totalizer to come computing through the processor computing that programs.
But all there is certain defective in above-mentioned two kinds of disposal routes, and the shortcoming that logarithm operation is decomposed into the power series computing is that arithmetic speed is slow.Adopt multiplier, totalizer and the logical resource construction operation unit of FPGA can reach higher arithmetic speed; Yet; Its highest point reason speed is limited by the arithmetic speed of multiplier; Highest point reason data speed only can reach about 80MHz, and structure (2) formula needs 10 multipliers at least, needs to consume a large amount of multiplier resources.
Summary of the invention
Technical matters to be solved by this invention is to solve in the spectrum analyzer, and the linear spectral data-switching is the slow-footed problem of logarithm data operation.
In order to solve the problems of the technologies described above, the technical scheme that the present invention adopted provides a kind of spectrum analyzer neutral line frequency spectrum data and converts the method to logarithmic data into, may further comprise the steps:
A10, convert ten binary fraction 10 0,000 0000～11 11 1111 into 16 data of tabling look-up respectively and be stored in the storer successively, and set up the one-to-one relationship table of ten binary fraction 10 0,000 0000～11 11 1111 and said 16 data of tabling look-up; Conversion method is: establishing ten represented decimal numbers of binary fraction is A, at first calculates (lnA/ln2) * 2
8, the result that will obtain then rounds the back with 16 binary complement representations;
A20, will and be divided into most-significant byte exponent bits data and low 10 decimal digits certificates through 18 binary-floating-point datas after the FFT conversion;
A30, said most-significant byte exponent bits data are expanded to 16 growth daties, wherein, said most-significant byte exponent bits data are as the most-significant byte of said 16 growth daties, and the least-significant byte of said 16 growth daties is complete 0;
A40, the said mapping table of setting up through steps A 10 search 16 data of tabling look-up that said storer obtains said low 10 decimal places correspondence;
A50, with said 16 growth daties and said 16 the data additions of tabling look-up that obtain of tabling look-up obtain 16 corresponding scale-of-two fixed-point numbers of 18 binary-floating-point datas to logarithmic data.
The present invention also provides a kind of spectrum analyzer neutral line frequency spectrum data to convert the device to logarithmic data into; Comprise storer, receiver, buffer, requestor and totalizer; Store 16 data of tabling look-up in the said storer, said 16 data of tabling look-up are corresponding one by one with 10 binary fraction 10 0,000 0000～11 11 1111 respectively; Corresponding relation is: establishing ten represented decimal numbers of binary fraction is A, at first calculates (lnA/ln2) * 2
8, the result that will obtain then rounds the back with 16 binary complement representations; Said receiver receives 18 binary-floating-point datas after the FFT conversion and is divided into most-significant byte exponent bits data and low 10 decimal digits certificates; Said buffer receives from the said most-significant byte exponent bits data of receiver acquisition and converts 16 growth daties into, and the most-significant byte of said 16 growth daties is said most-significant byte exponent bits data, and the least-significant byte of said 16 growth daties is complete 0; Said requestor is inquired about said storer and is obtained and corresponding 16 data of tabling look-up of said low 10 decimal digits certificate; Said totalizer reads said 16 growth daties and obtains 16 corresponding scale-of-two fixed-point numbers of said 18 binary-floating-point datas to logarithmic data with said 16 the data additions of tabling look-up that obtain from requestor from buffer.
The present invention, utilize dexterously table look-up, figure place is expanded, addition calculation, in spectrum analyzer, the linear spectral data are changed to the logarithm data in high speed having realized on the FPGA.Specifically, because in FPGA, the pipeline system access speed of storer can reach 200MHz, and 16 totalizer can satisfy 200MHz basically, and therefore, calculation process speed is faster, and saves the resource of multiplier.
Description of drawings
Fig. 1 is 18 binary floating point numerical representation synoptic diagram;
Fig. 2 converts the workflow block diagram to logarithmic data into for spectrum analyzer neutral line frequency spectrum data provided by the invention.
Embodiment
In spectrum analyzer, be linear 18 binary floating point numbers through the spectrum signal after the FFT processing, and process is 16 scale-of-two fixed-point numbers to the spectrum signal after the number conversion.If the decimal number that 18 binary floating point numerical tables show is X, the decimal number that 16 scale-of-two fixed-point numbers after the number conversion are represented is Y, and then the corresponding relation between the two is: Y=[(lnX/ln2) * 2
8].The invention provides a kind of high-speed linear frequency spectrum data and convert method and device into, be used to realize above-mentioned quick conversion logarithmic data to logarithmic data.
Below in conjunction with accompanying drawing and specific embodiment the present invention is made detailed explanation.
This specific embodiment is that example describes with the transfer process of 18 binary floating points several 00001011.1100000000 shown in Figure 1, and these 18 binary floating points several 00001011.1100000000 corresponding decimal data is 2
11* 0.75=1536, after the conversion is (ln1536/ln2) * 2 to logarithmic data
8=2710.
Spectrum analyzer neutral line frequency spectrum data provided by the invention converts into the method for logarithmic data as shown in Figure 2, may further comprise the steps:
A10, will all convert one 16 data of tabling look-up with decimal 10 0,000 0000～11 1,111 1111 of ten binary representations respectively into and be stored in the storer successively; Conversion method does; If ten corresponding decimal datas of binary fraction are A, at first calculate (lnA/ln2) * 2
8, the result that will obtain then rounds the back with 16 binary complement representations.Decimal place 11 0,000 0000 with 18 binary floating points several 00001011.1100000000 is an example, and 11 0,000 0000 corresponding decimal numbers are 0.75, calculate (lnA/ln2) * 2 according to formula
8=(ln0.75/ln2) * 2
8=-106.24, round and be-106, be expressed as 1,111 1,111 1,001 0110 with 16 two's complement.
A20, set up decimal 10 0,000 0000～11 1,111 1111 of ten binary representations and the one-to-one relationship table of said 16 data of tabling look-up, can inquire about low 10 decimal digits of obtaining 18 binary floating point numbers 16 data of tabling look-up according to this corresponding relation according to correspondence;
A30, will be divided into most-significant byte exponent bits data and low 10 decimal digits certificates through 18 binary floating point numbers after the FFT conversion.
A40, said most-significant byte exponent bits data are expanded to 16 growth daties, wherein, most-significant byte exponent bits data are as the most-significant byte of said 16 growth daties, and the least-significant byte of 16 growth daties is complete 0.To present embodiment, 16 growth daties are 0,000 1,011 0,000 0000.
A50, the said mapping table of setting up through steps A 30 search 16 data of tabling look-up that storer obtains said low 10 decimal places correspondence;
A60, the linear spectral data that 16 growth daties and 16 the data additions of tabling look-up obtaining of tabling look-up obtained show with 18 binary floating point numerical tables to logarithmic data.To present embodiment, 16 after 18 binary floating points several 00001011.1100000000 are changed is 0,000 1,011 0000 0000+1111,1,111 1001 011,0=0,000 1,010 1,001 0110 to logarithmic data, and corresponding decimal value data are 2710.
Verify that below in conjunction with instantiation spectrum analyzer neutral line frequency spectrum data provided by the invention converts the correctness to the method for logarithmic data into.If the entire data of the most-significant byte of 18 binary floating point numbers is m, low 10 small data is n, and then the decimal data of floating point representation is 2
m* n asks logarithm to obtain ln (2 to it
m* n)=m * ln2+lnn.Because hope the integer of result for representing of output with 16 bits, therefore need the result be multiply by a conversion coefficient again and change, conversion coefficient is 2
8/ ln2, i.e. 256/ln2, like this, the integer of 16 binary representations should be to (m * 256+ (lnn * 256)/ln2) asks the result after whole.
With 18 binary floating point numbers (00001011.1100000000) is example; Its most-significant byte exponent bits is 00001011, the integer data m=11 of expression, and decimal place is 1100000000; Decimal data n=0.75 of expression, ask logarithm to get to 18 binary floating point numbers: ln (2
11* 0.75)=and 11 * ln2+ln (0.75) ≈ 7.3369369, multiply by again that the result is 2709.75 behind the conversion coefficient, changing whole is 2710, is shown with 16 binary forms: 0,000 1,010 1,001 0110.It is thus clear that its result is consistent with the resulting result of method provided by the invention.
Among the present invention, the minimum data that 10 decimal places are represented is 1000000000, and corresponding decimal data is 0.5; Maximum data is 1111111111, and corresponding decimal data is 0.9990234375, and the maximum error value is 0000000001; Carrying out maximum error value after the number conversion is 201g (1/512)=0.017dB, therefore, and among the present invention; The data span of decimal place is 0.5～0.9990234375, and attainable precision is ± 0.017dB.
Because in FPGA; The pipeline system access speed of storer can reach 200MHz; 16 totalizer can satisfy 200MHz basically, and the method that converts into logarithmic data because of spectrum analyzer neutral line frequency spectrum data provided by the invention can realize very high speed.
Buffer among Fig. 2 is 8 buffers; Storer is 1024 * 16; Buffer, storer and 16 totalizers are logical design in the FPGA, FPGA take altera corp Stratix III series EP3SE80F1152C4 device, develop software and adopt the Quartus II of altera corp; 8.0,16 totalizers of version number are directly called the basic macroefficiency in basic macroefficiency (Megafunctions) storehouse.8 buffers call path C:/quartus8.0/libraries/megafuctions/storage/lpm_dff, and it is 8 that data bit width is set; The memory calls path is C:/quartus8.0/libraries/megafuctions/storage/lpm_rom, and it is 16 that the output bit wide is set, and capacity is 1024; 16 totalizers are called path C:/quartus8.0/libraries/megafuctions/arithmetic/parallel _ add, and input quantity 2 is set, input bit wide 16, and output bit wide 16, type of addition is the symbolic number addition.
The present invention also provides a kind of spectrum analyzer neutral line frequency spectrum data to convert the device to logarithmic data into; Goodbye Fig. 2; Comprise storer, receiver, buffer, requestor and totalizer; Store 16 data of tabling look-up in the said storer, said 16 data of tabling look-up are corresponding one by one with 10 binary fraction 10 0,000 0000～11 11 1111 respectively; Corresponding relation is: establishing ten represented decimal numbers of binary fraction is A, at first calculates (lnA/ln2) * 2
8, the result that will obtain then rounds the back with 16 binary complement representations; Said receiver receives 18 binary-floating-point datas after the FFT conversion and is divided into most-significant byte exponent bits data and low 10 decimal digits certificates; Said buffer receives from the said most-significant byte exponent bits data of receiver acquisition and converts 16 growth daties into, and the most-significant byte of said 16 growth daties is said most-significant byte exponent bits data, and the least-significant byte of said 16 growth daties is complete 0; Said requestor is inquired about said storer and is obtained and corresponding 16 data of tabling look-up of said low 10 decimal digits certificate; Said totalizer reads said 16 growth daties and obtains 16 corresponding scale-of-two fixed-point numbers of said 18 binary-floating-point datas to logarithmic data with said 16 the data additions of tabling look-up that obtain from requestor from buffer.
The present invention is not limited to above-mentioned preferred forms, and anyone should learn the structural change of under enlightenment of the present invention, making, and every have identical or close technical scheme with the present invention, all falls within protection scope of the present invention.
Claims (2)
1. a high-speed linear frequency spectrum data converts the method to logarithmic data into, it is characterized in that may further comprise the steps:
A10, convert ten binary fraction 10 0,000 0000～11 11 1111 into 16 data of tabling look-up respectively and be stored in the storer successively, and set up the one-to-one relationship table of ten binary fraction 10 0,000 0000～11 111111 and said 16 data of tabling look-up; Conversion method is: establishing ten represented decimal numbers of binary fraction is A, at first calculates (lnA/ln2) * 2
8, the result that will obtain then rounds the back with 16 binary complement representations;
A20, will and be divided into most-significant byte exponent bits data and low 10 decimal digits certificates through 18 binary-floating-point datas after the FFT conversion;
A30, said most-significant byte exponent bits data are expanded to 16 growth daties, wherein, said most-significant byte exponent bits data are as the most-significant byte of said 16 growth daties, and the least-significant byte of said 16 growth daties is complete 0;
A40, the said mapping table of setting up through steps A 10 search 16 data of tabling look-up that said storer obtains said low 10 decimal places correspondence;
A50, with said 16 growth daties and said 16 the data additions of tabling look-up that obtain of tabling look-up obtain 16 corresponding scale-of-two fixed-point numbers of 18 binary-floating-point datas to logarithmic data.
2. a high-speed linear frequency spectrum data converts the device to logarithmic data into, it is characterized in that comprising:
Storer stores 16 data of tabling look-up in this storer, said 16 data of tabling look-up are corresponding one by one with 10 binary fraction 10 0,000 0000～11 11 1111 respectively; Corresponding relation is: establishing ten represented decimal numbers of binary fraction is A, at first calculates (lnA/ln2) * 2
8, the result that will obtain then rounds the back with 16 binary complement representations;
Receiver receives 18 binary-floating-point datas after the FFT conversion and is divided into most-significant byte exponent bits data and low 10 decimal digits certificates;
Buffer receives the said most-significant byte exponent bits data that obtain from receiver and converts 16 growth daties into, and the most-significant byte of said 16 growth daties is said most-significant byte exponent bits data, and the least-significant byte of said 16 growth daties is complete 0;
Requestor is inquired about said storer and is obtained and corresponding 16 data of tabling look-up of said low 10 decimal digits certificate;
Totalizer reads said 16 growth daties and obtains 16 corresponding scale-of-two fixed-point numbers of said 18 binary-floating-point datas to logarithmic data with said 16 the data additions of tabling look-up that obtain from requestor from buffer.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106597098A (en) * | 2016-11-09 | 2017-04-26 | 深圳市鼎阳科技有限公司 | Data processing method and device for spectrum analyzer |
| CN109583581A (en) * | 2018-11-30 | 2019-04-05 | 上海寒武纪信息科技有限公司 | Data conversion device and Related product |
| US10997394B2 (en) | 2017-10-20 | 2021-05-04 | Huawei Technologies Co., Ltd. | Fingerprint information obtaining method and fingerprint recognition apparatus |
| US11249721B2 (en) | 2017-09-19 | 2022-02-15 | Huawei Technologies Co., Ltd. | Multiplication circuit, system on chip, and electronic device |
| US11249143B2 (en) | 2017-11-14 | 2022-02-15 | Huawei Technologies Co., Ltd. | Charging apparatus and charging system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6144977A (en) * | 1995-07-10 | 2000-11-07 | Motorola, Inc. | Circuit and method of converting a floating point number to a programmable fixed point number |
| CN1677308A (en) * | 2004-04-02 | 2005-10-05 | 明基电通股份有限公司 | Logarithmic converting method and device |
| CN101639768A (en) * | 2008-07-29 | 2010-02-03 | 索尼株式会社 | Apparatus, method, and program for arithmetic processing |
-
2011
- 2011-10-21 CN CN201110321509.2A patent/CN102436365B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6144977A (en) * | 1995-07-10 | 2000-11-07 | Motorola, Inc. | Circuit and method of converting a floating point number to a programmable fixed point number |
| CN1677308A (en) * | 2004-04-02 | 2005-10-05 | 明基电通股份有限公司 | Logarithmic converting method and device |
| CN101639768A (en) * | 2008-07-29 | 2010-02-03 | 索尼株式会社 | Apparatus, method, and program for arithmetic processing |
Non-Patent Citations (2)
| Title |
|---|
| ANDREA G. M. CILIO等: "Floating Point to Fixed Point Conversion of C Code", 《COMPILER CONSTRUCTION》 * |
| 裴志军等: "数字滤波器设计中浮点到定点转换技术", 《天津工程师范学院学报》 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106597098A (en) * | 2016-11-09 | 2017-04-26 | 深圳市鼎阳科技有限公司 | Data processing method and device for spectrum analyzer |
| CN106597098B (en) * | 2016-11-09 | 2019-11-12 | 深圳市鼎阳科技有限公司 | A kind of data processing method and device of spectrum analyzer |
| US11249721B2 (en) | 2017-09-19 | 2022-02-15 | Huawei Technologies Co., Ltd. | Multiplication circuit, system on chip, and electronic device |
| US10997394B2 (en) | 2017-10-20 | 2021-05-04 | Huawei Technologies Co., Ltd. | Fingerprint information obtaining method and fingerprint recognition apparatus |
| US11249143B2 (en) | 2017-11-14 | 2022-02-15 | Huawei Technologies Co., Ltd. | Charging apparatus and charging system |
| CN109583581A (en) * | 2018-11-30 | 2019-04-05 | 上海寒武纪信息科技有限公司 | Data conversion device and Related product |
| CN109583581B (en) * | 2018-11-30 | 2021-07-09 | 上海寒武纪信息科技有限公司 | Data conversion device and related product |
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