CN102436365B - Method and device for transforming high-speed linear spectrum data to logarithm data - Google Patents
Method and device for transforming high-speed linear spectrum data to logarithm data Download PDFInfo
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- CN102436365B CN102436365B CN201110321509.2A CN201110321509A CN102436365B CN 102436365 B CN102436365 B CN 102436365B CN 201110321509 A CN201110321509 A CN 201110321509A CN 102436365 B CN102436365 B CN 102436365B
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Abstract
The invention discloses a method and device for transforming linear spectrum data in spectrum analyzer to logarithm data. The method comprises the following steps of: respectively transforming 10 bits binary decimal points to 16 bits table lookup data and storing the data in a memory; classifying 18 bits binary floating point data into high 8 bits index bit data and low 10 bits decimal point bit data; expanding 8 bits full-0 low 8 bits to the high 8 bits index bit data to form 16 bits expanding data; obtaining the 16 bits table lookup data corresponding to the low 10 bits decimal point bit by the table lookup memory; summing the 16 bits expanding data and 16 bits table lookup data and obtaining 16 bits binary fixed point number logarithm data. The invention implements the high-speed transformation of linear spectrum data to logarithm data on a field programmable gata array (FPGA) by flexibly utilizing the table lookup, bit number expansion and summing calculation; the operation treatment speed is faster; and the resource of a multiplier is saved.
Description
Technical field
The present invention relates to spectrum analysis field, be specifically related to a kind of spectrum analyzer neutral line frequency spectrum data and be converted to the method for logarithmic data and device.
Background technology
Spectrum analyzer is the instrument of research electric signal spectrum structure, measurement for signal parameters such as signal distortion, percentage modulation spectral purity, frequency stability and crosstalks, also can, in order to some parameter of the Circuits System such as measuring amplifier and wave filter, be a kind of multiduty electronic measuring instrument.Spectrum analyzer is generally comprised of several parts such as signal acquisition module, AD modular converter, FFT processing module and output display modules, its principle of work is: signal acquisition module gathers measured signal, the output signal of local oscillator and each frequency component in measured signal are carried out successively difference frequency conversion in frequency mixer, the intermediate-freuqncy signal producing is by amplifying, then by AD modular converter, be transformed into after digital signal, carry out FFT Fourier analysis, to number conversion and be presented on display screen.
The performance of spectrum analyzer depends primarily on FFT and the performance to number conversion, become logarithmic relationship with number of sampling operation time, therefore, in high precision, high performance spectrum analyzer, generally adopt digital signal processor (DSP) auxiliary process, to improve FFT arithmetic speed, particularly in real time spectral analysis, need DSP to adopt FPGA to do in real time FFT calculation process, then FFT result is carried out number conversion output.Wherein, it is an important step of frequency spectrum processing that linear spectral data are converted to logarithmic data, its objective is the relativity for better display.Because the handling capacity of data in to number conversion process is very high, the circumstances that even there will be DSP to tackle.Therefore, existing processing mode is that logarithm operation is resolved into power series, is meeting on the basis of operational precision, and the first few items of exponentiation progression, obtains by computing, as (1) formula:
And under the conversion accuracy of ± 0.05dB, the first six of power series and substantially can meet accuracy requirement, therefore (1) formula can be reduced to:
Realize such a computing, take at present two kinds of methods, a kind of is that another kind is in FPGA, to utilize multiplier, totalizer to carry out computing by the processor computing that programs.
But above-mentioned two kinds of disposal routes all exist certain defect, the shortcoming that logarithm operation is decomposed into power series computing is that arithmetic speed is slow.Adopt multiplier, totalizer and the logical resource construction operation unit of FPGA can reach higher arithmetic speed, yet, its highest point reason speed is limited by the arithmetic speed of multiplier, highest point reason data speed only can reach 80MHz left and right, and structure (2) formula at least needs 10 multipliers, need to consume a large amount of multiplier resources.
Summary of the invention
Technical matters to be solved by this invention is to solve in spectrum analyzer, and linear spectral data are converted to the slow-footed problem of logarithm data operation.
In order to solve the problems of the technologies described above, the technical solution adopted in the present invention is to provide a kind of spectrum analyzer neutral line frequency spectrum data and is converted to the method to logarithmic data, comprises the following steps:
A10, ten binary fraction 10 0,000 0000～11 1,111 1111 are converted to respectively to 16 data of tabling look-up are stored in storer successively, and set up the one-to-one relationship table of ten binary fraction 10 0,000 0000～11 1,111 1111 and described 16 data of tabling look-up; Conversion method is: establishing ten represented decimal numbers of binary fraction is A, first calculates (lnA/ln2) * 2
8, then the result obtaining is rounded to 16 binary complement representations of rear use;
A20, by 18 binary-floating-point datas after FFT conversion and be divided into most-significant byte exponent bits data and low 10 decimal digits certificates;
A30, described most-significant byte exponent bits data are expanded to 16 growth daties, wherein, described most-significant byte exponent bits data are as the most-significant byte of described 16 growth daties, and the least-significant byte of described 16 growth daties is full 0;
A40, the described mapping table of setting up by steps A 10 search described storer and obtain 16 data of tabling look-up corresponding to described low 10 decimal places;
A50, by described 16 growth daties and described 16 data of tabling look-up that obtain of tabling look-up be added and obtain 16 scale-of-two fixed-point numbers corresponding to 18 binary-floating-point datas to logarithmic data.
The present invention also provides a kind of spectrum analyzer neutral line frequency spectrum data to be converted to the device to logarithmic data, comprise storer, receiver, buffer, requestor and totalizer, in described storer, store 16 data of tabling look-up, described 16 data of tabling look-up are corresponding one by one with 10 binary fraction 10 0,000 0000～11 11111111 respectively; Corresponding relation is: establishing ten represented decimal numbers of binary fraction is A, first calculates (lnA/ln2) * 2
8, then the result obtaining is rounded to 16 binary complement representations of rear use; Described receiver receives 18 binary-floating-point datas after FFT conversion and is divided into most-significant byte exponent bits data and low 10 decimal digits certificates; Described buffer receives the described most-significant byte exponent bits data that obtain from receiver and is converted to 16 growth daties, and the most-significant byte of described 16 growth daties is described most-significant byte exponent bits data, and the least-significant byte of described 16 growth daties is full 0; Described requestor is inquired about described storer and is obtained with described low 10 decimal digits according to 16 corresponding data of tabling look-up; Described totalizer reads described 16 growth daties and is added and obtains 16 scale-of-two fixed-point numbers corresponding to described 18 binary-floating-point datas to logarithmic data with described 16 data of tabling look-up that obtain from requestor from buffer.
The present invention, utilize dexterously table look-up, figure place is expanded, addition calculation, on FPGA, realized in spectrum analyzer linear spectral data to the high-speed transitions to logarithmic data.Specifically, because in FPGA, the pipeline system access speed of storer can reach 200MHz, and the totalizer of 16 can meet 200MHz substantially, and therefore, calculation process speed is faster, and saves the resource of multiplier.
Accompanying drawing explanation
Fig. 1 is 18 binary floating point numerical representation schematic diagram;
Fig. 2 is that spectrum analyzer neutral line frequency spectrum data provided by the invention is converted to the workflow block diagram to logarithmic data.
Embodiment
In spectrum analyzer, the spectrum signal after FFT processes is linear 18 binary floating point numbers, and is 16 scale-of-two fixed-point numbers through the spectrum signal to after number conversion.If the decimal number that 18 binary floating point numbers represent is X, the decimal number that 16 scale-of-two fixed-point numbers after number conversion are represented is Y, and the corresponding relation between the two is: Y=［ (lnX/ln2) * 2
8.The invention provides a kind of spectrum analyzer neutral line frequency spectrum data and be converted to the method for logarithmic data and device, for realizing the above-mentioned quick conversion to logarithmic data.
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
This specific embodiment be take the transfer process of 18 binary floating point numbers 00001011.1100000000 shown in a Fig. 1 and is described as example, and the decimal data of these 18 binary floating point number 00001011.1100000000 correspondences is 2
11* 0.75=1536, after conversion is (ln1536/ln2) * 2 to logarithmic data
8=2710.
Spectrum analyzer neutral line frequency spectrum data provided by the invention is converted to the method for logarithmic data as shown in Figure 2, comprises the following steps:
A10, the decimal with ten binary representations 10 0,000 0000～11 1,111 1111 are all converted to respectively to one 16 data of tabling look-up are stored in successively in storer, conversion method is, if ten decimal datas corresponding to binary fraction are A, first calculate (lnA/ln2) * 2
8, then the result obtaining is rounded to 16 binary complement representations of rear use.The decimal place 11 0,000 0000 of 18 binary floating point numbers 00001011.1100000000 of take is example, and the decimal number of 11 0,000 0000 correspondences is 0.75, according to formula, calculates (lnA/ln2) * 2
8=(ln0.75/ln2) * 2
8=-106.24, round as-106, by 16 two's complement, be expressed as 1,111 1,111 1,001 0110.
A20, set up decimal 10 0,000 0000～11 1,111 1111 of ten binary representations and the one-to-one relationship table of described 16 data of tabling look-up, according to this corresponding relation, can inquire about and obtain low 10 decimal digits of 18 binary floating point numbers according to 16 data of tabling look-up of correspondence;
A30,18 binary floating point numbers after FFT conversion are divided into most-significant byte exponent bits data and low 10 decimal digits certificates.
A40, described most-significant byte exponent bits data are expanded to 16 growth daties, wherein, most-significant byte exponent bits data are as the most-significant byte of described 16 growth daties, and the least-significant byte of 16 growth daties is full 0.For the present embodiment, 16 growth daties are 0,000 1,011 0,000 0000.
A50, the described mapping table of setting up by steps A 30 search storer and obtain 16 data of tabling look-up corresponding to described low 10 decimal places;
A60, by 16 growth daties and 16 data of tabling look-up obtaining of tabling look-up be added obtain the linear spectral data that represent with 18 binary floating point numbers to logarithmic data.For the present embodiment, after changing 16 of 18 binary floating point numbers 00001011.1100000000 are 0,000 1,011 0000 0,000,+11,111,111 1001 011,0=0,000 1,010 1,001 0110 to logarithmic data, and corresponding decimal value data are 2710.
Below in conjunction with instantiation, verify that spectrum analyzer neutral line frequency spectrum data provided by the invention is converted to the correctness to the method for logarithmic data.If the entire data of the most-significant byte of 18 binary floating point numbers is m, the small data of low 10 is n, and the decimal data of floating point representation is 2
m* n, asks logarithm to obtain ln (2 to it
m* n)=m * ln2+lnn.Because wish that the result of output is the integer representing with 16 bits, therefore result need to be multiplied by a conversion coefficient again and change, conversion coefficient is 2
8/ ln2, i.e. 256/ln2, like this, the integer of 16 binary representations should be to (m * 256+(lnn * 256)/ln2) ask the result after whole.
18 the binary floating point numbers (00001011.1100000000) of take are example, its most-significant byte exponent bits is 00001011, the integer data m=11 of expression, and decimal place is 1100000000, decimal data n=0.75 representing, asks logarithm to obtain to 18 binary floating point numbers: ln (2
11* 0.75)=11 * ln2+ln(0.75) ≈ 7.3369369, then to be multiplied by result after conversion coefficient be 2709.75, and changing whole is 2710, is shown: 0,000 1,010 1,001 0110 with 16 binary forms.Visible, its result is consistent with the resulting result of method provided by the invention.
In the present invention, the minimum data that 10 decimal places represent is 1000000000, corresponding decimal data is 0.5, and maximum data is 1111111111, and corresponding decimal data is 0.9990234375, maximum error value is 0000000001, carrying out maximum error value after number conversion is 20lg(1/512)=0.017dB, therefore, in the present invention, the data span of decimal place is 0.5～0.9990234375, and attainable precision is ± 0.017dB.
Because in FPGA, the pipeline system access speed of storer can reach 200MHz, the totalizer of 16 can meet 200MHz substantially, because spectrum analyzer neutral line frequency spectrum data provided by the invention is converted to, to the method for logarithmic data, can realize very high speed.
Buffer in Fig. 2 is 8 buffers, storer is 1024 * 16, buffer, storer and 16 totalizers are logical design in FPGA, FPGA take altera corp Stratix III series EP3SE80F1152C4 device, develop software and adopt the Quartus II of altera corp, 8.0,16 totalizers of version number are directly called the basic macroefficiency in basic macroefficiency (Megafunctions) storehouse.8 buffers call path C:/quartus8.0/libraries/megafuctions/storage/lpm_dff, and it is 8 that data bit width is set; Memory calls path is
C:/quartus8.0/libraries/megafuctions/storage/lpm_rom, it is 16 that output bit wide is set, capacity is 1024; 16 totalizers are called path
C:/quartus8.0/libraries/megafuctions/arithmetic/parallel _ add, arranges input quantity 2, input bit wide 16, and output bit wide 16, type of addition is symbolic number addition.
The present invention also provides a kind of spectrum analyzer neutral line frequency spectrum data to be converted to the device to logarithmic data, goodbye Fig. 2, comprise storer, receiver, buffer, requestor and totalizer, in described storer, store 16 data of tabling look-up, described 16 data of tabling look-up are corresponding one by one with 10 binary fraction 10 00000000～11 11 1111 respectively; Corresponding relation is: establishing ten represented decimal numbers of binary fraction is A, first calculates (lnA/ln2) * 2
8, then the result obtaining is rounded to 16 binary complement representations of rear use; Described receiver receives 18 binary-floating-point datas after FFT conversion and is divided into most-significant byte exponent bits data and low 10 decimal digits certificates; Described buffer receives the described most-significant byte exponent bits data that obtain from receiver and is converted to 16 growth daties, and the most-significant byte of described 16 growth daties is described most-significant byte exponent bits data, and the least-significant byte of described 16 growth daties is full 0; Described requestor is inquired about described storer and is obtained with described low 10 decimal digits according to 16 corresponding data of tabling look-up; Described totalizer reads described 16 growth daties and is added and obtains 16 scale-of-two fixed-point numbers corresponding to described 18 binary-floating-point datas to logarithmic data with described 16 data of tabling look-up that obtain from requestor from buffer.
The present invention is not limited to above-mentioned preferred forms, and anyone should learn the structural change of making under enlightenment of the present invention, and every have identical or close technical scheme with the present invention, within all falling into protection scope of the present invention.
Claims (2)
1. spectrum analyzer neutral line frequency spectrum data is converted to the method to logarithmic data, it is characterized in that comprising the following steps:
A10, ten binary fraction 10 0,000 0000～11 1,111 1111 are converted to respectively to 16 data of tabling look-up are stored in storer successively, and set up the one-to-one relationship table of ten binary fraction 10 0,000 0000～11 1,111 1111 and described 16 data of tabling look-up; Conversion method is: establishing ten represented decimal numbers of binary fraction is A, first calculates (lnA/ln2) * 2
8, then the result obtaining is rounded to 16 binary complement representations of rear use;
A20,18 binary-floating-point datas after FFT conversion are divided into most-significant byte exponent bits data and low 10 decimal digits certificates;
A30, described most-significant byte exponent bits data are expanded to 16 growth daties, wherein, described most-significant byte exponent bits data are as the most-significant byte of described 16 growth daties, and the least-significant byte of described 16 growth daties is full 0;
A40, the described mapping table of setting up by steps A 10 search described storer and obtain 16 data of tabling look-up corresponding to described low 10 decimal places;
A50, by described 16 growth daties and described 16 data of tabling look-up that obtain of tabling look-up be added and obtain 16 scale-of-two fixed-point numbers corresponding to 18 binary-floating-point datas to logarithmic data.
2. spectrum analyzer neutral line frequency spectrum data is converted to the device to logarithmic data, it is characterized in that comprising:
Storer, stores 16 data of tabling look-up in this storer, described 16 data of tabling look-up are corresponding one by one with 10 binary fraction 10 0,000 0000～11 1,111 1111 respectively; Corresponding relation is: establishing ten represented decimal numbers of binary fraction is A, first calculates (lnA/ln2) * 2
8, then the result obtaining is rounded to 16 binary complement representations of rear use;
Receiver, receives 18 binary-floating-point datas after FFT conversion and is divided into most-significant byte exponent bits data and low 10 decimal digits certificates;
Buffer, receives the described most-significant byte exponent bits data that obtain from receiver and is converted to 16 growth daties, and the most-significant byte of described 16 growth daties is described most-significant byte exponent bits data, and the least-significant byte of described 16 growth daties is full 0;
Requestor, inquires about described storer and obtains with described low 10 decimal digits according to 16 corresponding data of tabling look-up;
Totalizer reads described 16 growth daties and is added and obtains 16 scale-of-two fixed-point numbers corresponding to described 18 binary-floating-point datas to logarithmic data with described 16 data of tabling look-up that obtain from requestor from buffer.
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| CN106597098B (en) * | 2016-11-09 | 2019-11-12 | 深圳市鼎阳科技有限公司 | A kind of data processing method and device of spectrum analyzer |
| CN109521994B (en) | 2017-09-19 | 2020-11-10 | 华为技术有限公司 | Multiplication hardware circuit, system on chip and electronic equipment |
| CN109697402B (en) | 2017-10-20 | 2020-10-16 | 华为技术有限公司 | Fingerprint information acquisition method and fingerprint identification device |
| CN109787305B (en) | 2017-11-14 | 2024-05-14 | 华为技术有限公司 | Charging device and charging system |
| CN109583581B (en) * | 2018-11-30 | 2021-07-09 | 上海寒武纪信息科技有限公司 | Data conversion device and related product |
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