CN102361443A

CN102361443A - Single-event-upset resistant resettable scan structure D trigger

Info

Publication number: CN102361443A
Application number: CN2011103239275A
Authority: CN
Inventors: 池雅庆; 孙永节; 李鹏; 梁斌; 杜延康; 刘祥远; 陈建军; 何益百; 秦军瑞
Original assignee: National University of Defense Technology
Current assignee: National University of Defense Technology
Priority date: 2011-10-21
Filing date: 2011-10-21
Publication date: 2012-02-22
Anticipated expiration: 2031-10-21
Also published as: CN102361443B

Abstract

The invention discloses a single-event-upset resistant resettable scan structure D trigger, and aims to improve the single-event-upset resistance of the single-event-upset resistant resettable scan structure D trigger. The single-event-upset resistant resettable scan structure D trigger consists of a clock circuit, a scanning control buffer circuit, a reset buffer circuit, a master latch, a slave latch and an output buffer circuit, wherein the master latch consists of eighteen P-type metal-oxide semiconductor (PMOS) tubes and eighteen N-type metal-oxide semiconductor (NMOS) tubes; the slave latch consists of twelve PMOS tubes and twelve NMOS tubes; and both the master latch and the slave latch are subjected to duplication redundancy reinforcement, and clocked complementary metal-oxide semiconductor (C<2>MOS) circuit structures in the master latch and the slave latch are improved, namely pull-up circuits and pull-down circuits in mutually redundant C<2>MOS circuits are separated. The single-event-upset resistant resettable scan structure D trigger is strong in single-event-upset resistance, is applicable to a standard cell library of a single-event-upset resistant reinforcement integrated circuit, and is used in the fields of aviation, space flight and the like.

Description

Anti-single particle overturns reducible Scan Architecture d type flip flop

Technical field

The present invention relates to a kind of D master-slave flip-flop with resetting structure and Scan Architecture, more particularly to a kind of anti-single particle upset (signal event upset) reducible Scan Architecture d type flip flop.

Background technology

In cosmic space, there is a large amount of high energy particles (proton, electronics, heavy ion) and charged particle.After bombardment of the integrated circuit by these high energy particles and charged particle, electronic impulse can be produced in integrated circuit, may overturn the original level of IC interior node, this effect is referred to as single-particle inversion (SEU).LET (linear energy transfer) value of single-particle bombardment integrated circuit is higher, and the electronic impulse of generation is stronger.The integrated circuit used in Aeronautics and Astronautics field can all be threatened by single-particle inversion, make integrated circuit operation unstable, or even produce fatal mistake, therefore it is particularly important to develop advanced integrated circuit anti-single particle upset reinforcement technique.

The anti-single particle upset reinforcement technique of integrated circuit can be divided into system-level reinforcing, circuit-level and reinforce and device level reinforcing.The IC reliability of system-level reinforcing is high, but chip area is big, power consumption is big, the speed of service is slow.The integrated circuit speed of service that device level is reinforced is fast, and chip area is small, low in energy consumption, but device level is reinforced and realizes that difficulty is big, high cost.The IC reliability that circuit-level is reinforced is high, and chip area, power consumption and the speed of service are better than the integrated circuit of system-level reinforcing, and realizes that difficulty and cost are less than the integrated circuit that device level is reinforced, and is highly important integrated circuit anti-single particle upset reinforcement means.

D type flip flop is that, using one of most unit in sequential logical circuit, its anti-single particle upset ability directly determines the anti-single particle upset ability of integrated circuit.Circuit-level reinforcing is carried out to d type flip flop can effectively improve the anti-single particle upset ability of integrated circuit under less chip area, power consumption and cost.

Traditional d type flip flop is D master-slave flip-flop, is typically constituted by main latch and from level series of latches, and it is to realize the effective ways that d type flip flop anti-single particle is reinforced that the anti-single particle upset of latch, which is reinforced,." Upset Hardened Memory Design for Submicron CMOS Technology " (memory cell design is reinforced in the upset under sub-micron CMOS technology) (the 6th phases of December in 1996 volume 43 that T.Clain et al. is delivered on IEEE Transaction on Nuclear Science (IEEE atomic energy sciences journal), page 2874~2878) propose the latch that a kind of redundancy is reinforced, the latch adds a phase inverter and a backfeed loop on the basis of classical latch structure, circuit is mutually redundant with original phase inverter and backfeed loop.The input of N pipes is separated with the input of P pipes in phase inverter, and C in two backfeed loops, backfeed loop is connected respectively²Output of the input of the N pipes and P pipes of MOS circuits respectively from two phase inverters.The signal input of the latch and signal are preserved by C²MOS clock circuits are controlled.The redundancy reinforce latch advantage be：The trigging signal produced during one node of bombardment can return to original state by the correct level of corresponding node in its redundant circuit.The deficiency of latch that the redundancy is reinforced is：The C that input two is mutually redundant²MOS circuits share a pull-up PMOS and a pull-down NMOS pipe, make C in backfeed loop²There is an indirect pathway between the output node and redundant circuit corresponding node of MOS circuits, when single-particle bombardment makes the C²The level upset of MOS circuit output nodes, then the trigging signal can travel to the corresponding node of redundant circuit along indirect pathway, if the LET values of single-particle bombardment are higher, level upset can occur for two circuits being mutually redundant, and the output of latch is also overturn.The d type flip flop that traditional redundancy that the series of latches reinforced by two this kind of redundancies is constituted is reinforced, when the LET values that single-particle bombards are higher, then level upset also can occur for two circuits being mutually redundant, and the output of the d type flip flop of traditional redundancy reinforcing is also overturn." the The DF-DICE Storage Element for Immunity to Soft Errors " that R.Naseer et al. is delivered on the 48th IEEE International Midwest Symposium on Circuits and Systems (the 48th IEEE circuit and the international conference of system Midwest) (the DF-DICE memory cell that soft error is immunized) it is also proposed the latch that a kind of redundancy similar with above-mentioned latch structure is reinforced.Two C of this latch inputs²MOS circuits are completely self-contained, and indirect pathway is not present in corresponding node in two circuits for being mutually redundant, overcome the weak point for the latch that the redundancies of T.Clain et al. propositions is reinforced.But the latch that the redundancy that R.Naseer et al. is proposed is reinforced has used passgate structures in the feedback loop, when a node is overturn by single-particle bombardment, correct level is fed back to the node by its redundant circuit by transmission gate.Because the noise margin of passgate structures is relatively low, the signal feedback capability of backfeed loop is weaker, and when the LET values that single-particle bombards are higher, backfeed loop can not make the node recover correct level, has had a strong impact on latch anti-single particle upset ability.The d type flip flop that traditional redundancy that the series of latches reinforced by two this kind of redundancies is constituted is reinforced, when the LET values that single-particle bombards are higher, as the passgate structures in backfeed loop, the node can not be made to recover correct level, the d type flip flop anti-single particle upset ability that traditional redundancy is reinforced is have impact on.

Patent No. CN101499788A Chinese patent discloses the d type flip flop of a kind of anti-single particle upset and single event transient pulse.The invention is the d type flip flop that a kind of structure is similar to time sampling structure, including two variable connectors, two delay circuits, two protection gate circuits and three phase inverters, and the anti-single particle upset for realizing d type flip flop is reinforced.Due to shielding the electronic impulse that bombardment is produced using delay circuit and protection gate circuit; when the LET values that single-particle bombards are higher; electronic impulse width can be more than the time delay of delay circuit; the output level of protection gate circuit is overturn, the anti-single particle upset ability of the d type flip flop is greatly reduced.

Common D master-slave flip-flop is unfavorable for detecting circuit in test phase so that test job becomes very cumbersome, complexity.Scan Architecture is added on common D master-slave flip-flop architecture basics, can effectively simplify circuit test work, i.e., the input of D master-slave flip-flop can be controlled by scanning signal in test phase, and then control circuit state.

Some integrated circuits need to control the state of d type flip flop in integrated circuit, force d type flip flop output low level and the data wherein stored are set to logical zero.Increase reset circuit and reset signal input on the original architecture basics of Scan Architecture d type flip flop, it is possible to achieve the resetting structure of d type flip flop, and control by reset signal the reset function of d type flip flop.But reducible Scan Architecture d type flip flop anti-single particle upset ability is not high at present, is unfavorable for using in the IC chip in the fields such as Aeronautics and Astronautics.

The content of the invention

The technical problem to be solved in the present invention is, the problem of reducible Scan Architecture d type flip flop anti-single particle upset ability is not high is overturn for current anti-single particle, propose that a kind of anti-single particle overturns reducible Scan Architecture d type flip flop, it can under the single-particle bombardment of higher LET values normal work without generation single-particle inversion.

Anti-single particle proposed by the present invention overturn reducible Scan Architecture d type flip flop by clock circuit, scan control buffer circuit, reset buffer circuit, main latch, constituted from latch, output buffer.

Anti-single particle of the present invention, which overturns reducible Scan Architecture d type flip flop, five inputs and two output ends.Five inputs are CK i.e. clock signal input terminal, D i.e. data signal input, SE i.e. scan control signal input, SI i.e. scan data input and RN i.e. reseting input signal respectively；Two output ends are Q and QN respectively, and Q and QN export a pair of opposite data-signals.

Clock circuit has an input and two output ends, and input is CK, and output end is C, CN.Clock circuit is a two-stage phase inverter, is made up of first order phase inverter and second level phase inverter；First order phase inverter is made up of the first PMOS and the first NMOS tube, the grid Pg1 connection CK of the first PMOS, the drain electrode Nd1 for Pd1 the first NMOS tubes of connection that drain, and is used as an output end CN of clock circuit.The grid Ng1 connection CK of first NMOS tube, drain electrode Nd1 connections Pd1；Second level phase inverter is made up of the second PMOS and the second NMOS tube, the grid Pg2 connection CN of the second PMOS, The drain electrode Nd2 for Pd2 the second NMOS tubes of connection that drain, and it is used as another output end C of clock circuit.The grid Ng2 connection CN of second NMOS tube, drain electrode Nd2 connections Pd2.Substrate connection power vd D, source electrode Ps1, Ps2 connection power vd D of first PMOS and the second PMOS；The Substrate ground VSS of first NMOS tube and the second NMOS tube, source electrode Ns1, Ns2 are also grounded VSS.

Scan control buffer circuit has an input and an output end, and input is SE, and output end is SEN.Scan control buffer circuit is made up of the 3rd PMOS and the 3rd NMOS tube.The substrate and source electrode Ps3 of 3rd PMOS are all connected with power vd D, and the substrate and source electrode Ns3 of the 3rd NMOS tube are grounded VSS.The drain electrode Nd3 of the NMOS tube of the grid Pg3 connection SE of 3rd PMOS, drain electrode Pd3 connection the 3rd, and it is used as the output end SEN of scan control circuit；The grid Ng3 connection SE of 3rd NMOS tube, drain electrode Nd3 connections Pd3.

Resetting buffer circuit has an input and an output end, and input is RN, and output end is R.It is an one-level phase inverter to reset buffer circuit, wherein the grid Pg37 connection RN of the 37th PMOS, the drain electrode Nd37 for the NMOS tube of Pd37 connections the 37th that drains simultaneously are used as the output R, source electrode Ps37 connection power vds D for resetting buffer circuit；37th NMOS tube grid Ng37 connection RN, drain electrode Nd37 connections Pd37, source electrode Ns37 ground connection VSS.

Main latch and the latch that redundancy reinforcing is from latch, and also include Scan Architecture in main latch.Main latch and from latch tandem, and with clock circuit and resetting buffer circuit and being connected.Main latch is connected with scan control buffer circuit again, is connected from latch with output buffer.

Main latch has seven inputs and an output end, and seven inputs are D, C, CN, SE, SEN, SI, R, and an output end is MO.Main latch is made up of 18 PMOSs and 18 NMOS tubes, substrate connection the power vd D, the Substrate ground VSS of all NMOS tubes of all PMOSs in main latch.The source of the PMOS of the grid Pg4 connection SI of 4th PMOS, drain electrode Pd4 connection the 5th Pole Ps5, source electrode Ps4 connection power vd D；The source electrode Ps8, source electrode Ps5 connections Pd4 of the PMOS of the grid Pg5 connection SEN of 5th PMOS, drain electrode Pd5 connection the 8th；The source electrode Ps7, source electrode Ps6 connection power vds D of the PMOS of the grid Pg6 connection SE of 6th PMOS, drain electrode Pd6 connection the 7th；The grid Pg7 connection D of 7th PMOS, drain electrode Pd7 connections Ps8, source electrode Ps7 connection Pd6；The drain electrode Nd4, source electrode Ps8 connections Pd5 of the NMOS tube of the grid Pg8 connection C of 8th PMOS, drain electrode Pd8 connection the 4th；The source electrode Ps10, source electrode Ps9 connection power vds D of the PMOS of the grid Pg9 connection SI of 9th PMOS, drain electrode Pd9 connection the tenth；The source electrode Ps13, source electrode Ps10 connections Pd9 of the PMOS of the grid Pg10 connection SEN of tenth PMOS, drain electrode Pd10 connection the 13rd；The source electrode Ps12, source electrode Ps11 connection power vds D of the PMOS of the grid Pg11 connection SE of 11st PMOS, drain electrode Pd11 connection the 12nd；The grid Pg12 connection D of 12nd PMOS, drain electrode Pd12 connections Ps13, source electrode Ps12 connection Pd11；The drain electrode Nd9, source electrode Ps13 connections Pd10 of the NMOS tube of the grid Pg13 connection C of 13rd PMOS, drain electrode Pd13 connection the 9th；The source electrode Ps15, source electrode Ps14 connection power vds D of the PMOS of the grid Pg14 connection R of 14th PMOS, drain electrode Pd14 connection the 15th；The drain electrode Nd14 of the NMOS tube of the grid Pg15 connection Pd8 of 15th PMOS, drain electrode Pd15 connection the 14th is simultaneously used as the output MO of main latch, source electrode Ps15 connections Pd14；The source electrode Ps17, source electrode Ps16 connection power vds D of the PMOS of the grid Pg16 connection R of 16th PMOS, drain electrode Pd16 connection the 17th；The drain electrode Nd16, source electrode Ps17 connections Pd16 of the NMOS tube of the grid Pg17 connection Pd13 of 17th PMOS, drain electrode Pd17 connection the 16th；The source electrode Ps19, source electrode Ps18 connection power vds D of the PMOS of the grid Pg18 connection Pd17 of 18th PMOS, drain electrode Pd18 connection the 19th；The drain electrode Nd18, source electrode Ps19 connections Pd18 of the NMOS tube of the grid Pg19 connection CN of 19th PMOS, drain electrode Pd19 connection the 18th；The source electrode Ps21, source electrode Ps20 connection power vds D of the PMOS of the grid Pg20 connection Pd15 of 20th PMOS, drain electrode Pd20 connection the 21st；The The drain electrode Nd20, source electrode Ps21 connections Pd20 of the NMOS tube of the grid Pg21 connection CN of 21 PMOSs, drain electrode Pd21 connection the 20th；The drain electrode Nd5 of the NMOS tube of the grid Ng4 connection CN of 4th NMOS tube, drain electrode Nd4 connections Pd8, source electrode Ns4 connection the 5th；The drain electrode Nd6 of the NMOS tube of the grid Ng5 connection SE of 5th NMOS tube, drain electrode Nd5 connections Ns4, source electrode Ns5 connection the 6th；The grid Ng6 connection SI of 6th NMOS tube, drain electrode Nd6 connections Ns5, source electrode Ns6 ground connection VSS；The drain electrode Nd8 of the NMOS tube of the grid Ng7 connection D of 7th NMOS tube, drain electrode Nd7 connections Ns4, source electrode Ns7 connection the 8th；The grid Ng8 connection SEN of 8th NMOS tube, drain electrode Nd8 connections Ns7, source electrode Ns8 ground connection VSS；The drain electrode Nd10 of the NMOS tube of the grid Ng9 connection CN of 9th NMOS tube, drain electrode Nd9 connections Pd13, source electrode Ns9 connection the tenth；The drain electrode Nd11 of the NMOS tube of the grid Ng10 connection SE of tenth NMOS tube, drain electrode Nd10 connections Ns9, source electrode Ns10 connection the 11st；The grid Ng11 connection SI of 11st NMOS tube, drain electrode Nd11 connections Ns10, source electrode Ns11 ground connection VSS；The drain electrode Nd13 of the NMOS tube of the grid Ng12 connection D of 12nd NMOS tube, drain electrode Nd12 connections Ns9, source electrode Ns12 connection the 13rd；The grid Ng13 connection SEN of 13rd NMOS tube, drain electrode Nd13 connections Ns12, source electrode Ns13 ground connection VSS；The grid Ng14 connection Pd13 of 14th NMOS tube, drain electrode Nd14 connections Pd15, source electrode Ns14 ground connection VSS；The grid Ng15 connection R of 15th NMOS tube, drain electrode Nd15 connections Pd15, source electrode Ns15 ground connection VSS；The grid Ng16 connection Pd8 of 16th NMOS tube, drain electrode Nd16 connections Pd17, source electrode Ns16 ground connection VSS；The grid Ng17 connection R of 17th NMOS tube, drain electrode Nd17 connections Pd17, source electrode Ns17 ground connection VSS；The drain electrode Nd19 of the NMOS tube of the grid Ng18 connection C of 18th NMOS tube, drain electrode Nd18 connections Pd19, source electrode Ns18 connection the 19th；The grid Ng19 connection Pd15 of 19th NMOS tube, drain electrode Nd19 connections Ns18, source electrode Ns19 ground connection VSS；The drain electrode Nd21 of the NMOS tube of the grid Ng20 connection C of 20th NMOS tube, drain electrode Nd20 connections Pd21, source electrode Ns20 connection the 21st；21st The grid Ng21 connection Pd17 of NMOS tube, drain electrode Nd21 connections Ns20, source electrode Ns21 ground connection VSS.Scan Architecture in 4th PMOS, the 5th PMOS, the 6th PMOS and the 5th NMOS tube, the 6th NMOS tube, the 8th NMOS tube composition main latch.

There are four inputs and an output end from latch, four inputs are MO, C, CN, R, and an output end is SO.It is made up of from latch 12 PMOSs and 12 NMOS tubes, substrate connection the power vd D, the Substrate ground VSS of all NMOS tubes of all PMOSs from latch.The source electrode Ps23, source electrode Ps22 connection power vds D of the PMOS of the grid Pg22 connection MO of 22nd PMOS, drain electrode Pd22 connection the 23rd；The drain electrode Nd22, source electrode Ps23 connections Pd22 of the NMOS tube of the grid Pg23 connection CN of 23rd PMOS, drain electrode Pd23 connection the 22nd；The source electrode Ps25, source electrode Ps24 connection power vds D of the PMOS of the grid Pg24 connection MO of 24th PMOS, drain electrode Pd24 connection the 25th；The drain electrode Nd24, source electrode Ps25 connections Pd24 of the NMOS tube of the grid Pg25 connection CN of 25th PMOS, drain electrode Pd25 connection the 24th；The source electrode Ps27, source electrode Ps26 connection power vds D of the PMOS of the grid Pg26 connection R of 26th PMOS, drain electrode Pd26 connection the 27th；The drain electrode Nd26 of the NMOS tube of the grid Pg27 connection Pd25 of 27th PMOS, drain electrode Pd27 connection the 26th is simultaneously used as the output end SO from latch, source electrode Ps27 connection power supplys Pd26；The source electrode Ps29, source electrode Ps28 connection power vds D of the PMOS of the grid Pg28 connection R of 28th PMOS, drain electrode Pd28 connection the 29th；The drain electrode Nd28, source electrode Ps29 connections Pd28 of the NMOS tube of the grid Pg29 connection Pd23 of 29th PMOS, drain electrode Pd29 connection the 28th；The source electrode Ps31, source electrode Ps30 connection power vds D of the PMOS of the grid Pg30 connection Pd29 of 30th PMOS, drain electrode Pd30 connection the 31st；The drain electrode Nd30, source electrode Ps31 connections Pd30 of the NMOS tube of the grid Pg31 connection C of 31st PMOS, drain electrode Pd31 connection the 30th；The grid Pg32 connection Pd27 of 32nd PMOS, drain electrode Pd32 connection the 30th The source electrode Ps33 of three PMOSs, source electrode Ps32 connection power vd D；The drain electrode Nd32, source electrode Ps33 connections Pd32 of the NMOS tube of the grid Pg33 connection C of 33rd PMOS, drain electrode Pd33 connection the 32nd；The drain electrode Nd23 of the NMOS tube of the grid Ng22 connection C of 22nd NMOS tube, drain electrode Nd22 connections Pd23, source electrode Ns22 connection the 23rd；The grid Ng23 connection MO of 23rd NMOS tube, drain electrode Nd23 connections Ns22, source electrode Ns23 ground connection VSS；The drain electrode Nd25 of the NMOS tube of the grid Ng24 connection C of 24th NMOS tube, drain electrode Nd24 connections Pd25, source electrode Ns24 connection the 25th；The grid Ng25 connection MO of 25th NMOS tube, drain electrode Nd25 connections Ns24, source electrode Ns25 ground connection VSS；The grid Ng26 connection Pd23 of 26th NMOS tube, drain electrode Nd26 connections Pd27, source electrode Ns26 ground connection VSS；The grid Ng27 connection R of 27th NMOS tube, drain electrode Nd27 connections Pd27, source electrode Ns27 ground connection VSS；The grid Ng28 connection Pd25 of 28th NMOS tube, drain electrode Nd28 connections Pd29, source electrode Ns28 ground connection VSS；The grid Ng29 connection R of 29th NMOS tube, drain electrode Nd29 connections Pd29, source electrode Ns29 ground connection VSS；The drain electrode Nd31 of the NMOS tube of the grid Ng30 connection CN of 30th NMOS tube, drain electrode Nd30 connections Pd31, source electrode Ns30 connection the 31st；The grid Ng31 connection Pd27 of 31st NMOS tube, drain electrode Nd31 connections Ns30, source electrode Ns31 ground connection VSS；The drain electrode Nd33 of the NMOS tube of the grid Ng32 connection CN of 32nd NMOS tube, drain electrode Nd32 connections Pd33, source electrode Ns32 connection the 33rd；The grid Ng33 connection Pd29 of 33rd NMOS tube, drain electrode Nd33 connections Ns32, source electrode Ns33 ground connection VSS.

Output buffer has an input and two output ends, and an input is SO, and two output ends are QN, Q.Output buffer is made up of three PMOSs and three NMOS tubes, substrate connection the power vd D, the Substrate ground VSS of all NMOS tubes of all PMOSs in output buffer.The drain electrode Nd34, source electrode Ps34 connection power vds D of the NMOS tube of the grid Pg34 connection SO of 34th PMOS, drain electrode Pd34 connection the 34th；The grid Pg35 connections of 35th PMOS The drain electrode Nd35 of the NMOS tube of SO, drain electrode Pd35 connection the 35th is simultaneously used as output a QN, source electrode Ps35 connection power vds D of buffer circuit；The drain electrode Nd36 of the NMOS tube of the grid Pg36 connection Pd34 of 36th PMOS, drain electrode Pd36 connection the 36th is simultaneously used as output a Q, source electrode Ps36 connection power vds D of buffer circuit；The grid Ng34 connection SO of 34th NMOS tube, drain electrode Nd34 connections Pd34, source electrode Ns34 ground connection VSS；The grid Ng35 connection SO of 35th NMOS tube, drain electrode Nd35 connections Pd35, source electrode Ns35 ground connection VSS；The grid Ng36 connection Pd34 of 36th NMOS tube, drain electrode Nd36 connections Pd36, source electrode Ns36 ground connection VSS.

It is as follows that anti-single particle of the present invention overturns reducible Scan Architecture d type flip flop course of work：

The reducible Scan Architecture d type flip flop of anti-single particle upset of the present invention can also pass through reset state, i.e. scanning mode and reset state in the when marquis in scanning mode to be existed simultaneously.Anti-single particle of the present invention, which overturns reducible Scan Architecture d type flip flop, to be resetted at any time, and reset function is that set signal input part is controlled by RN.

When RN is that low level, SE are any level, anti-single particle of the present invention overturns reducible Scan Architecture d type flip flop and enters reset state, i.e. main latch and from latch by latching logic by force " 0 ", the output end Q and QN of output buffer are respectively low level and high level；

When RN is that high level, SE are low level, anti-single particle of the present invention overturns reducible Scan Architecture d type flip flop and is in normal operating conditions, i.e. clock circuit receives CK, CK is entered after row buffering to produce respectively the CN anti-phase with CK and with Cs of the CK with phase, and CN and C are passed to main latch and from latch.Between CK is low period, CN is that high level, C are low level, and main latch is opened, and receives D and output and MOs of the D with phase after buffered are simultaneously carried out to it, preservation state is in from latch, the MO of main latch output is not received but the MO that a upper CK trailing edge is sampled is preserved；Between CK is high period, CN is that low level, C are high level, and main latch is in preservation state, before preservation D and output and MOs of the D with phase that one CK rising edge is sampled, open and receive the output MO of main latch from latch, and buffered and output and SOs of the MO with phase are carried out to MO.Output buffer will receive the output SO from latch at any time, SO is buffered and export the QN anti-phase with SO and with Qs of the SO with phase.

When RN is that high level, SE are high level, anti-single particle of the present invention overturns reducible Scan Architecture d type flip flop and is in scanning mode, i.e. clock circuit receives CK, CK is entered after row buffering to produce respectively the CN anti-phase with CK and with Cs of the CK with phase, and CN and C are passed to main latch and from latch.Between CK is low period, CN is that high level, C are low level, and main latch is opened, and receives SI and output and MOs of the SI with phase after buffered are simultaneously carried out to it, preservation state is in from latch, the MO of main latch output is not received but the MO that a upper CK trailing edge is sampled is preserved；Between CK is high period, CN is that low level, C are high level, and main latch is in preservation state, preserves SI and output and MOs of the SI with phase that previous CK rising edges are sampled, the output MO of main latch is opened and received from latch, and buffered and output and SOs of the MO with phase are carried out to MO.Output buffer will receive the output SO from latch at any time, SO is buffered and export the QN anti-phase with SO and with Qs of the SO with phase.

Following technique effect can be reached using the present invention：

The anti-single particle upset ability that anti-single particle of the present invention overturns reducible Scan Architecture d type flip flop reinforces reducible Scan Architecture d type flip flop better than the unguyed reducible Scan Architecture d type flip flop of tradition, the reducible Scan Architecture d type flip flop of time sampling reinforcing and traditional redundancy.Because the present invention is transformed the unguyed reducible Scan Architecture d type flip flop structure of tradition, duplication redundancy reinforcing has been carried out to main latch and from latch, and for main latch and the C from latch²MOS circuit structures are improved, that is, separate the C being mutually redundant²Pull-up circuit and pull-down circuit in MOS circuits, further increase the present invention Anti-single particle overturns the anti-single particle upset ability of reducible Scan Architecture d type flip flop.Anti-single particle of the present invention overturns reducible Scan Architecture d type flip flop and is suitable for the standard cell lib that integrated circuit is reinforced in anti-single particle upset, applied to fields such as Aeronautics and Astronautics.

Brief description of the drawings

Fig. 1 is that anti-single particle of the present invention overturns reducible Scan Architecture d type flip flop logical construction schematic diagram.

Fig. 2 is that anti-single particle of the present invention overturns clock circuit structural representation in reducible Scan Architecture d type flip flop.

Fig. 3 is that anti-single particle of the present invention overturns scan control buffer circuit structure schematic diagram in reducible Scan Architecture d type flip flop.

Fig. 4 is that anti-single particle of the present invention overturns reset buffer circuit structure schematic diagram in reducible Scan Architecture d type flip flop.

Fig. 5 is that anti-single particle of the present invention overturns main latch structural representation in reducible Scan Architecture d type flip flop.

Fig. 6 is that anti-single particle of the present invention is overturn in reducible Scan Architecture d type flip flop from latch structure schematic diagram.

Fig. 7 is that anti-single particle of the present invention overturns output buffer structural representation in reducible Scan Architecture d type flip flop.

Embodiment

Fig. 1 is that anti-single particle of the present invention overturns reducible Scan Architecture d type flip flop logical construction schematic diagram.The present invention by clock circuit (as shown in Figure 2), scan control buffer circuit (as shown in Figure 3), reset buffer circuit (as shown in Figure 4), main latch (as shown in Figure 5), constitute from latch (as shown in Figure 6) and output buffer (as shown in Figure 7).The present invention has five inputs and two output ends.Two Input is CK i.e. clock signal input terminal, D i.e. data signal input, SE i.e. scan control signal input, SI i.e. scan data input and RN i.e. reseting input signal respectively；Two output ends are Q and QN respectively, and Q and QN export a pair of opposite data-signals.Clock circuit receives CK, and C and CN are exported respectively after carrying out buffered to CK.Scan control buffer circuit enters row buffering, input and SEN anti-phase SE to SE, and in the incoming main latch of SEN.Reset buffer circuit and enter row buffering, input and R anti-phase RN to RN, and the incoming main latch of R and from latch.Main latch receives D, C, CN, SE, SEN, SI, R, and main latch carries out exporting MO after the processing such as latching under C, CN, SE, SE and R control to D or SI.MO, C, CN and R are received from latch, SO is exported after the processing such as latching to MO progress under C, N and R control from latch.Output buffer receives SO, and it is carried out to export Q and QN after buffered.When RN is that high level, SE are low level, anti-single particle of the present invention overturns reducible Scan Architecture d type flip flop and is in normal operating conditions；When RN is that high level, SE are high level, anti-single particle of the present invention overturns reducible Scan Architecture d type flip flop and is in scanning work state；When RN is low level, anti-single particle of the present invention overturns reducible Scan Architecture d type flip flop and enters reset state.

As shown in Fig. 2 clock circuit has an input and two output ends, input is CK, and output end is C, CN.Clock circuit is a two-stage phase inverter, and first order phase inverter is made up of the first PMOS and the first NMOS tube, the grid Pg1 connection CK of the first PMOS, the drain electrode Nd1 for Pd1 the first NMOS tubes of connection that drain, and is used as an output end CN of clock circuit.The grid Ng1 connection CK of first NMOS tube, drain electrode Nd1 connections Pd1；Second level phase inverter is made up of the second PMOS and the second NMOS tube, the grid Pg2 connection CN of the second PMOS, the drain electrode Nd2 for Pd2 the second NMOS tubes of connection that drain, and is used as another output end C of clock circuit.The grid Ng2 connection CN of second NMOS tube, drain electrode Nd2 connections Pd2.The substrate connection power supply of first PMOS and the second PMOS VDD, source electrode Ps1, Ps2 connection power vd D；The Substrate ground VSS of first NMOS tube and the second NMOS tube, source electrode Ns1, Ns2 are also grounded VSS.

As shown in figure 3, scan control buffer circuit has an input and an output end, input is SE, and output end is SEN.Scan control buffer circuit is made up of the 3rd PMOS and the 3rd NMOS tube.The substrate and source electrode Ps3 of 3rd PMOS are all connected with power vd D, and the substrate and source electrode Ns3 of the 3rd NMOS tube are grounded VSS.The drain electrode Nd3 of the NMOS tube of the grid Pg3 connection SE of 3rd PMOS, drain electrode Pd3 connection the 3rd, and it is used as the output end SEN of scan control circuit；The grid Ng3 connection SE of 3rd NMOS tube, drain electrode Nd3 connections Pd3.

As shown in figure 4, resetting buffer circuit has an input and an output end, input is RN, and output end is R.It is an one-level phase inverter to reset buffer circuit, wherein the grid Pg37 connection RN of the 37th PMOS, the drain electrode Nd37 for the NMOS tube of Pd37 connections the 37th that drains simultaneously are used as the output R, source electrode Ps37 connection power vds D for resetting buffer circuit；37th NMOS tube grid Ng37 connection RN, drain electrode Nd37 connections Pd37, source electrode Ns37 ground connection VSS.

As shown in figure 5, main latch has seven inputs and an output end, seven inputs are D, C, CN, SE, SEN, SI, R, and an output end is MO.Main latch is made up of 18 PMOSs and 18 NMOS tubes, substrate connection the power vd D, the Substrate ground VSS of all NMOS tubes of all PMOSs in main latch.The source electrode Ps5, source electrode Ps4 connection power vds D of the PMOS of the grid Pg4 connection SI of 4th PMOS, drain electrode Pd4 connection the 5th；The source electrode Ps8, source electrode Ps5 connections Pd4 of the PMOS of the grid Pg5 connection SEN of 5th PMOS, drain electrode Pd5 connection the 8th；The source electrode Ps7, source electrode Ps6 connection power vds D of the PMOS of the grid Pg6 connection SE of 6th PMOS, drain electrode Pd6 connection the 7th；The grid Pg7 connection D of 7th PMOS, drain electrode Pd7 connections Ps8, source electrode Ps7 connection Pd6；The NMOS of the grid Pg8 connection C of 8th PMOS, drain electrode Pd8 connection the 4th The drain electrode Nd4 of pipe, source electrode Ps8 connection Pd5；The source electrode Ps10, source electrode Ps9 connection power vds D of the PMOS of the grid Pg9 connection SI of 9th PMOS, drain electrode Pd9 connection the tenth；The source electrode Ps13, source electrode Ps10 connections Pd9 of the PMOS of the grid Pg10 connection SEN of tenth PMOS, drain electrode Pd10 connection the 13rd；The source electrode Ps12, source electrode Ps11 connection power vds D of the PMOS of the grid Pg11 connection SE of 11st PMOS, drain electrode Pd11 connection the 12nd；The grid Pg12 connection D of 12nd PMOS, drain electrode Pd12 connections Ps13, source electrode Ps12 connection Pd11；The drain electrode Nd9, source electrode Ps13 connections Pd10 of the NMOS tube of the grid Pg13 connection C of 13rd PMOS, drain electrode Pd13 connection the 9th；The source electrode Ps15, source electrode Ps14 connection power vds D of the PMOS of the grid Pg14 connection R of 14th PMOS, drain electrode Pd14 connection the 15th；The drain electrode Nd14 of the NMOS tube of the grid Pg15 connection Pd8 of 15th PMOS, drain electrode Pd15 connection the 14th is simultaneously used as the output MO of main latch, source electrode Ps15 connections Pd14；The source electrode Ps17, source electrode Ps16 connection power vds D of the PMOS of the grid Pg16 connection R of 16th PMOS, drain electrode Pd16 connection the 17th；The drain electrode Nd16, source electrode Ps17 connections Pd16 of the NMOS tube of the grid Pg17 connection Pd13 of 17th PMOS, drain electrode Pd17 connection the 16th；The source electrode Ps19, source electrode Ps18 connection power vds D of the PMOS of the grid Pg18 connection Pd17 of 18th PMOS, drain electrode Pd18 connection the 19th；The drain electrode Nd18, source electrode Ps19 connections Pd18 of the NMOS tube of the grid Pg19 connection CN of 19th PMOS, drain electrode Pd19 connection the 18th；The source electrode Ps21, source electrode Ps20 connection power vds D of the PMOS of the grid Pg20 connection Pd15 of 20th PMOS, drain electrode Pd20 connection the 21st；The drain electrode Nd20, source electrode Ps21 connections Pd20 of the NMOS tube of the grid Pg21 connection CN of 21st PMOS, drain electrode Pd21 connection the 20th；The drain electrode Nd5 of the NMOS tube of the grid Ng4 connection CN of 4th NMOS tube, drain electrode Nd4 connections Pd8, source electrode Ns4 connection the 5th；The drain electrode Nd6 of the NMOS tube of the grid Ng5 connection SE of 5th NMOS tube, drain electrode Nd5 connections Ns4, source electrode Ns5 connection the 6th；The grid Ng6 connection SI of 6th NMOS tube, drain Nd6 connection Ns5, Source electrode Ns6 is grounded VSS；The drain electrode Nd8 of the NMOS tube of the grid Ng7 connection D of 7th NMOS tube, drain electrode Nd7 connections Ns4, source electrode Ns7 connection the 8th；The grid Ng8 connection SEN of 8th NMOS tube, drain electrode Nd8 connections Ns7, source electrode Ns8 ground connection VSS；The drain electrode Nd10 of the NMOS tube of the grid Ng9 connection CN of 9th NMOS tube, drain electrode Nd9 connections Pd13, source electrode Ns9 connection the tenth；The drain electrode Nd11 of the NMOS tube of the grid Ng10 connection SE of tenth NMOS tube, drain electrode Nd10 connections Ns9, source electrode Ns10 connection the 11st；The grid Ng11 connection SI of 11st NMOS tube, drain electrode Nd11 connections Ns10, source electrode Ns11 ground connection VSS；The drain electrode Nd13 of the NMOS tube of the grid Ng12 connection D of 12nd NMOS tube, drain electrode Nd12 connections Ns9, source electrode Ns12 connection the 13rd；The grid Ng13 connection SEN of 13rd NMOS tube, drain electrode Nd13 connections Ns12, source electrode Ns13 ground connection VSS；The grid Ng14 connection Pd13 of 14th NMOS tube, drain electrode Nd14 connections Pd15, source electrode Ns14 ground connection VSS；The grid Ng15 connection R of 15th NMOS tube, drain electrode Nd15 connections Pd15, source electrode Ns15 ground connection VSS；The grid Ng16 connection Pd8 of 16th NMOS tube, drain electrode Nd16 connections Pd17, source electrode Ns16 ground connection VSS；The grid Ng17 connection R of 17th NMOS tube, drain electrode Nd17 connections Pd17, source electrode Ns17 ground connection VSS；The drain electrode Nd19 of the NMOS tube of the grid Ng18 connection C of 18th NMOS tube, drain electrode Nd18 connections Pd19, source electrode Ns18 connection the 19th；The grid Ng19 connection Pd15 of 19th NMOS tube, drain electrode Nd19 connections Ns18, source electrode Ns19 ground connection VSS；The drain electrode Nd21 of the NMOS tube of the grid Ng20 connection C of 20th NMOS tube, drain electrode Nd20 connections Pd21, source electrode Ns20 connection the 21st；The grid Ng21 connection Pd17 of 21st NMOS tube, drain electrode Nd21 connections Ns20, source electrode Ns21 ground connection VSS.Scan Architecture in 4th PMOS, the 5th PMOS, the 6th PMOS and the 5th NMOS tube, the 6th NMOS tube, the 8th NMOS tube composition main latch.

As shown in fig. 6, having four inputs and an output end from latch, four inputs are MO, C, CN, R, and an output end is SO.From latch by 12 PMOSs and 12 NMOS Pipe is constituted, substrate connection the power vd D, the Substrate ground VSS of all NMOS tubes of all PMOSs from latch.The source electrode Ps23, source electrode Ps22 connection power vds D of the PMOS of the grid Pg22 connection MO of 22nd PMOS, drain electrode Pd22 connection the 23rd；The drain electrode Nd22, source electrode Ps23 connections Pd22 of the NMOS tube of the grid Pg23 connection CN of 23rd PMOS, drain electrode Pd23 connection the 22nd；The source electrode Ps25, source electrode Ps24 connection power vds D of the PMOS of the grid Pg24 connection MO of 24th PMOS, drain electrode Pd24 connection the 25th；The drain electrode Nd24, source electrode Ps25 connections Pd24 of the NMOS tube of the grid Pg25 connection CN of 25th PMOS, drain electrode Pd25 connection the 24th；The source electrode Ps27, source electrode Ps26 connection power vds D of the PMOS of the grid Pg26 connection R of 26th PMOS, drain electrode Pd26 connection the 27th；The drain electrode Nd26 of the NMOS tube of the grid Pg27 connection Pd25 of 27th PMOS, drain electrode Pd27 connection the 26th is simultaneously used as the output end SO from latch, source electrode Ps27 connection power supplys Pd26；The source electrode Ps29, source electrode Ps28 connection power vds D of the PMOS of the grid Pg28 connection R of 28th PMOS, drain electrode Pd28 connection the 29th；The drain electrode Nd28, source electrode Ps29 connections Pd28 of the NMOS tube of the grid Pg29 connection Pd23 of 29th PMOS, drain electrode Pd29 connection the 28th；The source electrode Ps31, source electrode Ps30 connection power vds D of the PMOS of the grid Pg30 connection Pd29 of 30th PMOS, drain electrode Pd30 connection the 31st；The drain electrode Nd30, source electrode Ps31 connections Pd30 of the NMOS tube of the grid Pg31 connection C of 31st PMOS, drain electrode Pd31 connection the 30th；The source electrode Ps33, source electrode Ps32 connection power vds D of the PMOS of the grid Pg32 connection Pd27 of 32nd PMOS, drain electrode Pd32 connection the 33rd；The drain electrode Nd32, source electrode Ps33 connections Pd32 of the NMOS tube of the grid Pg33 connection C of 33rd PMOS, drain electrode Pd33 connection the 32nd；The drain electrode Nd23 of the NMOS tube of the grid Ng22 connection C of 22nd NMOS tube, drain electrode Nd22 connections Pd23, source electrode Ns22 connection the 23rd；The grid Ng23 connection MO of 23rd NMOS tube, drain electrode Nd23 connections Ns22, source electrode Ns23 ground connection VSS； The drain electrode Nd25 of the NMOS tube of the grid Ng24 connection C of 24th NMOS tube, drain electrode Nd24 connections Pd25, source electrode Ns24 connection the 25th；The grid Ng25 connection MO of 25th NMOS tube, drain electrode Nd25 connections Ns24, source electrode Ns25 ground connection VSS；The grid Ng26 connection Pd23 of 26th NMOS tube, drain electrode Nd26 connections Pd27, source electrode Ns26 ground connection VSS；The grid Ng27 connection R of 27th NMOS tube, drain electrode Nd27 connections Pd27, source electrode Ns27 ground connection VSS；The grid Ng28 connection Pd25 of 28th NMOS tube, drain electrode Nd28 connections Pd29, source electrode Ns28 ground connection VSS；The grid Ng29 connection R of 29th NMOS tube, drain electrode Nd29 connections Pd29, source electrode Ns29 ground connection VSS；The drain electrode Nd31 of the NMOS tube of the grid Ng30 connection CN of 30th NMOS tube, drain electrode Nd30 connections Pd31, source electrode Ns30 connection the 31st；The grid Ng31 connection Pd27 of 31st NMOS tube, drain electrode Nd31 connections Ns30, source electrode Ns31 ground connection VSS；The drain electrode Nd33 of the NMOS tube of the grid Ng32 connection CN of 32nd NMOS tube, drain electrode Nd32 connections Pd33, source electrode Ns32 connection the 33rd；The grid Ng33 connection Pd29 of 33rd NMOS tube, drain electrode Nd33 connections Ns32, source electrode Ns33 ground connection VSS.

As shown in fig. 7, output buffer has an input and two output ends, an input is SO, and two output ends are QN, Q.Output buffer is made up of three PMOSs and three NMOS tubes, substrate connection the power vd D, the Substrate ground VSS of all NMOS tubes of all PMOSs in output buffer.The drain electrode Nd34, source electrode Ps34 connection power vds D of the NMOS tube of the grid Pg34 connection SO of 34th PMOS, drain electrode Pd34 connection the 34th；The drain electrode Nd35 of the NMOS tube of the grid Pg35 connection SO of 35th PMOS, drain electrode Pd35 connection the 35th is simultaneously used as output a QN, source electrode Ps35 connection power vds D of buffer circuit；The drain electrode Nd36 of the NMOS tube of the grid Pg36 connection Pd34 of 36th PMOS, drain electrode Pd36 connection the 36th is simultaneously used as output a Q, source electrode Ps36 connection power vds D of buffer circuit；The grid Ng34 of 34th NMOS tube Connect SO, drain electrode Nd34 connections Pd34, source electrode Ns34 ground connection VSS；The grid Ng35 connection SO of 35th NMOS tube, drain electrode Nd35 connections Pd35, source electrode Ns35 ground connection VSS；The grid Ng36 connection Pd34 of 36th NMOS tube, drain electrode Nd36 connections Pd36, source electrode Ns36 ground connection VSS.

It is respectively 2.88MeVcm that Beijing Institute of Atomic Energy's H-13 tandem accelerators, which can produce LET values,²/mg、8.62MeV·cm²/mg、12.6MeV·cm²/ mg and 17.0MeVcm²/ mg four kinds of ground heavy ion irradiation test environments.It is respectively 2.88MeVcm by the LET values that traditional unguyed reducible Scan Architecture d type flip flop in normal operating conditions, the reducible Scan Architecture d type flip flop of traditional redundancy reinforcing, the time sampling reducible Scan Architecture d type flip flop of reinforcing and the reducible Scan Architecture d type flip flop of anti-single particle of the present invention upset are placed in Beijing Institute of Atomic Energy's H-13 tandem accelerators generation²/mg、8.62MeV·cm²/mg、12.6MeV·cm²/ mg and 17.0MeVcm²In/mg ground heavy ion irradiation test environment, observe whether each d type flip flop occurs single-particle inversion, obtain each d type flip flop and occur the minimum LET Value Datas that single-particle inversion needs.Table 1 is to test obtained traditional unguyed reducible Scan Architecture d type flip flop, tradition redundancy using the ground heavy particle irradiation of Beijing Institute of Atomic Energy's H-13 tandem accelerators progress to reinforce the minimum LET Value Datas that reducible Scan Architecture d type flip flop, the time sampling reducible Scan Architecture d type flip flop of reinforcing and anti-single particle of the present invention overturn reducible Scan Architecture d type flip flop generation single-particle inversion needs.The unguyed reducible Scan Architecture d type flip flop of tradition is 2.88MeVcm in LET values²/mg、8.62MeV·cm²/mg、12.6MeV·cm²/ mg and 17.0MeVcm²Single-particle inversion occurs during/mg ground heavy ion irradiation test environment work, it is 12.6MeVcm that traditional redundancy, which reinforces reducible Scan Architecture d type flip flop in LET values,²/ mg and 17.0MeVcm²Single-particle inversion occurs during/mg ground heavy ion irradiation test environment work, it is 8.62MeVcm that time sampling, which reinforces reducible Scan Architecture d type flip flop in LET values,²/mg、12.6MeV·cm²/ mg and 17.0MeVcm²/ mg ground heavy ion Single-particle inversion occurs during irradiation test environment work, it is 17.0MeVcm that anti-single particle of the present invention, which overturns reducible Scan Architecture d type flip flop only in LET values,²Occurs single-particle inversion during/mg ground heavy ion irradiation test environment work.It can be seen that from this table, minimum LET values reducible Scan Architecture d type flip flop more unguyed than tradition that the present invention occurs single-particle inversion and needed improves 343%, reducible Scan Architecture d type flip flop, which is reinforced, than traditional redundancy improves 35%, reducible Scan Architecture d type flip flop, which is reinforced, than time sampling improves 97%, therefore the anti-single particle upset ability of the present invention is better than the unguyed reducible Scan Architecture d type flip flop of tradition, reducible Scan Architecture d type flip flop is reinforced in time sampling and traditional redundancy reinforces reducible Scan Architecture d type flip flop, it is suitable for the standard cell lib that integrated circuit is reinforced in anti-single particle upset, applied to aviation, the fields such as space flight.

Table 1

Claims

1. a kind of anti-single particle overturns reducible Scan Architecture d type flip flop, anti-single particle overturn reducible Scan Architecture d type flip flop by clock circuit, scan control buffer circuit, reset buffer circuit, main latch, constituted from latch, output buffer, there are five inputs and two output ends, five inputs are CK i.e. clock signal input terminal, D i.e. data signal input, SE i.e. scan control signal input, SI i.e. scan data input and RN i.e. reseting input signal respectively；Two output ends are Q and QN respectively, and Q and QN export a pair of opposite data-signals；Clock circuit has an input and two output ends, and input is CK, and output end is C, CN；Clock circuit is a two-stage phase inverter, is made up of first order phase inverter and second level phase inverter；First order phase inverter is made up of the first PMOS and the first NMOS tube, the grid Pg1 connection CK of the first PMOS, the drain electrode Nd1 for Pd1 the first NMOS tubes of connection that drain, and is used as an output end CN of clock circuit；The grid Ng1 connection CK of first NMOS tube, drain electrode Nd1 connections Pd1；Second level phase inverter is made up of the second PMOS and the second NMOS tube, the grid Pg2 connection CN of the second PMOS, the drain electrode Nd2 for Pd2 the second NMOS tubes of connection that drain, and is used as another output end C of clock circuit；The grid Ng2 connection CN of second NMOS tube, drain electrode Nd2 connections Pd2；Substrate connection power vd D, source electrode Ps1, Ps2 connection power vd D of first PMOS and the second PMOS；The Substrate ground VSS of first NMOS tube and the second NMOS tube, source electrode Ns1, Ns2 are also grounded VSS；Scan control buffer circuit has an input and an output end, and input is SE, and output end is SEN；Scan control buffer circuit is made up of the 3rd PMOS and the 3rd NMOS tube；The substrate and source electrode Ps3 of 3rd PMOS are all connected with power vd D, and the substrate and source electrode Ns3 of the 3rd NMOS tube are grounded VSS；The drain electrode Nd3 of the NMOS tube of the grid Pg3 connection SE of 3rd PMOS, drain electrode Pd3 connection the 3rd, and it is used as the output end SEN of scan control circuit；The grid Ng3 connection SE of 3rd NMOS tube, drain electrode Nd3 connections Pd3；Resetting buffer circuit has an input and an output end, and input is RN, Output end is R；It is an one-level phase inverter to reset buffer circuit, wherein the grid Pg37 connection RN of the 37th PMOS, the drain electrode Nd37 for the NMOS tube of Pd37 connections the 37th that drains simultaneously are used as the output R, source electrode Ps37 connection power vds D for resetting buffer circuit；37th NMOS tube grid Ng37 connection RN, drain electrode Nd37 connections Pd37, source electrode Ns37 ground connection VSS；Output buffer has an input and two output ends, and an input is SO, and two output ends are QN, Q；Output buffer is made up of three PMOSs and three NMOS tubes, substrate connection the power vd D, the Substrate ground VSS of all NMOS tubes of all PMOSs in output buffer；The drain electrode Nd34, source electrode Ps34 connection power vds D of the NMOS tube of the grid Pg34 connection SO of 34th PMOS, drain electrode Pd34 connection the 34th；The drain electrode Nd35 of the NMOS tube of the grid Pg35 connection SO of 35th PMOS, drain electrode Pd35 connection the 35th is simultaneously used as output a QN, source electrode Ps35 connection power vds D of buffer circuit；The drain electrode Nd36 of the NMOS tube of the grid Pg36 connection Pd34 of 36th PMOS, drain electrode Pd36 connection the 36th is simultaneously used as output a Q, source electrode Ps36 connection power vds D of buffer circuit；The grid Ng34 connection SO of 34th NMOS tube, drain electrode Nd34 connections Pd34, source electrode Ns34 ground connection VSS；The grid Ng35 connection SO of 35th NMOS tube, drain electrode Nd35 connections Pd35, source electrode Ns35 ground connection VSS；The grid Ng36 connection Pd34 of 36th NMOS tube, drain electrode Nd36 connections Pd36, source electrode Ns36 ground connection VSS；Main latch and the latch that redundancy reinforcing is from latch, and also include Scan Architecture in main latch, main latch and from latch tandem, and be connected with clock circuit and reset buffer circuit, main latch is connected with scan control buffer circuit again, is connected from latch with output buffer；It is characterized in that main latch has seven inputs and an output end, seven inputs are D, C, CN, SE, SEN, SI, R, and an output end is MO；Main latch is made up of 18 PMOSs and 18 NMOS tubes, substrate connection the power vd D, the Substrate ground VSS of all NMOS tubes of all PMOSs in main latch；The PMOS of the grid Pg4 connection SI of 4th PMOS, drain electrode Pd4 connection the 5th Source electrode Ps5, source electrode Ps4 connection power vd D；The source electrode Ps8, source electrode Ps5 connections Pd4 of the PMOS of the grid Pg5 connection SEN of 5th PMOS, drain electrode Pd5 connection the 8th；The source electrode Ps7, source electrode Ps6 connection power vds D of the PMOS of the grid Pg6 connection SE of 6th PMOS, drain electrode Pd6 connection the 7th；The grid Pg7 connection D of 7th PMOS, drain electrode Pd7 connections Ps8, source electrode Ps7 connection Pd6；The drain electrode Nd4, source electrode Ps8 connections Pd5 of the NMOS tube of the grid Pg8 connection C of 8th PMOS, drain electrode Pd8 connection the 4th；The source electrode Ps10, source electrode Ps9 connection power vds D of the PMOS of the grid Pg9 connection SI of 9th PMOS, drain electrode Pd9 connection the tenth；The source electrode Ps13, source electrode Ps10 connections Pd9 of the PMOS of the grid Pg10 connection SEN of tenth PMOS, drain electrode Pd10 connection the 13rd；The source electrode Ps12, source electrode Ps11 connection power vds D of the PMOS of the grid Pg11 connection SE of 11st PMOS, drain electrode Pd11 connection the 12nd；The grid Pg12 connection D of 12nd PMOS, drain electrode Pd12 connections Ps13, source electrode Ps12 connection Pd11；The drain electrode Nd9, source electrode Ps13 connections Pd10 of the NMOS tube of the grid Pg13 connection C of 13rd PMOS, drain electrode Pd13 connection the 9th；The source electrode Ps15, source electrode Ps14 connection power vds D of the PMOS of the grid Pg14 connection R of 14th PMOS, drain electrode Pd14 connection the 15th；The drain electrode Nd14 of the NMOS tube of the grid Pg15 connection Pd8 of 15th PMOS, drain electrode Pd15 connection the 14th is simultaneously used as the output MO of main latch, source electrode Ps15 connections Pd14；The source electrode Ps17, source electrode Ps16 connection power vds D of the PMOS of the grid Pg16 connection R of 16th PMOS, drain electrode Pd16 connection the 17th；The drain electrode Nd16, source electrode Ps17 connections Pd16 of the NMOS tube of the grid Pg17 connection Pd13 of 17th PMOS, drain electrode Pd17 connection the 16th；The source electrode Ps19, source electrode Ps18 connection power vds D of the PMOS of the grid Pg18 connection Pd17 of 18th PMOS, drain electrode Pd18 connection the 19th；The drain electrode Nd18, source electrode Ps19 connections Pd18 of the NMOS tube of the grid Pg19 connection CN of 19th PMOS, drain electrode Pd19 connection the 18th；The source electrode Ps21, source electrode Ps20 connection power vds D of the PMOS of the grid Pg20 connection Pd15 of 20th PMOS, drain electrode Pd20 connection the 21st；21st PMOS Grid Pg21 connection CN, the drain electrode Nd20, source electrode Ps21 connections Pd20 of the NMOS tube of drain electrode Pd21 connections the 20th；The drain electrode Nd5 of the NMOS tube of the grid Ng4 connection CN of 4th NMOS tube, drain electrode Nd4 connections Pd8, source electrode Ns4 connection the 5th；The drain electrode Nd6 of the NMOS tube of the grid Ng5 connection SE of 5th NMOS tube, drain electrode Nd5 connections Ns4, source electrode Ns5 connection the 6th；The grid Ng6 connection SI of 6th NMOS tube, drain electrode Nd6 connections Ns5, source electrode Ns6 ground connection VSS；The drain electrode Nd8 of the NMOS tube of the grid Ng7 connection D of 7th NMOS tube, drain electrode Nd7 connections Ns4, source electrode Ns7 connection the 8th；The grid Ng8 connection SEN of 8th NMOS tube, drain electrode Nd8 connections Ns7, source electrode Ns8 ground connection VSS；The drain electrode Nd10 of the NMOS tube of the grid Ng9 connection CN of 9th NMOS tube, drain electrode Nd9 connections Pd13, source electrode Ns9 connection the tenth；The drain electrode Nd11 of the NMOS tube of the grid Ng10 connection SE of tenth NMOS tube, drain electrode Nd10 connections Ns9, source electrode Ns10 connection the 11st；The grid Ng11 connection SI of 11st NMOS tube, drain electrode Nd11 connections Ns10, source electrode Ns11 ground connection VSS；The drain electrode Nd13 of the NMOS tube of the grid Ng12 connection D of 12nd NMOS tube, drain electrode Nd12 connections Ns9, source electrode Ns12 connection the 13rd；The grid Ng13 connection SEN of 13rd NMOS tube, drain electrode Nd13 connections Ns12, source electrode Ns13 ground connection VSS；The grid Ng14 connection Pd13 of 14th NMOS tube, drain electrode Nd14 connections Pd15, source electrode Ns14 ground connection VSS；The grid Ng15 connection R of 15th NMOS tube, drain electrode Nd15 connections Pd15, source electrode Ns15 ground connection VSS；The grid Ng16 connection Pd8 of 16th NMOS tube, drain electrode Nd16 connections Pd17, source electrode Ns16 ground connection VSS；The grid Ng17 connection R of 17th NMOS tube, drain electrode Nd17 connections Pd17, source electrode Ns17 ground connection VSS；The drain electrode Nd19 of the NMOS tube of the grid Ng18 connection C of 18th NMOS tube, drain electrode Nd18 connections Pd19, source electrode Ns18 connection the 19th；The grid Ng19 connection Pd15 of 19th NMOS tube, drain electrode Nd19 connections Ns18, source electrode Ns19 ground connection VSS；The drain electrode Nd21 of the NMOS tube of the grid Ng20 connection C of 20th NMOS tube, drain electrode Nd20 connections Pd21, source electrode Ns20 connection the 21st；The grid Ng21 connection Pd17 of 21st NMOS tube, drain Nd21 Connect Ns20, source electrode Ns21 ground connection VSS；Scan Architecture in 4th PMOS, the 5th PMOS, the 6th PMOS and the 5th NMOS tube, the 6th NMOS tube, the 8th NMOS tube composition main latch；There are four inputs and an output end from latch, four inputs are MO, C, CN, R, and an output end is SO；It is made up of from latch 12 PMOSs and 12 NMOS tubes, substrate connection the power vd D, the Substrate ground VSS of all NMOS tubes of all PMOSs from latch；The source electrode Ps23, source electrode Ps22 connection power vds D of the PMOS of the grid Pg22 connection MO of 22nd PMOS, drain electrode Pd22 connection the 23rd；The drain electrode Nd22, source electrode Ps23 connections Pd22 of the NMOS tube of the grid Pg23 connection CN of 23rd PMOS, drain electrode Pd23 connection the 22nd；The source electrode Ps25, source electrode Ps24 connection power vds D of the PMOS of the grid Pg24 connection MO of 24th PMOS, drain electrode Pd24 connection the 25th；The drain electrode Nd24, source electrode Ps25 connections Pd24 of the NMOS tube of the grid Pg25 connection CN of 25th PMOS, drain electrode Pd25 connection the 24th；The source electrode Ps27, source electrode Ps26 connection power vds D of the PMOS of the grid Pg26 connection R of 26th PMOS, drain electrode Pd26 connection the 27th；The drain electrode Nd26 of the NMOS tube of the grid Pg27 connection Pd25 of 27th PMOS, drain electrode Pd27 connection the 26th is simultaneously used as the output end SO from latch, source electrode Ps27 connection power supplys Pd26；The source electrode Ps29, source electrode Ps28 connection power vds D of the PMOS of the grid Pg28 connection R of 28th PMOS, drain electrode Pd28 connection the 29th；The drain electrode Nd28, source electrode Ps29 connections Pd28 of the NMOS tube of the grid Pg29 connection Pd23 of 29th PMOS, drain electrode Pd29 connection the 28th；The source electrode Ps31, source electrode Ps30 connection power vds D of the PMOS of the grid Pg30 connection Pd29 of 30th PMOS, drain electrode Pd30 connection the 31st；The drain electrode Nd30, source electrode Ps31 connections Pd30 of the NMOS tube of the grid Pg31 connection C of 31st PMOS, drain electrode Pd31 connection the 30th；The source electrode Ps33, source electrode Ps32 connection power vds D of the PMOS of the grid Pg32 connection Pd27 of 32nd PMOS, drain electrode Pd32 connection the 33rd；The grid Pg33 connection C of 33rd PMOS, drain electrode Pd33 connections the The drain electrode Nd32 of 32 NMOS tubes, source electrode Ps33 connection Pd32；The drain electrode Nd23 of the NMOS tube of the grid Ng22 connection C of 22nd NMOS tube, drain electrode Nd22 connections Pd23, source electrode Ns22 connection the 23rd；The grid Ng23 connection MO of 23rd NMOS tube, drain electrode Nd23 connections Ns22, source electrode Ns23 ground connection VSS；The drain electrode Nd25 of the NMOS tube of the grid Ng24 connection C of 24th NMOS tube, drain electrode Nd24 connections Pd25, source electrode Ns24 connection the 25th；The grid Ng25 connection MO of 25th NMOS tube, drain electrode Nd25 connections Ns24, source electrode Ns25 ground connection VSS；The grid Ng26 connection Pd23 of 26th NMOS tube, drain electrode Nd26 connections Pd27, source electrode Ns26 ground connection VSS；The grid Ng27 connection R of 27th NMOS tube, drain electrode Nd27 connections Pd27, source electrode Ns27 ground connection VSS；The grid Ng28 connection Pd25 of 28th NMOS tube, drain electrode Nd28 connections Pd29, source electrode Ns28 ground connection VSS；The grid Ng29 connection R of 29th NMOS tube, drain electrode Nd29 connections Pd29, source electrode Ns29 ground connection VSS；The drain electrode Nd31 of the NMOS tube of the grid Ng30 connection CN of 30th NMOS tube, drain electrode Nd30 connections Pd31, source electrode Ns30 connection the 31st；The grid Ng31 connection Pd27 of 31st NMOS tube, drain electrode Nd31 connections Ns30, source electrode Ns31 ground connection VSS；The drain electrode Nd33 of the NMOS tube of the grid Ng32 connection CN of 32nd NMOS tube, drain electrode Nd32 connections Pd33, source electrode Ns32 connection the 33rd；The grid Ng33 connection Pd29 of 33rd NMOS tube, drain electrode Nd33 connections Ns32, source electrode Ns33 ground connection VSS.