CN104821804B - A kind of d type flip flop with clear terminal - Google Patents
A kind of d type flip flop with clear terminal Download PDFInfo
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- CN104821804B CN104821804B CN201510278562.7A CN201510278562A CN104821804B CN 104821804 B CN104821804 B CN 104821804B CN 201510278562 A CN201510278562 A CN 201510278562A CN 104821804 B CN104821804 B CN 104821804B
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Abstract
A kind of d type flip flop with clear terminal, including clock module, filtering wave by prolonging time module, principal and subordinate level DICE latch modules, output module；Wherein principal and subordinate's level DICE latch modules are according to the clock signal exported from clock module, and the external data signal received by the filtering wave by prolonging time module, and corresponding data-signal is exported to data outputting module.Principal and subordinate's level DICE latch modules are provided with clear terminal；The transient pulse that filtering wave by prolonging time module is used to prevent single particle effect from causing is entered into inside register；Principal and subordinate's level DICE latch modules overturn for correcting the internal node that single particle effect causes；Clear terminal is used for output end zero setting；Filtering wave by prolonging time module plays a part of anti-SET; principal and subordinate's level DICE latch modules avoid storage inside node from overturning, and play a part of anti-SEU, and protection band structure is added in layout design; the structure restrained effectively SEL, it helps reduce the SET pulse width in circuit.
Description
Technical field
The present invention relates to field of semiconductor devices, more particularly to a kind of d type flip flop with clear terminal.
Background technology
In radiation environment, the energy particle of surrounding can penetrate into chip internal to semiconductor devices, and ionising radiation occurs,
Electronics and the hole pair of certain amount are produced on the movement locus of energy particle.These are due to single energy particle ionising radiation
And the electronics and hole for producing are possible in the presence of electric field be absorbed by the internal node of circuit, cause semiconductor devices function
It is abnormal.Above-mentioned effect is referred to as single particle effect.
Single particle effect is a kind of stochastic effects.People were found that Binder, telecommunication satellite, JK flip-flop hair in 1975
Raw abnormal flop phenomenon, the factor for finding to trigger the abnormal flop phenomenon by constantly research includes the height in cosmic ray
Can proton, heavy ion, neutron, electronics and gamma-rays, and radioisotopic α particles contained by ceramic cartridge etc..Simple grain
Son upset (SEU) is taken place mostly in memory device and logic circuit.Find within 1979 that single high energy particle can cause CMOS devices
There is locking in part.Find within 1986 that single high energy particle can also cause power MOS (Metal Oxide Semiconductor) device that single event burnout occurs again.1987 again
It was found that single event gate rupture.Further simulated experiment and the test of satellite in orbit confirm that almost all of integrated circuit can be sent out
Raw single particle effect.
With the fast development of semiconductor technology, the integrated level of spacecraft semiconductor devices is improved constantly, the spy of device
Levy size less and less, operating voltage is less and less, correspondingly, critical charge is less and less, cause integrated circuit increasingly to hold
Easily there is single particle effect.D type flip flop is that most sequential devices is used in integrated circuit, and this device is turned over there is single-particle
Turn and single-ion transient state after, it will error message is remained, influence subsequent operation, so as to cause whole system mistake or collapse
Burst, cause serious consequence.Additionally, traditional d type flip flop will be presented labile state after the power-up, it is unfavorable for that system works.
The content of the invention
It is an object of the invention to provide a kind of d type flip flop with clear terminal, the anti-single particle for realizing d type flip flop is imitated
Should, it is ensured that the accuracy of d type flip flop output information.
A kind of d type flip flop with clear terminal, including clock module, filtering wave by prolonging time module, principal and subordinate's level DICE latch modules,
Output module, wherein principal and subordinate level DICE latch modules according to the clock signal exported from clock module, and by the time delay
The external data signal that filtration module is received, corresponding data-signal is exported to data outputting module.
Principal and subordinate's level DICE latch modules include main module and are provided with from level module, main module and from level module
Clear terminal.
Filtering wave by prolonging time module receives external data signal, and the external data signal of reception is divided into first via signal and the
Two road signals；The filtering wave by prolonging time module is filtered treatment to first via signal, and second road signal is not processed；When through prolonging
When filtering process first via signal it is identical with second road signal when, filtering wave by prolonging time module output data；At through filtering wave by prolonging time
When the first via signal of reason is different from second road signal, filtering wave by prolonging time module not output data.
Filtering wave by prolonging time module includes the first phase inverter, filtering wave by prolonging time path, through path, the first tristate inverter；First
External data is divided into first via signal and second road signal by phase inverter, and first via signal enters first after filtering wave by prolonging time path
Tristate inverter, second road signal is directly entered the first tristate inverter.
Include first to fourth from node from level module, be single-particle sensitive nodes from node, from node successively logic phase
It is adjacent.
Main module includes first to fourth host node, and host node is single-particle sensitive nodes, host node logic phase successively
It is adjacent；Host node and from node be physically spaced arrangement.
In some embodiments, four clear terminals are especially provided with main module, four is provided with from level module
Individual clear terminal.The effect of clear terminal is that, output zero setting, trigger has a fixed output when its benefit is the electricity on circuit
Signal, makes circuit be in a state for stabilization, and the trigger for being not added with clear terminal will easily be presented labile state after the power-up,
It is unfavorable for that system works, this trigger is generally used for the system for not considering power-up state.
Four host nodes and four are physically spaced arrangement from node.From four single-particle sensitive spots in level module, when
When one of sensitive spot occurs single-particle inversion, adjacent sensitive point can return error correcting, as long as avoiding adjacent sensitive
Point coverlet particle bombardment, you can ensure that the information of node is correct, main is also such.Therefore in laying out pattern in logic
Adjacent sensitive point is separated, and the sensitive dot interlace of principal and subordinate's level is put during layout.
In certain embodiments, the d type flip flop with clear terminal, can also include protection band, and the protection band of PMOS is by P+
Active composition, the protection band of NMOS tube is constituted by N+ is active, and protection band is both provided between single-particle sensitive nodes.Protection band
Width is using the active minimum widith in design rule.
In certain embodiments, the d type flip flop circuit with clear terminal can be cmos circuit, the intrinsic pnpn of cmos device
Four-layer structure forms a parasitic controllable silicon, and under single particle effect, the voltage drop on p traps resistance or resistance substrate may
So that longitudinal NPN or lateral PNP triode ON of parasitism, produce positive current feedback, ultimately result in two parasitic triodes and reach
To saturation, and saturation state is maintained, form the high current path from power supply to ground, cause circuit that breech lock occurs.
Adding protection band can reduce the gain of parasitic transistor, and control to lead to the voltage of interior trap and substrate, make parasitism
Transistor is unable to reach saturation, i.e., cannot produce circuit pathways, serves the effect of anti-breech lock.
Filtering wave by prolonging time path may include inverter module and filter unit, and inverter module is made up of even number of inverters,
It is anti-phase for time delay；Filter unit is used to filter pulse signal.
The number of inverter module can be according to increase the need for time delay length in practical application or reduction.
Clock module is used to export a pair of inversion signals.
According to above-mentioned d type flip flop, when transient pulse arrives, the pulse is prevented to enter into electricity by filtering wave by prolonging time module
Inside road, play a part of anti-SET (single event transient pulse).When storage inside node overturns, by DICE structures
Remove upset pulse rapidly, it is ensured that circuit output result is normal, plays a part of anti-SEU.Protection band is added in layout design
Structure, the structure restrained effectively SEL (single event latchup), it helps reduce the SET pulse width in circuit.So as to whole
Body circuit structure has the function of anti-single particle effect.The effect of set end is that output is put 1, and its benefit is the electricity on circuit
When trigger have a fixed output signal, circuit is in the state of stabilization.
Brief description of the drawings
Fig. 1 is the schematic diagram of the d type flip flop with clear terminal of an embodiment of the present invention；
Fig. 2 is the filtering wave by prolonging time module principle figure of an embodiment of the present invention；
Fig. 3 is the DICE unit schematic diagrams of an embodiment of the present invention；
Fig. 4 is the clock module circuit diagram of the d type flip flop with clear terminal of an embodiment of the present invention；
Fig. 5 is the filtering wave by prolonging time module principle figure of the d type flip flop with clear terminal of an embodiment of the present invention；
Fig. 6 is the filtering wave by prolonging time module circuit diagram of the d type flip flop with clear terminal of an embodiment of the present invention；
Fig. 7 is principal and subordinate's level DICE latch module circuit diagrams of the d type flip flop with clear terminal of an embodiment of the present invention；
Fig. 8 is the output module circuit diagram of the d type flip flop with clear terminal of an embodiment of the present invention；
The response ripple that Fig. 9 is bombarded for one node of d type flip flop with clear terminal of an embodiment of the present invention by single-particle
Shape figure.
Specific embodiment
Invention is described in further detail below in conjunction with the accompanying drawings.
As shown in figure 1, the d type flip flop with clear terminal of an embodiment of the present invention, including clock module 1, filtering wave by prolonging time
Module 2, principal and subordinate level DICE latch modules 3, output module 4.Principal and subordinate's level DICE latch modules include main module 31 and from
Level module 32.Principal and subordinate's two-stage has all carried out DICE reinforcings, and adds filtering wave by prolonging time module 2 in data terminal.
The clock signal output terminal of clock module 1 is connected with the clock signal input terminal of principal and subordinate level DICE latch modules 3,
The data input pin of filtering wave by prolonging time module 2 is connected with data source, the data of data output end and principal and subordinate level DICE latch modules 3
Input is connected, and the data output end of principal and subordinate level DICE latch modules 3 connects the signal input part of output module 4.
Principal and subordinate's level DICE latch modules include main module and are provided with from level module, main module and from level module
Clear terminal.
Fig. 2 gives the filtering wave by prolonging time module principle figure in an embodiment of the present invention.Figure includes two PMOS P00
With P01, two NMOS tube N00 and N01 and two phase inverter I65 and I66.Data enter from D ports.Only when a0 points and b0 points
When data are identical, the data could spread out of from OUT terminal.When a transient pulse occurs, a0 points are this pulse signal.Due to
There are two presence of phase inverter, transient pulse is filtered, b0 points maintain former data constant.Because a0, b0 point data are different, transient state
Pulse cannot pass to OUT terminal, it is to avoid the generation of wrong data.
Fig. 3 gives the circuit theory diagrams of the DICE units in an embodiment of the present invention.The circuit includes six PMOS
Pipe P0~P5, six NMOS tube N0~N5, six tristate inverters SR1, SR2 and phase inverter an I67, CK, CKN are anti-a pair
The clock signal of phase.There are four logic states to be respectively stored in four nodes a, b, c in unit, in d, the wherein shape of each node
State is separated by node and does not connect each other all by adjacent node control.
When a negative upset pulse appears in the node a that current state is " 1 ", can be by PMOS P2 in node b
One positive pulse-type disturbance of upper generation, but do not interfere with storage state of the storage in node c and d.Because negative upset pulse
Will not be transmitted by feeding back NMOS tube N5, and the positive pulse-type disturbance for being delivered to node b will not further be passed by PMOS P3
It is delivered to node c.Therefore, node a, b and node c, d are isolated, and node c, D-shaped are (common into the redundant node of node a, b
With redundancy structure is constituted, node a, d are mutually redundant, and node b, c are mutually redundant), when node a, b are interfered, node c, d
The logic state that remain them is unaffected.As can be seen here, bombardment of the single-particle to node is only to draw on node a and b
Play temporary transient disturbance.This disturbance will soon be eliminated after single event, because other two states of node c and d
By the state before forcing upset node to return to by the feedback effect of NMOS tube N2 and PMOS P0.Specific node c's
Status signal the node b of upset is returned to by NMOS tube N2 before state, the status signal of node d passes through PMOS P0
(same, when node c, d receive interference, node a, b keep their logic to state before the node a of upset is returned to
State before state is unaffected, and node a, b force node c, d to recover by feedback effect).For positive temporary disturbance
Pulse, the principle of the DICE element circuit disturbance rejections is similar to.
As shown in figure 4, clock module includes input end of clock CK, phase inverter I74, phase inverter I75, phase inverter I76, anti-phase
Device I77, wherein input end of clock CK connection phase inverter I75, the input of phase inverter I77, the output end connection of phase inverter I75 are anti-
The input of phase device I74, the input of the output end connection phase inverter I76 of phase inverter I77；The clock circuit exports four kinds of clocks
Signal CKN, CKNN, CK2N, CK2NN.
Clock is divided into two-way primarily to the driving force of enhancing clock, phase inverter I75, phase inverter I77 mainly make
With being output clock inversion signal, phase inverter I74, phase inverter I76 Main Functions are the stronger clock signals of generation ability, wherein
CKN, CK2N are in-phase signal, and CKNN, CK2NN are in-phase signal, while CKN, CKNN inversion signal each other.
As shown in figure 5, filtering wave by prolonging time module includes the first phase inverter 21, filtering wave by prolonging time path 22, through path 23, first
Tristate inverter 24.The input termination data source of the first phase inverter 21, the output end connection filtering wave by prolonging time of the first phase inverter 21 leads to
Road 22 and the input of through path 23.The output end of filtering wave by prolonging time path 22 and through path 23 connects the first tristate inverter
24 input.Filtering wave by prolonging time path 22 includes inverter module 221 and filter unit 222.Filtering wave by prolonging time path 22 filters wink
State pulse, through path 23 allows transient pulse to pass through.
Fig. 6 is the filtering wave by prolonging time module circuit diagram of the d type flip flop with clear terminal of an embodiment of the present invention.
Specifically, the first phase inverter is made up of PMOS P56, NMOS tube N55.
Inverter module 222 is made up of even number of inverters, anti-phase for time delay.Inverter module 222 herein is by two
Individual PMOS, two NMOS tubes are in series, and (source electrode of such as PMOS P55 connects power supply, and the drain electrode of PMOS P55 connects PMOS
The source electrode of P54, the drain electrode of PMOS P54 connects the source electrode of NMOS tube N52, and the drain electrode of NMOS tube N52 connects the source electrode of NMOS tube N53,
The grounded drain of NMOS tube N53).Filter unit is used to filter pulse signal.Filter unit is by a PMOS and a NMOS
(such as source electrode of PMOS P51, drain electrode connects power supply to pipe composition respectively, and the source electrode of NMOS tube N50, grid are grounded respectively, PMOS
P51, the grid of NMOS tube N50 are connected with each other).
The number of inverter module can be according to increase the need for time delay length in practical application or reduction.
When filtering wave by prolonging time module has pulse signal to be input into, the pulse signal transmission by through path is anti-phase to the first tri-state
Device, is filtered out by the pulse signal of filtering wave by prolonging time path, and the first tristate inverter is not received from filtering wave by prolonging time path
Pulse signal, i.e., the two paths of signals that now the first tristate inverter is received is obstructed, and now the first tristate inverter is without output, i.e.,
Whole filtering wave by prolonging time module is not exported, so as to ensure that whole d type flip flop is not influenceed by single-particle pulse signal, it is to avoid
The generation of wrong data.
Additionally, the output end of the first tristate inverter is also associated with phase inverter I78, phase inverter I79, for latching the one or three
The output of state phase inverter.
More specifically, filtering wave by prolonging time module include NMOS tube N43, N44, N45, N46, N47, N48, N49, N50, N51,
N52, N53, N54, N55, PMOS P44, P45, P46, P47, P48, P49, P50, P51, P52, P53, P54, P55, P56.Its
Middle N49, N50, P50, P51 play a part of electric capacity, and phase inverter I78, phase inverter I79 are latched for data.D is data input,
DOWN3 is filtering data output end.
Data input pin D connects PMOS P56, the grid of NMOS tube N55, the drain electrode connection NMOS tube N55's of PMOS P56
Source electrode, the source electrode of PMOS P56 connects power supply, the grounded drain of NMOS tube P55, the source electrode of NMOS tube N55 connect NMOS tube N52,
N53, N43, PMOS P54, P55, the grid of P44.
The source electrode of PMOS P55 connects power supply, and the drain electrode of PMOS P55 connects the source electrode of PMOS P54, the leakage of PMOS P54
Pole connects the source electrode of NMOS tube N52, and the drain electrode of NMOS tube N52 connects the source electrode of NMOS tube N53, the grounded drain of NMOS tube N53.
The source electrode of PMOS P51, drain electrode connect power supply respectively, and the source electrode of NMOS tube N50, grid are grounded respectively, PMOS
P51, the grid of NMOS tube N50 connect the source electrode of NMOS tube N52, the grid of NMOS tube N51 respectively.
The source electrode of PMOS P52 connects power supply, and the drain electrode of PMOS P52 connects the source electrode of PMOS P53, the leakage of PMOS P53
Pole connects the source electrode of NMOS tube N54, and the drain electrode of NMOS tube N54 connects the source electrode of NMOS tube N51, the grounded drain of NMOS tube N51.
The source electrode of PMOS P50, drain electrode connect power supply respectively, and the source electrode of NMOS tube N49, grid are grounded respectively, PMOS
P50, the grid of NMOS tube N49 connect the source electrode of NMOS tube N54, the grid of NMOS tube N47 respectively.
The source electrode of PMOS P49 connects power supply, and the drain electrode of PMOS P49 connects the source electrode of PMOS P48, the leakage of PMOS P48
Pole connects the source electrode of NMOS tube N47, and the drain electrode of NMOS tube N47 connects the source electrode of NMOS tube N48, the grounded drain of NMOS tube N48.
The source electrode of PMOS P46 connects power supply, and the drain electrode of PMOS P46 connects the source electrode of PMOS P47, the leakage of PMOS P47
Pole connects the source electrode of NMOS tube N46, and the drain electrode of NMOS tube N46 connects the source electrode of NMOS tube N45, the grounded drain of NMOS tube N45.
The source electrode of PMOS P44 connects power supply, and the drain electrode of PMOS P44 connects the source electrode of PMOS P45, the leakage of PMOS P45
Pole connects the source electrode of NMOS tube N44, and the drain electrode of NMOS tube N44 connects the source electrode of NMOS tube N43, the grounded drain of NMOS tube N43.
The input of phase inverter I78 connects the source electrode of NMOS tube N44, the output end of phase inverter I79, phase inverter I78 respectively
Output end, phase inverter I79 input be filtering wave by prolonging time module output end DOMN3.
As shown in fig. 6, principal and subordinate's level DICE latch modules include main module and from level module, main module and from level mould
Clear terminal RN is provided with block.
Main module includes：
Second tristate inverter：The source electrode of PMOS P18 connects power supply, and the drain electrode of PMOS P18 connects the source of PMOS P17
Pole, the drain electrode of PMOS P17 connects the source electrode of NMOS tube N17, and the drain electrode of NMOS tube N17 connects the source electrode of NMOS tube N18, NMOS tube
The grounded drain of N18.
3rd tristate inverter：The source electrode of NMOS tube N28 connects power supply, and the drain electrode of NMOS tube N28 connects the source of PMOS P29
Pole, the drain electrode of PMOS P29 connects the source electrode of NMOS tube N29, and the drain electrode of NMOS tube N29 connects the source electrode of NMOS tube N28, NMOS tube
The grounded drain of N28.
Main DICE units：The source electrode of PMOS P19 connects power supply, and the drain electrode of PMOS P19 connects the source electrode of PMOS P20,
The drain electrode of PMOS P20 connects the source electrode of NMOS tube N20, and the drain electrode of NMOS tube N20 connects the source electrode of NMOS tube N19, NMOS tube N19's
Grounded drain.
The source electrode of PMOS P36 connects power supply, and the drain electrode of PMOS P36 connects the source electrode of NMOS tube N36, the leakage of NMOS tube N36
Pole is grounded.
The source electrode of PMOS P38 connects power supply, and the drain electrode of PMOS P38 connects the source electrode of PMOS P39, the leakage of PMOS P39
Pole connects the source electrode of NMOS tube N37, and the drain electrode of NMOS tube N37 connects the source electrode of NMOS tube N38, the grounded drain of NMOS tube N38.
The source electrode of PMOS P25 connects power supply, and the drain electrode of PMOS P25 connects the source electrode of NMOS tube N25, the leakage of NMOS tube N25
Pole is grounded.
The grid of PMOS P19 connects the drain electrode of PMOS P25, the grid of NMOS tube N38；
The source electrode of NMOS tube N17 connects the grid of PMOS P36, the grid of NMOS tube N25, the source electrode of NMOS tube N20.
The grid of NMOS tube N19 connects the grid of PMOS P38, the source electrode of NMOS tube N36；The source electrode of NMOS tube N29 connects
The grid of NMOS tube N36, the source electrode of NMOS tube N37, the grid of PMOS P25.
Main module includes the first host node DOWN4, the second host node DOWN2, the 3rd host node DOWNM1, the 4th main section
Point UP3, four host nodes are single-particle sensitive nodes, four host nodes Logic adjacent successively, successively equivalent to the node in Fig. 2
a、b、c、d。
Main module includes four clear terminal RN, respectively by PMOS P59, P36 and the grid of NMOS tube N58, N59
Draw, specifically
The source electrode of PMOS P59 connects power supply, and drain electrode connects the drain electrode of PMOS P25.
The source electrode of PMOS P36 connects power supply, and drain electrode connects the grid of PMOS P38.
The source electrode of NMOS tube N58 connects the grid of NOMS pipes N38, and drain electrode connects the source electrode of NOMS pipes N25.
The source electrode of NMOS tube N59 connects the grid of NOMS pipes N19, and drain electrode connects the source electrode of NOMS pipes N36.
The effect of clear terminal RN is that, output zero setting, trigger has a fixed output when its benefit is the electricity on circuit
Signal, makes circuit be in a state for stabilization, and the trigger for being not added with clear terminal will be presented labile state after the power-up, unfavorable
In system work, this trigger is generally used for the system for not considering power-up state.
Include from level module：
4th tristate inverter：The source electrode of PMOS P21 connects power supply, and the drain electrode of PMOS P21 connects the source of PMOS P22
Pole, the drain electrode of PMOS P22 connects the source electrode of NMOS tube N22, and the drain electrode of NMOS tube N22 connects the source electrode of NMOS tube N21, NMOS tube
The grounded drain of N21.
5th tristate inverter：The source electrode of PMOS P34 connects power supply, and the drain electrode of PMOS P34 connects the source of PMOS P32
Pole, the drain electrode of PMOS P32 connects the source electrode of NMOS tube N32, and the drain electrode of NMOS tube N32 connects the source electrode of NMOS tube N34, NMOS tube
The grounded drain of N34.
From level DICE units：The source electrode of PMOS P24 connects power supply, and the drain electrode of PMOS P24 connects the source electrode of PMOS P23,
The drain electrode of PMOS P23 connects the source electrode of NMOS tube N23, and the drain electrode of NMOS tube N23 connects the source electrode of NMOS tube N24, NMOS tube N24's
Grounded drain.
The source electrode of PMOS P40 connects power supply, and the drain electrode of PMOS P40 connects the source electrode of NMOS tube N39, the leakage of NMOS tube N39
Pole is grounded.
The source electrode of PMOS P41 connects power supply, and the drain electrode of PMOS P41 connects the source electrode of PMOS P42, the leakage of PMOS P42
Pole connects the source electrode of NMOS tube N41, and the drain electrode of NMOS tube N41 connects the source electrode of NMOS tube N40, the grounded drain of NMOS tube N40.
The source electrode of PMOS P43 connects power supply, and the drain electrode of PMOS P43 connects the source electrode of NMOS tube N42, the leakage of NMOS tube N42
Pole is grounded.
The source electrode of NMOS tube N22 connects the grid of NMOS tube N42, the source electrode of NMOS tube N23, the grid of PMOS P40；NMOS
The source electrode of pipe N32 connects the grid of NMOS tube N39, the source electrode of NMOS tube N41, the grid of PMOS P43.
The drain electrode of PMOS P40 connects the grid of PMOS P41, the grid of NMOS tube N24.
First is provided with from level module from node Q1NN, second from node DOWN1, the 3rd from node UP1, the 4th from section
Point UP2, four from node be single-particle sensitive nodes, four from node successively Logic adjacent, successively equivalent to the node in Fig. 2
a、b、c、d。
Include four clear terminal RN from level module, respectively by PMOS P57, P58 and the grid of NMOS tube N56, N57
Draw, specifically：
The source electrode of PMOS P57 connects power supply, and drain electrode connects the drain electrode of PMOS P23.
The source electrode of PMOS P58 connects power supply, and drain electrode connects the drain electrode of PMOS P32.
The source electrode of NMOS tube N56 connects the drain electrode of NOMS pipes N24, grounded drain.
The source electrode of NMOS tube N57 connects the drain electrode of NOMS pipes N40, grounded drain.
The effect of clear terminal RN is that, output zero setting, trigger has a fixed output when its benefit is the electricity on circuit
Signal, makes circuit be in a state for stabilization, and the trigger for being not added with clear terminal is easy to labile state occur after the power-up, no
Beneficial to system work, this trigger is generally used for the system for not considering power-up state.
3rd host node DOWNM1 connects the grid of PMOS P34, the grid of NMOS tube N34, i.e. the 4th tristate inverter
Input.
First host node DOWNM4 connects the grid of PMOS P21, the grid of NMOS tube N21, i.e. the 5th tristate inverter
Input.
As shown in figure 8, output module：The grid of the input termination NMOS tube N24 of phase inverter I68, I69 is (i.e. from level signal
Output end Q1NN), the grid (i.e. from level signal output part UP1) of the input termination PMOS P24 of phase inverter I72, I73 is anti-phase
The output end of device I69, I73 is the input of the data output end connection phase inverter I70 of output module output end QN, phase inverter I68
End, the input of the output end connection phase inverter I71 of phase inverter I72, phase inverter I71, the output end of phase inverter I70 are output mould
Block output end Q, phase inverter is used to strengthen the driving force of output signal.
The d type flip flop with clear terminal of one embodiment of the invention uses the CMOS technology of 0.13um.Filtering wave by prolonging time module resists
The general principle of SET is that input is made up of two paths of signals, if a transient pulse signal is transmitted to input in the external world, by
Different in two paths of signals, the pulse cannot be passed in next stage circuit so that the output of circuit is remained in that correctly.Principal and subordinate's level
The general principle of the anti-SEU of DICE latch modules is that it is internal in the presence of 4 memory nodes for intercoupling, if due to certain
The one of memory node of reason there occurs upset, and remaining memory node will come the data correction of this mistake upset, make
The output for obtaining circuit is remained in that correctly.
The d type flip flop with clear terminal in any of the above-described embodiment, the first host node DOWN4, the 3rd host node DOWNM1
Identical (information of i.e. two node storages is identical), the second host node DOWN2, the 4th host node UP3 are identical.First from node
Q1NN, second are from node DOWN1, the 3rd from node UP1, the 4th from node UP2, and four adjacent from node successively sequential logic.
Second is identical from node UP2 from node DOWN1 and the 4th, and first is identical from node UP1 from node Q1NN and the 3rd.Output end Q
Storage state controlled by input D and clock CK.When input D has data transfer, if there is transient pulse to produce, due to section
Point A is different with the data of B, transient pulse cannot pass to filtering wave by prolonging time module output end DOWN3, it is to avoid transient pulse enters touches
In hair device.
In main module, if there is single-particle inversion, during negative pulse, the 4th host node in the first host node DOWN4 signals
Wrong data can be corrected and feed back to the first host node DOWN4 by UP3；During positive pulse, the second host node DOWN2 can be by mistake
Miss data correction and feed back to the first host node DOWN4, holding circuit output result is correct, and other nodes are also same original
Output end, when clear terminal RN signals are 0, is set to 0, trigger normal work when being 1 by reason.
The domain of the d type flip flop with clear terminal of any of the above-described embodiment includes protection band, and protection band includes PMOS
Protection band, NMOS tube protection band.PMOS protection band is constituted by P+ is active, and NMOS tube protection band is constituted by N+ is active, sensitive spot
Between there is protection band to isolate, protection bandwidth be design rule in active minimum widith 0.28um.Layout design rules are each
Technique processing producer formulates according to the concrete condition of oneself processing line, as long as using same technique, its layout design rule
It is then the same, is mainly in view of area for cutting using minimum widith, that is, serves the effect of anti-breech lock and make the face of domain
Product is unlikely to increase excessive, meets the requirement of integrated circuit miniaturization, reduces cost.
The circuit of the d type flip flop of anti-single particle effect is cmos circuit, and the intrinsic pnpn four-layer structures of cmos device are formed
One parasitic controllable silicon, under single particle effect, voltage drop on p traps resistance or resistance substrate may be such that the vertical of parasitism
To NPN or lateral PNP triode ON, positive current feedback is produced, ultimately result in two parasitic triodes and reach saturation, and maintain
Saturation state, produces the high current path from power supply to ground, causes circuit that breech lock occurs.Adding protection band can reduce parasitic crystalline substance
The gain of body pipe, and control to lead to the voltage of interior trap and substrate, parasitic transistor is unable to reach saturation, i.e., cannot produce circuit
Path, serves the effect of anti-breech lock, it helps reduce the SET pulse width in circuit.Additionally, being put device is carried out
When, the storage inside node of the same potential that staggers, it is to avoid had influence on by same incoming particle.
In circuit simulation, sensitive nodes are accessed by by double-exponential function current source, single-particle incidence can be simulated and made
Into transient effect.Voltage at sensitive spot will be reduced to below 0V, or raise to more than supply voltage, and this is a kind of worse
The single-particle inversion of situation collects charge model.Trigger adds pulse current source simulation single-particle in individual data memory node
The simulation waveform of incident (single-particle inversion threshold value LET=100MeVcm2/mg) is as shown in Figure 9.
Fig. 9 show the sound of one node of d type flip flop with clear terminal by single-particle bombardment of an embodiment of the present invention
Oscillogram is answered, abscissa is time shaft, and unit is ns, and ordinate is that voltage axis unit is V, and d type flip flop is given in figure two
Plant under input condition.Can be, it is evident that certain sensitive nodes there occurs upset after being bombarded by single-particle but dry from figure
Pulse is disturbed by being eliminated by the feedback of redundancy structure after about 1.1ns, storage state originally can be recovered without hair in time
It is raw to change.It is believed that the individual node of circuit has the ability of anti-SEU.
Above-described is only some embodiments of the present invention.For the person of ordinary skill of the art, not
On the premise of departing from the invention design, various modifications and improvements can be made, these belong to the protection domain of invention.
Claims (9)
1. it is a kind of d type flip flop with clear terminal, including clock module, filtering wave by prolonging time module, principal and subordinate's level DICE latch modules, defeated
Go out module, wherein
The filtering wave by prolonging time module includes the first phase inverter, filtering wave by prolonging time path, through path, the first tristate inverter；It is described
External data is divided into first via signal and second road signal by the first phase inverter, and the first via signal is logical through the filtering wave by prolonging time
Enter first tristate inverter behind road, it is anti-that the second road signal is directly entered first tri-state through the through path
Phase device；
Principal and subordinate's level DICE latch modules are according to the clock signal exported from the clock module, and filtered by the time delay
The external data signal that ripple module is received, corresponding data-signal is exported to data outputting module；
Principal and subordinate level DICE latch modules include main module and from level module, the main module and are set from level module
It is equipped with clear terminal.
2. the d type flip flop with clear terminal according to claim 1, wherein, the outside that the filtering wave by prolonging time module will be received
Data-signal is divided into first via signal and second road signal；The filtering wave by prolonging time module is carried out at filtering wave by prolonging time to first via signal
Reason, does not process to second road signal；When the first via signal processed through filtering wave by prolonging time and undressed second road signal phase
Meanwhile, filtering wave by prolonging time module output data；When different, filtering wave by prolonging time module not output data.
3. the d type flip flop with clear terminal according to claim 2, wherein
It is described to include first to fourth from node from level module, it is described from node be single-particle sensitive nodes, it is described from node according to
Secondary Logic adjacent；
The main module include first to fourth host node, the host node be single-particle sensitive nodes, the host node according to
Secondary Logic adjacent；
The host node and from node be physically spaced arrangement.
4. the d type flip flop with clear terminal according to claim 3, wherein, four clearings are provided with the main module
End, it is described that four clear terminals are provided with from level module.
5. the d type flip flop with clear terminal according to claim 4, also including protection band, the protection band includes PMOS
Protection band, NMOS tube protection band, the PMOS protection band are constituted by P+ is active, and the NMOS tube protection band is by the active structures of N+
Into being both provided with protection band between adjacent single-particle sensitive nodes.
6. according to any described d type flip flop with clear terminal of Claims 1 to 5, wherein, the filtering wave by prolonging time path includes anti-
Phase device unit and filter unit, the inverter module are made up of even number of inverters.
7. the d type flip flop with clear terminal according to claim 6, wherein, the number of the inverter module is variable.
8. the d type flip flop with clear terminal according to claim 5, wherein, the width of the protection band uses layout design
Active minimum widith in rule.
9. the d type flip flop with clear terminal according to claim 8, wherein, the clock module exports a pair of inversion signals.
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| CN106788340B (en) * | 2017-01-12 | 2020-03-24 | 深圳大学 | Synchronous set D trigger resistant to single event upset |
| CN106712743B (en) * | 2017-01-12 | 2020-03-20 | 深圳大学 | Synchronous reset D trigger resisting single event upset |
| CN106941345B (en) * | 2017-03-17 | 2020-03-10 | 中国电子科技集团公司第二十四研究所 | D trigger and asynchronous successive approximation type analog-to-digital converter |
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| CN102361442A (en) * | 2011-10-21 | 2012-02-22 | 中国人民解放军国防科学技术大学 | Single-event-upset resistant resettable D trigger |
| CN102361443A (en) * | 2011-10-21 | 2012-02-22 | 中国人民解放军国防科学技术大学 | Single-event-upset resistant resettable scan structure D trigger |
| CN102394595A (en) * | 2011-10-21 | 2012-03-28 | 中国人民解放军国防科学技术大学 | Settable and resettable D trigger resisting single event upset |
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| US8054099B2 (en) * | 2009-07-29 | 2011-11-08 | The Boeing Company | Method and apparatus for reducing radiation and cross-talk induced data errors |
| WO2013078439A2 (en) * | 2011-11-22 | 2013-05-30 | Silicon Space Technology Corporation | Memory circuit incorporating radiation hardened memory scrub engine |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102361442A (en) * | 2011-10-21 | 2012-02-22 | 中国人民解放军国防科学技术大学 | Single-event-upset resistant resettable D trigger |
| CN102361443A (en) * | 2011-10-21 | 2012-02-22 | 中国人民解放军国防科学技术大学 | Single-event-upset resistant resettable scan structure D trigger |
| CN102394595A (en) * | 2011-10-21 | 2012-03-28 | 中国人民解放军国防科学技术大学 | Settable and resettable D trigger resisting single event upset |
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