CN102331922B - 运算装置、高速缓存装置及其控制方法 - Google Patents

运算装置、高速缓存装置及其控制方法 Download PDF

Info

Publication number
CN102331922B
CN102331922B CN201110145879.5A CN201110145879A CN102331922B CN 102331922 B CN102331922 B CN 102331922B CN 201110145879 A CN201110145879 A CN 201110145879A CN 102331922 B CN102331922 B CN 102331922B
Authority
CN
China
Prior art keywords
data
node
waterline
cache
section point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201110145879.5A
Other languages
English (en)
Chinese (zh)
Other versions
CN102331922A (zh
Inventor
伊藤忠幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Publication of CN102331922A publication Critical patent/CN102331922A/zh
Application granted granted Critical
Publication of CN102331922B publication Critical patent/CN102331922B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/02—Comparing digital values
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
CN201110145879.5A 2010-06-07 2011-06-01 运算装置、高速缓存装置及其控制方法 Expired - Fee Related CN102331922B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010-130447 2010-06-07
JP2010130447A JP5650441B2 (ja) 2010-06-07 2010-06-07 演算装置、キャッシュ装置、その制御方法及びコンピュータプログラム

Publications (2)

Publication Number Publication Date
CN102331922A CN102331922A (zh) 2012-01-25
CN102331922B true CN102331922B (zh) 2015-07-15

Family

ID=44352182

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110145879.5A Expired - Fee Related CN102331922B (zh) 2010-06-07 2011-06-01 运算装置、高速缓存装置及其控制方法

Country Status (4)

Country Link
US (1) US8812783B2 (enExample)
EP (2) EP2437159B1 (enExample)
JP (1) JP5650441B2 (enExample)
CN (1) CN102331922B (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8862702B2 (en) * 2012-07-18 2014-10-14 Accedian Networks Inc. Systems and methods of installing and operating devices without explicit network addresses
JP2015013429A (ja) * 2013-07-05 2015-01-22 キヤノン株式会社 画像処理装置及びその制御方法、並びにプログラム
CN107016008B (zh) * 2016-06-06 2020-06-09 阿里巴巴集团控股有限公司 信息处理方法和装置及动态信息的显示方法和装置
JP7278067B2 (ja) 2018-12-20 2023-05-19 キヤノン株式会社 データ処理装置及びその制御方法及びプログラム
US11442868B2 (en) 2019-05-24 2022-09-13 Texas Instruments Incorporated Aggressive write flush scheme for a victim cache
CN113672286B (zh) * 2021-07-30 2024-10-01 奇点微(上海)光电科技有限公司 一种流水线求值器、移动轨迹分析处理装置、方法及设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5572690A (en) * 1993-10-21 1996-11-05 Sun Microsystems, Inc. Cascaded multistage counterflow pipeline processor for carrying distinct data in two opposite directions
US5710905A (en) * 1995-12-21 1998-01-20 Cypress Semiconductor Corp. Cache controller for a non-symetric cache system
US5748539A (en) * 1997-03-05 1998-05-05 Sun Microsystems, Inc. Recursive multi-channel interface
CN1431599A (zh) * 2002-08-22 2003-07-23 智慧第一公司 标记位址堆叠及使用其的微处理器
US7546405B2 (en) * 2006-09-26 2009-06-09 Sony Computer Entertainment Inc. Methods and apparatus for dynamic grouping of requestors of resources in a multi-processor system

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5163142A (en) * 1988-10-28 1992-11-10 Hewlett-Packard Company Efficient cache write technique through deferred tag modification
JPH04178755A (ja) * 1990-11-13 1992-06-25 Toshiba Corp データ統合装置
US5353424A (en) * 1991-11-19 1994-10-04 Digital Equipment Corporation Fast tag compare and bank select in set associative cache
US5386527A (en) * 1991-12-27 1995-01-31 Texas Instruments Incorporated Method and system for high-speed virtual-to-physical address translation and cache tag matching
JPH05324468A (ja) * 1992-05-21 1993-12-07 Fujitsu Ltd 階層化キャッシュメモリ
JPH08263370A (ja) * 1995-03-27 1996-10-11 Toshiba Microelectron Corp キャッシュメモリシステム
US5905680A (en) * 1996-04-30 1999-05-18 Texas Instruments Incorporated Self-timed comparison circuits and systems
JPH10190744A (ja) * 1996-12-26 1998-07-21 Toshiba Corp 情報記憶装置
JP3623082B2 (ja) * 1997-09-26 2005-02-23 日本電信電話株式会社 連想メモリモジュール
US6825848B1 (en) * 1999-09-17 2004-11-30 S3 Graphics Co., Ltd. Synchronized two-level graphics processing cache
US6754772B2 (en) * 2001-11-15 2004-06-22 Micron Technology, Inc. Distributed cache
US7502887B2 (en) * 2003-11-12 2009-03-10 Panasonic Corporation N-way set associative cache memory and control method thereof
US7689772B2 (en) * 2006-05-04 2010-03-30 Intel Corporation Power-performance modulation in caches using a smart least recently used scheme
US7991960B2 (en) * 2006-10-11 2011-08-02 Arm Limited Adaptive comparison control in a data store
KR101077513B1 (ko) * 2007-06-20 2011-10-28 후지쯔 가부시끼가이샤 캐시 메모리 장치, 연산 처리 장치 및 그 제어 방법
US7913007B2 (en) * 2007-09-27 2011-03-22 The University Of North Carolina Systems, methods, and computer readable media for preemption in asynchronous systems using anti-tokens
JP2010102623A (ja) * 2008-10-27 2010-05-06 Nec Electronics Corp キャッシュメモリ及びその制御方法
US8539185B2 (en) * 2008-11-13 2013-09-17 International Business Machines Corporation Systolic networks for a spiral cache
US8271728B2 (en) * 2008-11-13 2012-09-18 International Business Machines Corporation Spiral cache power management, adaptive sizing and interface operations
US8051337B2 (en) * 2009-01-22 2011-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for fast cache-hit detection
US8452944B2 (en) * 2009-05-22 2013-05-28 Canon Kabushiki Kaisha Information processing apparatus and information processing method
JP5627330B2 (ja) * 2010-08-02 2014-11-19 キヤノン株式会社 情報処理装置、キャッシュ装置およびデータ処理方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5572690A (en) * 1993-10-21 1996-11-05 Sun Microsystems, Inc. Cascaded multistage counterflow pipeline processor for carrying distinct data in two opposite directions
US5710905A (en) * 1995-12-21 1998-01-20 Cypress Semiconductor Corp. Cache controller for a non-symetric cache system
US5748539A (en) * 1997-03-05 1998-05-05 Sun Microsystems, Inc. Recursive multi-channel interface
CN1431599A (zh) * 2002-08-22 2003-07-23 智慧第一公司 标记位址堆叠及使用其的微处理器
US7546405B2 (en) * 2006-09-26 2009-06-09 Sony Computer Entertainment Inc. Methods and apparatus for dynamic grouping of requestors of resources in a multi-processor system

Also Published As

Publication number Publication date
US8812783B2 (en) 2014-08-19
CN102331922A (zh) 2012-01-25
EP2437159A1 (en) 2012-04-04
US20110302373A1 (en) 2011-12-08
EP2393004A1 (en) 2011-12-07
JP5650441B2 (ja) 2015-01-07
EP2393004B1 (en) 2018-10-31
JP2011257880A (ja) 2011-12-22
EP2437159B1 (en) 2018-10-31

Similar Documents

Publication Publication Date Title
CN102331922B (zh) 运算装置、高速缓存装置及其控制方法
US8155134B2 (en) System-on-chip communication manager
US9110714B2 (en) Systems and methods for multi-tasking, resource sharing, and execution of computer instructions
US11831565B2 (en) Method for maintaining cache consistency during reordering
US7925804B2 (en) FIFO device and method of storing data in FIFO buffer
EP0947926A2 (en) System and method for multi-tasking, resource sharing, and execution of computer instructions
US20050210185A1 (en) System and method for organizing data transfers with memory hub memory modules
US20080065833A1 (en) Processing device, computer system, and mobile apparatus
US10282343B2 (en) Semiconductor device
CN102654827A (zh) 一种先进先出缓冲器及缓存数据的方法
US20080300992A1 (en) Interface Controller that has Flexible Configurability and Low Cost
US20120331187A1 (en) Bandwidth control for a direct memory access unit within a data processing system
US20030056073A1 (en) Queue management method and system for a shared memory switch
US11119924B2 (en) Interface device including ports and a cache memory, and control method thereof
CN101894012B (zh) 信息处理装置及信息处理方法
US20080298383A1 (en) Buffer Minimization in Interface Controller
US6189075B1 (en) Circuit for the management of memories in a multiple-user environment with access request and priority
US10505704B1 (en) Data uploading to asynchronous circuitry using circular buffer control
US6578118B1 (en) Method and logic for storing and extracting in-band multicast port information stored along with the data in a single memory without memory read cycle overhead
KR100358178B1 (ko) 공유메모리 스위치에서의 멀티캐스팅 장치 및 그 방법
US12086638B2 (en) Topology of accelerators
US8645597B2 (en) Memory block reclaiming judging apparatus and memory block managing system
US6715021B1 (en) Out-of-band look-ahead arbitration method and/or architecture
JP2013196509A (ja) 情報処理装置及びその制御方法
US7475159B2 (en) High-speed scheduler

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20150715

Termination date: 20210601

CF01 Termination of patent right due to non-payment of annual fee