JP5650441B2 - 演算装置、キャッシュ装置、その制御方法及びコンピュータプログラム - Google Patents

演算装置、キャッシュ装置、その制御方法及びコンピュータプログラム Download PDF

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JP5650441B2
JP5650441B2 JP2010130447A JP2010130447A JP5650441B2 JP 5650441 B2 JP5650441 B2 JP 5650441B2 JP 2010130447 A JP2010130447 A JP 2010130447A JP 2010130447 A JP2010130447 A JP 2010130447A JP 5650441 B2 JP5650441 B2 JP 5650441B2
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data
cache
pipeline
data processing
node
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Japanese (ja)
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JP2011257880A (ja
JP2011257880A5 (enExample
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伊藤　忠幸
忠幸 伊藤
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Canon Inc
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Canon Inc
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Priority to JP2010130447A priority Critical patent/JP5650441B2/ja
Priority to EP11195127.3A priority patent/EP2437159B1/en
Priority to EP11164892.9A priority patent/EP2393004B1/en
Priority to US13/105,062 priority patent/US8812783B2/en
Priority to CN201110145879.5A priority patent/CN102331922B/zh
Publication of JP2011257880A publication Critical patent/JP2011257880A/ja
Publication of JP2011257880A5 publication Critical patent/JP2011257880A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/02—Comparing digital values
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
JP2010130447A 2010-06-07 2010-06-07 演算装置、キャッシュ装置、その制御方法及びコンピュータプログラム Active JP5650441B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2010130447A JP5650441B2 (ja) 2010-06-07 2010-06-07 演算装置、キャッシュ装置、その制御方法及びコンピュータプログラム
EP11195127.3A EP2437159B1 (en) 2010-06-07 2011-05-05 Apparatus for data comparison and control method thereof
EP11164892.9A EP2393004B1 (en) 2010-06-07 2011-05-05 Cache apparatus and control method thereof
US13/105,062 US8812783B2 (en) 2010-06-07 2011-05-11 Operation apparatus, cache apparatus, and control method thereof
CN201110145879.5A CN102331922B (zh) 2010-06-07 2011-06-01 运算装置、高速缓存装置及其控制方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010130447A JP5650441B2 (ja) 2010-06-07 2010-06-07 演算装置、キャッシュ装置、その制御方法及びコンピュータプログラム

Publications (3)

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JP2011257880A JP2011257880A (ja) 2011-12-22
JP2011257880A5 JP2011257880A5 (enExample) 2013-07-25
JP5650441B2 true JP5650441B2 (ja) 2015-01-07

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JP2010130447A Active JP5650441B2 (ja) 2010-06-07 2010-06-07 演算装置、キャッシュ装置、その制御方法及びコンピュータプログラム

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US (1) US8812783B2 (enExample)
EP (2) EP2437159B1 (enExample)
JP (1) JP5650441B2 (enExample)
CN (1) CN102331922B (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8862702B2 (en) * 2012-07-18 2014-10-14 Accedian Networks Inc. Systems and methods of installing and operating devices without explicit network addresses
JP2015013429A (ja) * 2013-07-05 2015-01-22 キヤノン株式会社 画像処理装置及びその制御方法、並びにプログラム
CN107016008B (zh) * 2016-06-06 2020-06-09 阿里巴巴集团控股有限公司 信息处理方法和装置及动态信息的显示方法和装置
JP7278067B2 (ja) 2018-12-20 2023-05-19 キヤノン株式会社 データ処理装置及びその制御方法及びプログラム
US11442868B2 (en) 2019-05-24 2022-09-13 Texas Instruments Incorporated Aggressive write flush scheme for a victim cache
CN113672286B (zh) * 2021-07-30 2024-10-01 奇点微(上海)光电科技有限公司 一种流水线求值器、移动轨迹分析处理装置、方法及设备

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US5353424A (en) * 1991-11-19 1994-10-04 Digital Equipment Corporation Fast tag compare and bank select in set associative cache
US5386527A (en) * 1991-12-27 1995-01-31 Texas Instruments Incorporated Method and system for high-speed virtual-to-physical address translation and cache tag matching
JPH05324468A (ja) * 1992-05-21 1993-12-07 Fujitsu Ltd 階層化キャッシュメモリ
DE69430352T2 (de) * 1993-10-21 2003-01-30 Sun Microsystems Inc., Mountain View Gegenflusspipeline
JPH08263370A (ja) * 1995-03-27 1996-10-11 Toshiba Microelectron Corp キャッシュメモリシステム
US5710905A (en) * 1995-12-21 1998-01-20 Cypress Semiconductor Corp. Cache controller for a non-symetric cache system
US5905680A (en) * 1996-04-30 1999-05-18 Texas Instruments Incorporated Self-timed comparison circuits and systems
JPH10190744A (ja) * 1996-12-26 1998-07-21 Toshiba Corp 情報記憶装置
US5748539A (en) * 1997-03-05 1998-05-05 Sun Microsystems, Inc. Recursive multi-channel interface
JP3623082B2 (ja) * 1997-09-26 2005-02-23 日本電信電話株式会社 連想メモリモジュール
US6825848B1 (en) * 1999-09-17 2004-11-30 S3 Graphics Co., Ltd. Synchronized two-level graphics processing cache
US6862670B2 (en) 2001-10-23 2005-03-01 Ip-First, Llc Tagged address stack and microprocessor using same
US6754772B2 (en) * 2001-11-15 2004-06-22 Micron Technology, Inc. Distributed cache
US7502887B2 (en) * 2003-11-12 2009-03-10 Panasonic Corporation N-way set associative cache memory and control method thereof
US7689772B2 (en) * 2006-05-04 2010-03-30 Intel Corporation Power-performance modulation in caches using a smart least recently used scheme
US7546405B2 (en) * 2006-09-26 2009-06-09 Sony Computer Entertainment Inc. Methods and apparatus for dynamic grouping of requestors of resources in a multi-processor system
US7991960B2 (en) * 2006-10-11 2011-08-02 Arm Limited Adaptive comparison control in a data store
KR101077513B1 (ko) * 2007-06-20 2011-10-28 후지쯔 가부시끼가이샤 캐시 메모리 장치, 연산 처리 장치 및 그 제어 방법
US7913007B2 (en) * 2007-09-27 2011-03-22 The University Of North Carolina Systems, methods, and computer readable media for preemption in asynchronous systems using anti-tokens
JP2010102623A (ja) * 2008-10-27 2010-05-06 Nec Electronics Corp キャッシュメモリ及びその制御方法
US8539185B2 (en) * 2008-11-13 2013-09-17 International Business Machines Corporation Systolic networks for a spiral cache
US8271728B2 (en) * 2008-11-13 2012-09-18 International Business Machines Corporation Spiral cache power management, adaptive sizing and interface operations
US8051337B2 (en) * 2009-01-22 2011-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for fast cache-hit detection
US8452944B2 (en) * 2009-05-22 2013-05-28 Canon Kabushiki Kaisha Information processing apparatus and information processing method
JP5627330B2 (ja) * 2010-08-02 2014-11-19 キヤノン株式会社 情報処理装置、キャッシュ装置およびデータ処理方法

Also Published As

Publication number Publication date
US8812783B2 (en) 2014-08-19
CN102331922A (zh) 2012-01-25
EP2437159A1 (en) 2012-04-04
US20110302373A1 (en) 2011-12-08
EP2393004A1 (en) 2011-12-07
EP2393004B1 (en) 2018-10-31
JP2011257880A (ja) 2011-12-22
EP2437159B1 (en) 2018-10-31
CN102331922B (zh) 2015-07-15

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