CN102306692A - Processing method of LED (light emitting diode) - Google Patents
Processing method of LED (light emitting diode) Download PDFInfo
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- CN102306692A CN102306692A CN201110262555A CN201110262555A CN102306692A CN 102306692 A CN102306692 A CN 102306692A CN 201110262555 A CN201110262555 A CN 201110262555A CN 201110262555 A CN201110262555 A CN 201110262555A CN 102306692 A CN102306692 A CN 102306692A
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Abstract
The invention provides a processing method of an LED (light emitting diode), relates to the field of LED processing and aims at solving the technical problem of relatively complex processing technology of the LED in the prior art. The method comprises the following steps: obtaining an epitaxial wafer; processing the epitaxial wafer, and generating a figure of a P electrode area and the figure of an N electrode area of an LED, an electric current barrier layer figure of the LED, and a transparent conducting layer figure of the LED respectively on the epitaxial wafer; carrying out protective layer yellow-light processing on the epitaxial wafer after treatment; and generating a bonding pad figure and a protective layer figure of the LED on the epitaxial wafer. According to the invention, the processing procedures of the LED can be reduced.
Description
Technical field
The present invention relates to LED processing procedure field, be meant the manufacturing method thereof of a kind of LED especially.
Background technology
The processing procedure of High Power LED LED is five road processing procedures at present, and manufacturing process is described below:
EPI wafer; (LED epitaxial wafer) → mesa gold-tinted; (definition LED platform) → ICP dry etching; (plasma dry) → Remove PR; (removal photoresistance) → SiO2 hard mask deposition; (silica deposit is done rigid barrier layer) → laser half cutting; (radium-shine cutting) → SWE; (sidewall etch) → Remove hard mask; (removing the rigid barrier layer of silicon dioxide) → CBL; (SiO2) deposition; (current barrier layer silica deposit) → CBL gold-tinted; (definition current barrier layer silicon dioxide gold-tinted figure) → CBL wet etching; (current barrier layer Wet-type etching) → Remove PR; (removing photoresistance) → ITO deposition; (transparency conducting layer deposition) → ITO gold-tinted; (definition electrically conducting transparent layer pattern) → ITO wet etching; (transparency conducting layer Wet-type etching) → Remove PR; (removal photoresistance) → RTP; (rapid thermal annealing) → NP gold-tinted; (definition electrode pattern) → metal deposition; (Pad); (metal electrode deposition) → liftoff; (peeling off does not need metal section and part) → Remove PR; (removal photoresistance) → PAD annealing; (electrode annealing) → Preservation deposition; (SiO2); (silicon dioxide layer of protection deposition) → Preservation gold-tinted; (definition protective layer figure) → SiO2 wet etching; (silicon dioxide layer of protection Wet-type etching) → Remove PR; (removal photoresistance).
Can find out that LED uses five road processing procedures at present, processing procedure is long man-hour.
Summary of the invention
The technical problem that the present invention will solve provides the manufacturing method thereof of a kind of LED, has reduced the processing procedure operation of LED, thereby has reduced processing procedure man-hour.
For solving the problems of the technologies described above, embodiments of the invention provide technical scheme following:
The manufacturing method thereof of a kind of LED comprises:
Obtain epitaxial wafer;
Said epitaxial wafer is handled, respectively the figure of the P polar region of generation LED and the figure of the N district utmost point, the current blocking layer pattern of LED, the electrically conducting transparent layer pattern of LED on said epitaxial wafer;
Said epitaxial wafer to after handling carries out protective layer gold-tinted processing procedure, on said epitaxial wafer, generates land pattern and the protective layer figure of LED.
The figure of figure and the N district utmost point of P polar region that on said epitaxial wafer, generates LED is for generating through the step of said epitaxial wafer being carried out platform gold-tinted processing procedure;
At the current blocking layer pattern that generates LED on the said epitaxial wafer for generating through the step of the said epitaxial wafer behind said platform gold-tinted processing procedure being carried out current barrier layer gold-tinted processing procedure;
At the electrically conducting transparent layer pattern that generates LED on the said epitaxial wafer for generating through the step of the said epitaxial wafer behind said current barrier layer gold-tinted processing procedure being carried out transparency conducting layer gold-tinted processing procedure.
The said step that said epitaxial wafer is carried out platform gold-tinted processing procedure comprises:
Said epitaxial wafer is carried out the platform gold-tinted handle, to define required etched zone;
Said epitaxial wafer to after handling through said platform gold-tinted carries out etching, etches into the n type gallium nitride layer of said epitaxial wafer, with the figure of the P utmost point of definition LED and the figure of the N utmost point;
Remove the photoresistance that applies when carrying out the processing of platform gold-tinted on the said epitaxial wafer.
The said step that said epitaxial wafer behind the platform gold-tinted processing procedure is carried out current barrier layer gold-tinted processing procedure comprises:
On deposition current barrier layer on the said epitaxial wafer of platform gold-tinted processing procedure;
Said epitaxial wafer to the deposition current barrier layer carries out the processing of current barrier layer gold-tinted, to define the current blocking layer pattern of LED;
Said epitaxial wafer to handling through the current barrier layer gold-tinted carries out the etching of current barrier layer, with etching not by the zone of photoresistance protection;
Remove the photoresistance that applies when carrying out the processing of current barrier layer gold-tinted on the said epitaxial wafer.
Said said epitaxial wafer behind the platform gold-tinted processing procedure is carried out before the step of current barrier layer gold-tinted processing procedure, said method also comprises: on the rigid barrier layer of deposition on the said epitaxial wafer of said platform gold-tinted processing procedure; After the said epitaxial wafer that deposits rigid barrier layer carried out hemisection, carry out sidewall etch again; Said epitaxial wafer after sidewall etch is removed the processing on rigid barrier layer;
Saidly be specially: deposition current barrier layer on the said epitaxial wafer of removing rigid barrier layer in step through deposition current barrier layer on the said epitaxial wafer of platform gold-tinted processing procedure.
The said step that said epitaxial wafer behind said current barrier layer gold-tinted processing procedure is carried out transparency conducting layer gold-tinted processing procedure comprises:
At deposit transparent conductive layer on the said epitaxial wafer of said current barrier layer gold-tinted processing procedure;
Said epitaxial wafer to the deposit transparent conductive layer carries out the processing of transparency conducting layer gold-tinted, to define the electrically conducting transparent layer pattern;
Said epitaxial wafer to handling through the transparency conducting layer gold-tinted carries out the etching of transparency conducting layer, with etching not by the zone of photoresistance protection;
Remove the photoresistance that applies when carrying out the processing of transparency conducting layer gold-tinted on the said epitaxial wafer.
After the step of the photoresistance that applies when carrying out the processing of transparency conducting layer gold-tinted on the said epitaxial wafer of said removal, said method also comprises:
Said epitaxial wafer to removing the photoresistance that applies when the transparency conducting layer gold-tinted is handled carries out the transparency conducting layer annealing in process.
Said said epitaxial wafer after handling is carried out protective layer gold-tinted processing procedure, on said epitaxial wafer, generates the land pattern of LED and the step of protective layer figure comprises:
On the said epitaxial wafer of said transparency conducting layer gold-tinted processing procedure, depositing protective layer;
Said epitaxial wafer to the deposition protective layer carries out the processing of protective layer gold-tinted, with definition protective layer figure;
Said epitaxial wafer to handling through the protective layer gold-tinted carries out etching, waits to define the protective layer of the position of pad with removal;
The said epitaxial wafer that carries out etch processes is carried out the pad evaporation metal to be handled;
Said epitaxial wafer to handling through the pad evaporation metal carries out lift-off processing;
Remove the photoresistance that applies when carrying out the processing of protective layer gold-tinted on the said epitaxial wafer.
After the step of the photoresistance that applies when carrying out the processing of protective layer gold-tinted on the said epitaxial wafer of said removal, said method also comprises:
Said epitaxial wafer to removing the photoresistance that applies when the protective layer gold-tinted is handled carries out the pad alloy treatment.
Embodiments of the invention have following beneficial effect:
In the such scheme, the land pattern of LED handle to be generated by gold-tinted with the protective layer figure, therefore, has reduced the processing procedure operation of LED, thereby has reduced processing procedure man-hour.
Description of drawings
Fig. 1 is the schematic flow sheet of an embodiment of the manufacturing method thereof of a kind of LED of the present invention;
Fig. 2 is the schematic flow sheet of another embodiment of the manufacturing method thereof of a kind of LED of the present invention;
Fig. 3-1 is the structural representation of the epitaxial wafer of manufacturing method thereof when each flow process of the described LED of Fig. 2 to 3-19.
Embodiment
For technical problem, technical scheme and advantage that embodiments of the invention will be solved is clearer, will combine accompanying drawing and specific embodiment to be described in detail below.
Among the application, the principle of gold-tinted processing procedure is: through the photosensitive material (being called photoresist or photoresistance again) to being coated in substrate, the part that after exposure, development, stays shields to bottom, carries out etching and the nonvolatil figure of final acquisition then.
As shown in Figure 1, the embodiment for the manufacturing method thereof of LED of the present invention (Light Emitting Diode, light-emitting diode) comprises:
Wherein, the figure of figure and the N district utmost point of P polar region that on said epitaxial wafer, generates LED is for generating through the step of said epitaxial wafer being carried out platform gold-tinted processing procedure;
Current barrier layer (CBL, the Current blocking layer) figure that on said epitaxial wafer, generates LED is for generating through the step of the said epitaxial wafer behind said platform gold-tinted processing procedure being carried out current barrier layer gold-tinted processing procedure;
Transparency conducting layer (TCL, the Transparent Conducting Layer) figure that on said epitaxial wafer, generates LED is for generating through the step of the said epitaxial wafer behind said current barrier layer gold-tinted processing procedure being carried out transparency conducting layer gold-tinted processing procedure.
As shown in Figure 2, be another embodiment of the manufacturing method thereof of LED of the present invention.Fig. 3-1 is the structural representation of the epitaxial wafer of manufacturing method thereof when each handling process of the described LED of Fig. 2 to 3-19.Specifically describe embodiments of the invention below in conjunction with Fig. 2,3-1 to 3-19.
Said method comprises:
Wherein, step 22 comprises:
Step 221 shown in Fig. 3-2, is carried out the platform gold-tinted to said epitaxial wafer and is handled, to define required etched zone (no PR region covered);
Step 222 shown in Fig. 3-3, is carried out etching to the said epitaxial wafer after handling through said platform gold-tinted, etches into n type gallium nitride (N-GaN) layer of said epitaxial wafer, with the figure of the P utmost point of definition LED and the figure of the N utmost point; This step can for, carry out ICP dry etching (manifold type electricity slurry ion etching machine dry ecthing).
Step 223 shown in Fig. 3-4, is removed the photoresistance PR 35 that applies when carrying out the processing of platform gold-tinted on the said epitaxial wafer.
Optional, before the step 23, said method also comprises:
Step 22A is shown in Fig. 3-5, on the rigid barrier layer 36 of deposition on the said epitaxial wafer of said platform gold-tinted processing procedure; That is to say, use SiO2 to deposit rigid barrier layer (SiO2 hard mask deposition).
Step 22B, shown in Fig. 3-6, the said epitaxial wafer that deposits rigid barrier layer carried out hemisection after, carry out sidewall etch again; Specifically can for: use radium-shine cutting machine to carry out carrying out sidewall etch (laser half cutting SWE), not shown sidewall etch effect after the hemisection.
Step 22C shown in Fig. 3-7, removes the processing on rigid barrier layer to the said epitaxial wafer after sidewall etch.
Accordingly, step 23 comprises:
Step 231, shown in Fig. 3-8, deposition current barrier layer 37 on the said epitaxial wafer of removing rigid barrier layer.That is to say deposition current barrier layer (CBL SiO2 deposition).
Step 232 shown in Fig. 3-9, is carried out the current barrier layer gold-tinted to the said epitaxial wafer on deposition current barrier layer and is handled, to define the current blocking layer pattern of LED;
Step 233 shown in Fig. 3-10, is carried out the etching of current barrier layer to the said epitaxial wafer of handling through the current barrier layer gold-tinted, with etching not by the zone of photoresistance protection; This step can for, carry out current barrier layer wet etching CBL SiO2 wet etching).
Step 234 shown in Fig. 3-11, is removed the photoresistance 38 (Remove PR) that applies when carrying out the processing of current barrier layer gold-tinted on the said epitaxial wafer.
Wherein, step 22A-step 22C is optional, if execution in step 22A-step 22C not, then corresponding, step 231 is: on deposition current barrier layer on the said epitaxial wafer of platform gold-tinted processing procedure; Step 232-step 234 is not given unnecessary details with above-mentioned similar here.
Wherein, step 24 comprises:
Step 241 is shown in Fig. 3-12, at deposition (deposition) transparency conducting layer 39 on the said epitaxial wafer of said current barrier layer gold-tinted processing procedure;
Step 242 shown in Fig. 3-13, is carried out the transparency conducting layer gold-tinted to the said epitaxial wafer of deposit transparent conductive layer and is handled, to define the electrically conducting transparent layer pattern;
Step 243 shown in Fig. 3-14, is carried out the etching of transparency conducting layer to the said epitaxial wafer of handling through the transparency conducting layer gold-tinted, not by the zone of photoresistance protection, can carry out wet etching (wet etching) with etching;
Step 244 shown in Fig. 3-15, is removed the photoresistance 41 that applies when carrying out the processing of transparency conducting layer gold-tinted on the said epitaxial wafer.
Optional, after the step 244, said method also comprises:
Step 245 is carried out transparency conducting layer annealing in process (RTP) to the said epitaxial wafer of removing the photoresistance that applies when the transparency conducting layer gold-tinted is handled.
Wherein, transparency conducting layer can be made up of indium tin oxide (ITO, Indium Tin Oxides).
Step 251 is shown in Fig. 3-16, at deposition protective layer 43 (Preservation Deposition) on the said epitaxial wafer of said transparency conducting layer gold-tinted processing procedure; Can use SiO2; Its Reflect index (reflectivity) is 1.46, takes out efficient to increase light.
Step 252 shown in Fig. 3-17, is carried out protective layer (preservation) gold-tinted to the said epitaxial wafer that deposits protective layer and is handled, with definition protective layer figure;
Step 253 is carried out etching to the said epitaxial wafer of handling through the protective layer gold-tinted, waits to define the protective layer of the position of pad with removal; Can be buffer silicon oxide (BOE, Buffer Oxide Etcher) wet etching, wait to define the deposition protective layer of the position of pad Pad 45 with removal; That is to say, define figure with the mode of wet etching.
Step 254 shown in Fig. 3-18, is carried out the pad evaporation metal to the said epitaxial wafer that carries out etch processes and is handled;
Step 255 is peeled off (lift off) to the said epitaxial wafer of handling through the pad evaporation metal and is handled;
Step 256 shown in Fig. 3-19, is removed the photoresistance 42 that applies when carrying out the processing of protective layer gold-tinted on the said epitaxial wafer, promptly accomplishes LED Chip chip.
Optional, after the step 256, said method also comprises:
Step 257 is carried out pad (PAD) alloy treatment to the said epitaxial wafer of removing the photoresistance that applies when the protective layer gold-tinted is handled.
In the prior art, the processing procedure time of LED is longer, needs five road processing procedure operations.And the negative photoresistance that the arts demand price of NP gold-tinted is expensive carries out pad layer and peels off (Pad layer lift off).
Among the present invention, after the change of the processing flow of LED, the gold-tinted road is reduced to four roads by five roads, and NP gold-tinted of the prior art and preservation gold-tinted are merged operation, and the twice gold-tinted is merged into together.
Processing flow of the present invention comprises: EPI wafer; (LED epitaxial wafer) → mesa gold-tinted; (definition LED platform) → ICP dry etching; (plasma dry) → Remove PR; (removal photoresistance) → SiO2 hard mask deposition; (silica deposit is done rigid barrier layer) → laser half cutting; (radium-shine cutting) → SWE; (sidewall etch) → Remove hard mask; (removing the rigid barrier layer of silicon dioxide) → CBL; (SiO2) deposition; (current barrier layer silica deposit) → CBL gold-tinted; (definition current barrier layer silicon dioxide gold-tinted figure) → CBL wet etching; (current barrier layer Wet-type etching) → Remove PR; (removing photoresistance) → ITO deposition; (transparency conducting layer deposition) → ITO gold-tinted; (definition electrically conducting transparent layer pattern) → ITO wet etching; (transparency conducting layer Wet-type etching) → Remove PR; (removal photoresistance) → RTP; (rapid thermal annealing) → Preservation deposition; (silicon dioxide layer of protection deposition) → Preservation gold-tinted; (definition preservation figure) → SiO2 ICP dry etching to the gold-tinted chamber; (mode of wet etching is eaten up the position that will define Pad) → metal deposition; (Pad evaporation metal) → lift off; (peeling off unwanted metal section and part) → Remove PR; (removing photoresistance) → Pad annealing; (PAD alloy).
In the above-mentioned flow process, the Preservation gold-tinted can use positive photoresistance, also can use negative photoresistance, uses the cost of positive photoresistance lower.
The present invention can bring following beneficial effect: carry out processing flow improvement, reduce processing procedure road number, thereby reduce processing procedure man-hour; In addition, need not use the expensive negative photoresistance that uses when carrying out the processing of NP gold-tinted, reduce production cost.
The above is a preferred implementation of the present invention; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from principle according to the invention; Can also make some improvement and retouching, these improvement and retouching also should be regarded as protection scope of the present invention.
Claims (9)
1. the manufacturing method thereof of a LED is characterized in that, comprising:
Obtain epitaxial wafer;
Said epitaxial wafer is handled, respectively the figure of the P polar region of generation LED and the figure of N polar region, the current blocking layer pattern of LED, the electrically conducting transparent layer pattern of LED on said epitaxial wafer;
Said epitaxial wafer to after handling carries out protective layer gold-tinted processing procedure, on said epitaxial wafer, generates land pattern and the protective layer figure of LED.
2. the manufacturing method thereof of LED according to claim 1 is characterized in that,
The figure of figure and N polar region of P polar region that on said epitaxial wafer, generates LED is for generating through the step of said epitaxial wafer being carried out platform gold-tinted processing procedure;
At the current blocking layer pattern that generates LED on the said epitaxial wafer for generating through the step of the said epitaxial wafer behind said platform gold-tinted processing procedure being carried out current barrier layer gold-tinted processing procedure;
At the electrically conducting transparent layer pattern that generates LED on the said epitaxial wafer for generating through the step of the said epitaxial wafer behind said current barrier layer gold-tinted processing procedure being carried out transparency conducting layer gold-tinted processing procedure.
3. the manufacturing method thereof of LED according to claim 2 is characterized in that, the said step that said epitaxial wafer is carried out platform gold-tinted processing procedure comprises:
Said epitaxial wafer is carried out the platform gold-tinted handle, to define required etched zone;
Said epitaxial wafer to after handling through said platform gold-tinted carries out etching, etches into the n type gallium nitride layer of said epitaxial wafer, with the figure of the P polar region of definition LED and the figure of N polar region;
Remove the photoresistance that applies when carrying out the processing of platform gold-tinted on the said epitaxial wafer.
4. the manufacturing method thereof of LED according to claim 2 is characterized in that, the said step that said epitaxial wafer behind the platform gold-tinted processing procedure is carried out current barrier layer gold-tinted processing procedure comprises:
On deposition current barrier layer on the said epitaxial wafer of platform gold-tinted processing procedure;
Said epitaxial wafer to the deposition current barrier layer carries out the processing of current barrier layer gold-tinted, to define the current blocking layer pattern of LED;
Said epitaxial wafer to handling through the current barrier layer gold-tinted carries out the etching of current barrier layer, with etching not by the zone of photoresistance protection;
Remove the photoresistance that applies when carrying out the processing of current barrier layer gold-tinted on the said epitaxial wafer.
5. the manufacturing method thereof of LED according to claim 4 is characterized in that,
Said said epitaxial wafer behind the platform gold-tinted processing procedure is carried out before the step of current barrier layer gold-tinted processing procedure, said method also comprises: on the rigid barrier layer of deposition on the said epitaxial wafer of said platform gold-tinted processing procedure; After the said epitaxial wafer that deposits rigid barrier layer carried out hemisection, carry out sidewall etch again; Said epitaxial wafer after sidewall etch is removed the processing on rigid barrier layer;
Saidly be specially: deposition current barrier layer on the said epitaxial wafer of removing rigid barrier layer in step through deposition current barrier layer on the said epitaxial wafer of platform gold-tinted processing procedure.
6. the manufacturing method thereof of LED according to claim 2 is characterized in that, the said step that said epitaxial wafer behind said current barrier layer gold-tinted processing procedure is carried out transparency conducting layer gold-tinted processing procedure comprises:
At deposit transparent conductive layer on the said epitaxial wafer of said current barrier layer gold-tinted processing procedure;
Said epitaxial wafer to the deposit transparent conductive layer carries out the processing of transparency conducting layer gold-tinted, to define the electrically conducting transparent layer pattern;
Said epitaxial wafer to handling through the transparency conducting layer gold-tinted carries out the etching of transparency conducting layer, with etching not by the zone of photoresistance protection;
Remove the photoresistance that applies when carrying out the processing of transparency conducting layer gold-tinted on the said epitaxial wafer.
7. the manufacturing method thereof of LED according to claim 6 is characterized in that, after the step of the photoresistance that applies when carrying out the processing of transparency conducting layer gold-tinted on the said epitaxial wafer of said removal, said method also comprises:
Said epitaxial wafer to removing the photoresistance that applies when the transparency conducting layer gold-tinted is handled carries out the transparency conducting layer annealing in process.
8. the manufacturing method thereof of LED according to claim 2 is characterized in that, said said epitaxial wafer after handling is carried out protective layer gold-tinted processing procedure, on said epitaxial wafer, generates the land pattern of LED and the step of protective layer figure comprises:
On the said epitaxial wafer of said transparency conducting layer gold-tinted processing procedure, depositing protective layer;
Said epitaxial wafer to the deposition protective layer carries out the processing of protective layer gold-tinted, with definition protective layer figure;
Said epitaxial wafer to handling through the protective layer gold-tinted carries out etching, waits to define the protective layer of the position of pad with removal;
The said epitaxial wafer that carries out etch processes is carried out the pad evaporation metal to be handled;
Said epitaxial wafer to handling through the pad evaporation metal carries out lift-off processing;
Remove the photoresistance that applies when carrying out the processing of protective layer gold-tinted on the said epitaxial wafer.
9. the manufacturing method thereof of LED according to claim 8 is characterized in that, after the step of the photoresistance that applies when carrying out the processing of protective layer gold-tinted on the said epitaxial wafer of said removal, said method also comprises:
Said epitaxial wafer to removing the photoresistance that applies when the protective layer gold-tinted is handled carries out the pad alloy treatment.
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| CN103713251A (en) * | 2014-01-03 | 2014-04-09 | 合肥彩虹蓝光科技有限公司 | Method for verifying relation between voltage of LED white light chip and ITO film |
| CN105428474A (en) * | 2015-12-10 | 2016-03-23 | 厦门乾照光电股份有限公司 | Simple manufacturing method of high-efficient light emitting diode chip |
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Application publication date: 20120104 |