CN102305912A - Low power consumption integrated circuit testing device with compressible data and method using same - Google Patents
Low power consumption integrated circuit testing device with compressible data and method using same Download PDFInfo
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
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Abstract
The invention discloses a low power consumption integrated circuit testing device with compressible data and a method using the same. The device comprises a scanning forest, an XOR gate network, an output selection circuit, a first control register and a second control register, wherein the scanning forest comprises a plurality of scanning input ends and a plurality of mutually connected scanning trigger groups; the scanning input ends are connected to all scanning triggers in the first scanning trigger group; all scanning triggers in each scanning trigger group are connected with the output ends of the scanning triggers in the previous scanning trigger group; the input end of each XOR gate in the XOR gate network is connected with the output ends of the scanning triggers in the last group of scanning trigger group; and the output selection circuit is connected with the XOR gate network. According to the low power consumption integrated circuit testing device, node hop in the circuit can be reduced, energy consumption is lowered, and meanwhile compression of test response data can be achieved.
Description
Technical field
The present invention relates to the digital integrated circuit technical field of measurement and test, relate in particular to compressible low power consumption integrated circuit proving installation of a kind of data and method thereof.
Background technology
In the digital circuit test field, a lot of low-power consumption method of testings are suggested with data compression method, and still most low-power consumption method of testing can not be used for the compression verification data, and most data compression method can not be used for reducing power consumption.
Can reduce power consumption simultaneously and method of compressing data mainly contains:
(1) unknown bits (X position) assignment to test vector reduces power consumption and while packed data, and such method can only be sought a compromise with reducing in data compression in the power consumption.If it is many that power consumption reduces, the data compression effect is just not obvious, otherwise if data compression is more remarkable, power consumption reduces just not obvious.
(2) utilize the linear codec circuit that data are compressed, utilize the method for clock shielding to reduce power consumption simultaneously.Though this method can well reduce power consumption, the test data compression effects can be weakened.
Summary of the invention
The technical matters that (one) will solve
The technical matters that the present invention will solve is: compressible low power consumption integrated circuit proving installation of a kind of data and method thereof are provided, and it can reduce the saltus step of node in the circuit, reduces power consumption, can realize the compression of test response data simultaneously.
(2) technical scheme
For addressing the above problem, the invention provides the compressible low power consumption integrated circuit proving installation of a kind of data, comprising: scan forest, XOR gate network, output select circuit, first control register and second control register; Wherein,
Said scan forest; Comprise a plurality of scan input ends and a plurality of interconnective sweep trigger group, said scan input end connects all sweep triggers in first sweep trigger group, and all sweep triggers in each sweep trigger group connect the output terminal of going up sweep trigger in the one scan trigger group; The corresponding a plurality of scanning trees of said a plurality of scan input end; Each sweep trigger in the said scanning tree is connected with the output terminal of previous sweep trigger, forms scan chain;
The input end of each XOR gate in the said XOR gate network links to each other with last sweep trigger output terminal of organizing in sweep trigger group of said scan forest;
Said output select circuit connects said XOR gate network, is used to select the test response of needs observation in each clock period;
Said first control register is used to control the clock shielded signal;
Said second control register is used for said output select circuit is controlled.
Whether partly have according to sweep trigger and common follow-uply to divide into groups, form a plurality of sweep trigger groups with the principle forerunner unit at the combinational logic of circuit-under-test.
Preferably, said first control register comprises a plurality of register cells, and in each clock period, the value of one of them unit is 1, and the value of remaining element is 0.For example: in first cycle, first cell value is 1, and other unit is 0.Second cell value of second period is 1, and remaining element is 0.By that analogy.
Preferably, said second control register comprises a plurality of register cells, and in each clock period, the value of the scanning tree corresponding unit that need be observed is 1, and the value of remaining element is 0.
Preferably, said output select circuit comprises and door and or door.
Preferably, two scan chains connect same XOR gate.Two scan chain a
1, a
2..., a
nWith b
1, b
2..., b
nIf satisfy (a
1, b
1), (a
2, b
2) ..., (a
n, b
n) the right any a pair of combinational logic at circuit-under-test of these sweep triggers partly do not have common forerunner, two scan chain a then
1, a
2..., a
nWith b
1, b
2..., b
nCan be connected to same XOR gate.
A kind of method of utilizing aforementioned means that integrated circuit is tested may further comprise the steps:
A: utilize and select compression method that each test vector is encoded;
B: generate with the corresponding test response of each test vector and select vector;
C: each test vector is carried out the low-power consumption test.
Preferably, said steps A further comprises:
A1: with said test vector be divided into length equal n the section, to each subvector section with c=[log
2(n+1)+2] position coding, wherein 2 is control bit, all the other log
2(n+1) position is a data bit; N is the number of scanning tree, is natural number;
Wherein, said test vector is divided into when section of length less than n, earlier said test vector being divided into the section that length equals n, final stage length maybe be less than n, to a section of curtailment n, its length mended is n (arbitrarily using 0 or 1).C is a natural number.
A2: add up in each subvector section contained 0 number a and 1 number b;
A3: if a=1, making control bit is 01, and data bit is represented 0 position; If a=0, making control bit is 01, and data bit is log
2(n+1) individual 1;
If b=1, making control bit is 00, and data bit is represented 1 position; If b=0, making control bit is 00, and data bit is log
2(n+1) individual 1;
If a＞1 and b＞1, the length that said test vector is got is that the section of n is divided into the section of length less than c, and each section use the c+2 bit representation, and making control bit is 11, data bit be correspondence length less than c section value.
Preferably, said step B further comprises:
B1: can detected each fault f for test vector, output set list (f)=(O that fault can propagate into is found out in simulation
1..., O
m);
B2:, find out the error listing observe (O that it can observe for each output
i)={ f
1..., f
t;
B3: output set and failure collection are carried out initialization, and making output set is all outputs that can observe fault, and failure collection is all faults that can be detected;
B4: from said output set, select the output that can observe maximum faults, the deletion fault that this output observed from said failure collection, deletion should be exported from output set simultaneously;
B5: repeating step B4 is empty until failure collection;
B6:, generate test response and select vector with being changed to 1 with the output corresponding cells of deleting in second control register from output set.
Preferably, said step C further comprises:
C1: the test vector to behind the coding is decoded;
C2: the test vector that decoding obtains is imported in n the scanning tree;
C3：i＝1；
C4: i scanning tree caught test response;
C5: select vector to shift out the test response of the needs observation of each scanning tree according to test response, move into the corresponding test vector of i scanning tree simultaneously again;
C6:i increases by 1, if i＜=n repeats C4 and C5.Wherein, i is a natural number.
(3) beneficial effect
The present invention catches test response through in one-period, only making in the circuit part scanning element, thereby has reduced the saltus step of node in the circuit; Simultaneously, the present invention can be observed in a plurality of observation stations according to same fault, selects minimum observation station to observe all faults, adopts the selectivity output intent to realize the compression of test response.
Description of drawings
Fig. 1 is the structural representation of arrangement for testing integrated circuit described in the embodiment of the invention;
The method flow diagram of Fig. 2 for described in the embodiment of the invention integrated circuit being tested;
Fig. 3 is the structural representation of scanning tree in the scan forest described in the embodiment among the present invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment, specific embodiments of the invention describes in further detail.Following examples are used to explain the present invention, but are not used for limiting scope of the present invention.
As shown in Figure 1, the compressible low power consumption integrated circuit proving installation of data of the present invention comprises: scan forest, XOR gate network, output select circuit, first control register and second control register; Wherein,
Said scan forest; Comprise a plurality of scan input ends and a plurality of interconnective sweep trigger group, said scan input end connects all sweep triggers in first sweep trigger group, and all sweep triggers in each sweep trigger group connect the output terminal of going up sweep trigger in the one scan trigger group; The corresponding a plurality of scanning trees of said a plurality of scan input end; Each sweep trigger in the said scanning tree is connected with the output terminal of previous sweep trigger, forms scan chain;
Whether partly have according to sweep trigger and common follow-uply to divide into groups, form a plurality of sweep trigger groups with the principle forerunner unit at the combinational logic of circuit-under-test.
The input end of each XOR gate in the said XOR gate network links to each other with last sweep trigger output terminal of organizing in sweep trigger group of said scan forest; Each trigger of circuit being added the multiplex adapter of an alternative constitute a scanning element, is a sweep trigger.The output of two input difference CC built-up sections of multiplex adapter and the output of previous trigger.All like this scanning elements can connect into the shape of a chain, become scan chain.Two scan chain a
1, a
2..., a
nWith b
1, b
2..., b
nIf satisfy (a
1, b
1), (a
2, b
2) ..., (a
n, b
n) the right any a pair of combinational logic at circuit-under-test of these sweep triggers partly do not have common forerunner, two scan chain a then
1, a
2..., a
nWith b
1, b
2..., b
nCan be connected to same XOR gate.
Said output select circuit connects said XOR gate network, is used to select the test response of needs observation in each clock period; Said output select circuit comprises and door and or door.
Said first control register is used to control the clock shielded signal; Said first control register comprises a plurality of register cells, and in each clock period, the value of one of them unit is 1, and the value of remaining element is 0.For example: in first cycle, first cell value is 1, and other unit is 0.Second cell value of second period is 1, and remaining element is 0.By that analogy.
Said second control register is used for said output select circuit is controlled.Said second control register comprises a plurality of register cells, and in each clock period, the value of the scanning tree corresponding unit that need be observed is 1, and the value of remaining element is 0.
The formation of scanning tree: establishing circuit has n scan input end, and the sweep trigger group that constructs has g.If g≤n then chooses out g wantonly from n scan input end, each scan input end connects whole sweep triggers of a sweep trigger group, and the structure of scan forest is promptly accomplished.If g＞n, then optional n group is connected to respectively on each scan input end, and each scan input end only connects whole sweep triggers of a sweep trigger group.Construct the ground floor of scan forest like this.From remaining (g-n) individual sweep trigger group, select n sweep trigger group again, the man-to-man output terminal with the sweep trigger in certain group of ground floor of each sweep trigger during each is organized connects, thereby constructs the second layer of scan forest.Like Fig. 3, certain scan input end SI
iThe whole sweep trigger F that connect certain sweep trigger group
1,1, F
1,2..., F
1, f, then the whole sweep trigger F in the next sweep trigger group
2,1, F
2,2..., F
2, fBe connected to one group sweep trigger F successively one by one
1,1, F
1,2..., F
1, fOutput terminal.Repeat said process, the sweep trigger in all sweep trigger groups all is connected to the output terminal of the sweep trigger in other the sweep trigger group.In Fig. 3, scan forest is by n bar scanning tree TC
1..., TC
i..., TC
nForm.
As shown in Figure 2, the method for utilizing aforementioned means that integrated circuit is tested according to the invention may further comprise the steps:
A: utilize and select compression method that each test vector is encoded;
This step further may further comprise the steps:
A1: with said test vector be divided into length equal n the section, to each subvector section with c=[log
2(n+1)+2] position coding, wherein 2 is control bit, all the other log
2(n+1) position is a data bit; N is the number of scanning tree, is natural number;
A2: add up in each subvector section contained 0 number a and 1 number b;
A3: if a=1, making control bit is 01, and data bit is represented 0 position; If a=0, making control bit is 01, and data bit is log
2(n+1) individual 1;
If b=1, making control bit is 00, and data bit is represented 1 position; If b=0, making control bit is 00, and data bit is log
2(n+1) individual 1;
If a＞1 and b＞1, the length that said test vector is got is that the section of n is divided into the section of length less than c, and each section use the c+2 bit representation, and making control bit is 11, data bit be correspondence length less than c section value.
B: generate with the corresponding test response of each test vector and select vector;
This step further may further comprise the steps:
B1: can detected each fault f for test vector, output set list (f)=(O that fault can propagate into is found out in simulation
1..., O
m);
B2:, find out the error listing observe (O that it can observe for each output
i)={ f
1..., f
t;
B3: output set and failure collection are carried out initialization, and making output set is all outputs that can observe fault, and failure collection is all faults that can be detected;
B4: from said output set, select the output that can observe maximum faults, the deletion fault that this output observed from said failure collection, deletion should be exported from output set simultaneously;
B5: repeating step B4 is empty until failure collection;
B6:, generate test response and select vector with being changed to 1 with the output corresponding cells of deleting in second control register from output set.
C: each test vector is carried out the low-power consumption test.
This step further may further comprise the steps:
C1: the test vector to behind the coding is decoded;
C2: the test vector that decoding obtains is imported in n the scanning tree;
C3：i＝1；
C4: i scanning tree caught test response;
C5: select vector to shift out the test response of the needs observation of each scanning tree according to test response, move into the corresponding test vector of i scanning tree simultaneously again;
C6:i increases by 1, if i＜=n repeats C4 and C5.Wherein, i is a natural number.
The present invention relates to the design for Measurability of integrated circuit, design for Measurability is meant for ease test, in the process of circuit design, carries out testing for ease outside some functions and the design carried out.In test, this part circuit is Be Controlled and observation more easily, is used for reducing testing cost.
The present invention relates to a kind of device and method that after Chip Packaging, chip quality is detected.Owing to can't directly visit the internal circuit of chip after the Chip Packaging, the method that therefore test of chip is adopted is the input end built-in test vector at chip, and collects test response at chip output.Real income test response and the deserved test response of non-fault circuit are compared, thereby judge that chip circuit has non-fault.
Test vector: test vector is meant one group of logical value inserting internal circuit through the chip input end.Can contain in the test vector and confirm to confirm the position such as ' 1 ' in test vector " 10xxxx " and ' 0 ' expression in position and uncertain position, the uncertain position of ' x ' expression.
Test vector coding: contain 0,1 and three kinds of states of x in the test vector.The state that can represent vector with less information.Such as vector is 00000000, can represent this vector with a numeral 8 and state 0.
Test vector decode: according to coding theory, the design solutions decoding circuit makes the vector behind the coding be reduced to the process of original vector.
Fault model is to be the needs that study a question, with the physical imperfection in the actual chips abstract be logical fault models.Fault model commonly used has single stuck-at fault and delay fault.The described physical imperfection of single stuck-at fault is that the output valve of a certain signal line is fixed as logical one or 0 in the circuit, is designated as s-a-1 and s-a-0 respectively.The described physical imperfection of delay fault is, the hopping edge paths of the signal value of certain node of circuit propagates into output, and this delay has surpassed given restriction, observes wrong value at output terminal.
Test response is caught: the output of combination of circuits logic gets into the process of trigger through clock signal.
Testing power consumption: the power consumption of circuit is owing to the saltus step in the adjacent clock period of node in the circuit causes.The objective of the invention is in test process, to realize low-power consumption, the saltus step in the adjacent periods of circuit is reduced.
Make up follow-up: in circuit structure, the output signal line of composite door is that the combination of input signal cable of this composite door is follow-up.Making up follow-up relation can iteration.
The combination forerunner: in circuit structure, the input signal cable of composite door is the combination forerunner of the output signal line of this composite door.Combination forerunner's relation can iteration.
Common combination forerunner: close follow-up identical with mutual group.
Adopted experiment of the present invention: experiment porch is Dell precision 690 workstations.Provided the experimental result that the present invention is applied to ISCAS89 and IWLS2005 circuit in the table 1; FFs representes the number of trigger in the table; FC representes fault coverage, and vec1 representes the test vector number before the dynamic compression, and vec2 representes the test vector number after the dynamic compression; TA representes the ratio that test duration and single scan chain reduce, TA
1The ratio that the expression test duration reduces than multi-scanning chain; AP representes average power consumption, and PP representes peak power, and CP representes to catch power consumption; Reg representes the length of control register 1; Group representes the group number that is divided into according to the scan forest principle, and size representes the size of each group, and SI representes to scan the number of input.
By finding out in the table 1, adopt the device and method described in the present invention, will reduce largely and catch power consumption and move in and out power consumption.
In the table 2, the scan forest method of compression scheme is not used in " no SE " expression.Bits representes vectorial figure place in the table, and area representes area overhead.R1 representes the vectorial figure place of scan forest and the ratio of original vector figure place; R4 representes the vectorial figure place of this method and the ratio of original vector figure place; TRR representes the test response figure place of scan forest and the ratio of original test response figure place, and TRR1 representes the test response figure place of this method and the ratio of original vector test response figure place.Adopt the present invention can lower amount of test data very effectively.
Table 1
| circuit | FFs | FC | vec1 | vec2 | TA | TA 1 | AP | PP | CP | reg | group | size | SI |
| s9234 | 228 | 93.27 | 380 | 166 | 84.12 | -305.11 | 88.24 | 82.37 | 82.38 | 6 | 90 | 3 | 16 |
| s13207 | 669 | 98.37 | 340 | 243 | 92.72 | -310.74 | 91.29 | 89.34 | 86.59 | 8 | 186 | 4 | 32 |
| s15850 | 597 | 96.58 | 395 | 132 | 93.31 | -103.15 | 89.79 | 84.54 | 82.45 | 6 | 101 | 6 | 16 |
| s35932 | 1728 | 89.82 | 45 | 27 | 99.05 | -10.42 | 93.78 | 90.32 | 91.75 | 10 | 11 | 158 | 1 |
| s38417 | 1636 | 99.50 | 749 | 188 | 98.41 | 42.69 | 91.89 | 85.60 | 85.62 | 6 | 84 | 20 | 16 |
| s38584 | 1452 | 96.96 | 664 | 196 | 98.12 | 22.35 | 91.75 | 84.45 | 84.77 | 6 | 96 | 16 | 16 |
| b17 | 1415 | 94.10 | 3254 | 577 | 90.18 | -309.05 | 92.76 | 90.34 | 90.82 | 10 | 309 | 5 | 32 |
| b18 | 3320 | 99.36 | 4256 | 726 | 94.35 | -104.73 | 93.28 | 92.49 | 92.39 | 10 | 370 | 10 | 32 |
| b19 | 6642 | 98.37 | 18750 | 3287 | 97.77 | 13.33 | 92.88 | 90.84 | 91.52 | 10 | 250 | 28 | 32 |
| wb_conmax | 770 | 95.87 | 834 | 350 | 93.66 | -239.46 | 90.27 | 91.54 | 92.04 | 8 | 180 | 5 | 32 |
| usb_funct | 1746 | 99.31 | 1161 | 430 | 97.56 | 3.63 | 95.53 | 91.85 | 91.84 | 8 | 105 | 17 | 16 |
| DMA | 2192 | 94.02 | 1721 | 414 | 96.12 | -106.73 | 90.77 | 91.35 | 91.01 | 8 | 274 | 8 | 32 |
| pci_bridge32 | 3360 | 99.83 | 1055 | 380 | 98.01 | 12.20 | 91.08 | 93.49 | 92.47 | 8 | 159 | 22 | 32 |
| des_perf | 8808 | 100 | 420 | 195 | 99.15 | 95.39 | 97.23 | 90.38 | 90.47 | 8 | 27 | 327 | 16 |
| ethernet | 10544 | 99.01 | 7054 | 1768 | 97.22 | -307.15 | 88.11 | 96.31 | 93.75 | 10 | 2109 | 5 | 64 |
| vga_lcd | 17079 | 99.06 | 8901 | 2007 | 99.45 | 58.44 | 90.08 | 96.35 | 93.39 | 8 | 427 | 40 | 32 |
Table 2
Above embodiment only is used to explain the present invention; And be not limitation of the present invention; The those of ordinary skill in relevant technologies field under the situation that does not break away from the spirit and scope of the present invention, can also be made various variations and modification; Therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (9)
1. the compressible low power consumption integrated circuit proving installation of data is characterized in that, comprising: scan forest, XOR gate network, output select circuit, first control register and second control register; Wherein,
Said scan forest; Comprise a plurality of scan input ends and a plurality of interconnective sweep trigger group, said scan input end connects all sweep triggers in first sweep trigger group, and all sweep triggers in each sweep trigger group connect the output terminal of going up sweep trigger in the one scan trigger group; The corresponding a plurality of scanning trees of said a plurality of scan input end; Each sweep trigger in the said scanning tree is connected with the output terminal of previous sweep trigger, forms scan chain;
The input end of each XOR gate in the said XOR gate network links to each other with last sweep trigger output terminal of organizing in sweep trigger group of said scan forest;
Said output select circuit connects said XOR gate network, is used to select the test response of needs observation in each clock period;
Said first control register is used to control the clock shielded signal;
Said second control register is used for said output select circuit is controlled.
2. the compressible low power consumption integrated circuit proving installation of data as claimed in claim 1 is characterized in that said first control register comprises a plurality of register cells, and in each clock period, the value of one of them unit is 1, and the value of remaining element is 0.
3. the compressible low power consumption integrated circuit proving installation of data as claimed in claim 1; It is characterized in that said second control register comprises a plurality of register cells, in each clock period; The value of the scanning tree corresponding unit that need be observed is 1, and the value of remaining element is 0.
4. the compressible low power consumption integrated circuit proving installation of data as claimed in claim 1 is characterized in that, said output select circuit comprises and door and or door.
5. the compressible low power consumption integrated circuit proving installation of data as claimed in claim 1 is characterized in that two scan chains connect same XOR gate.
6. one kind is utilized the method that each said device is tested integrated circuit among the claim 1-5, it is characterized in that, may further comprise the steps:
A: utilize and select compression method that each test vector is encoded;
B: generate with the corresponding test response of each test vector and select vector;
C: each test vector is carried out the low-power consumption test.
7. the method that integrated circuit is tested as claimed in claim 6 is characterized in that, said steps A further comprises:
A1: with said test vector be divided into length equal n the section, to each subvector section with c=[log
2(n+1)+2] position coding, wherein 2 is control bit, all the other log
2(n+1) position is a data bit;
A2: add up in each subvector section contained 0 number a and 1 number b;
A3: if a=1, making control bit is 01, and data bit is represented 0 position; If a=0, making control bit is 01, and data bit is log
2(n+1) individual 1;
If b=1, making control bit is 00, and data bit is represented 1 position; If b=0, making control bit is 00, and data bit is log
2(n+1) individual 1;
If a＞1 and b＞1, the length that said test vector is got is that the section of n is divided into the section of length less than c, and each section use the c+2 bit representation, and making control bit is 11, data bit be correspondence length less than c section value.
8. the method that integrated circuit is tested as claimed in claim 6 is characterized in that, said step B further comprises:
B1: can detected each fault f for test vector, output set list (f)=(O that fault can propagate into is found out in simulation
1..., O
m);
B2:, find out the error listing observe (O that it can observe for each output
i)={ f
1..., f
t;
B3: output set and failure collection are carried out initialization, and making output set is all outputs that can observe fault, and failure collection is all faults that can be detected;
B4: from said output set, select the output that can observe maximum faults, the deletion fault that this output observed from said failure collection, deletion should be exported from output set simultaneously;
B5: repeating step B4 is empty until failure collection;
B6:, generate test response and select vector with being changed to 1 with the output corresponding cells of deleting in second control register from output set.
9. the method that integrated circuit is tested as claimed in claim 6 is characterized in that, said step C further comprises:
C1: the test vector to behind the coding is decoded;
C2: the test vector that decoding obtains is imported in n the scanning tree;
C3：i＝1；
C4: i scanning tree caught test response;
C5: select vector to shift out the test response of the needs observation of each scanning tree according to test response, move into the corresponding test vector of i scanning tree simultaneously again;
C6:i increases by 1, if i＜=n repeats C4 and C5.
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| PCT/CN2012/077512 WO2013016989A1 (en) | 2011-07-29 | 2012-06-26 | Test stimuli compression and test response compaction in low-power scan testing |
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Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102654561A (en) * | 2012-04-17 | 2012-09-05 | 清华大学 | Scanning and testing method based on three-dimensional chips |
| CN102879731A (en) * | 2012-09-26 | 2013-01-16 | 清华大学 | Digital integrated circuit test method |
| WO2013016989A1 (en) * | 2011-07-29 | 2013-02-07 | Tsinghua University | Test stimuli compression and test response compaction in low-power scan testing |
| CN104122497A (en) * | 2014-08-11 | 2014-10-29 | 中国科学院自动化研究所 | Circuit and method for generating test vectors required by built-in self-test of integrated circuit |
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| CN109581207A (en) * | 2018-12-19 | 2019-04-05 | 天津大学 | Low-cost circuit state control method for fault injection attack hardware simulation |
| CN109581207B (en) * | 2018-12-19 | 2020-12-11 | 天津大学 | Low-cost circuit state control method for fault injection attack hardware simulation |
| CN109581206B (en) * | 2018-12-19 | 2020-12-11 | 天津大学 | Integrated circuit fault injection attack simulation method based on partial scanning |
| WO2022087928A1 (en) * | 2020-10-28 | 2022-05-05 | 华为技术有限公司 | Method and apparatus for generating decompression circuit |
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| CN102305912B (en) | 2014-06-04 |
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