CN116739094A - Quantum circuit crosstalk optimization method and device, storage medium and electronic device - Google Patents
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Abstract
The application discloses a crosstalk optimization method and device of a quantum circuit, a storage medium and an electronic device, wherein the method comprises the following steps: acquiring attribute values of a quantum chip, wherein the quantum chip is used for running a quantum circuit; generating a corresponding satisfiability model theory SMT function for representing crosstalk according to the attribute value of the quantum chip and the quantum logic gate of the quantum circuit; and solving the SMT function, and reconstructing the quantum circuit according to the SMT function solution. By utilizing the embodiment of the application, the quantum circuit can be reconstructed according to the crosstalk so as to slow down the crosstalk influence in the execution process of the quantum circuit, improve the execution efficiency and stability of the quantum circuit and supplement the blank of the related technology.
Description
Technical Field
The application belongs to the technical field of quantum computing, and particularly relates to a crosstalk optimization method and device for a quantum circuit, a storage medium and an electronic device.
Background
With the continuous development of electronic technology, the frequency of signals in high-speed circuits becomes high, edges become steep, circuit boards become smaller, and the density of wirings becomes larger, so that signal integrity problems are more and more prominent in the design of high-speed digital circuits, which has become an unavoidable problem for high-speed circuit design engineers.
Crosstalk, which is an important issue in signal integrity, is a problem that is commonly found in digital designs and may occur on devices such as chips, PCBs, connectors, chip packages, and connector cables, and how to reduce the effects of chip crosstalk is a critical issue.
Disclosure of Invention
The application aims to provide a crosstalk optimization method and device for a quantum circuit, a storage medium and an electronic device, so as to solve the defects in the prior art, reconstruct the quantum circuit according to crosstalk, reduce the influence of the crosstalk in the execution process of the quantum circuit, improve the execution efficiency and stability of the quantum circuit and supplement the blank of the related technology.
One embodiment of the present application provides a method for optimizing crosstalk of a quantum wire, the method comprising:
acquiring attribute values of a quantum chip, wherein the quantum chip is used for running a quantum circuit;
generating a corresponding satisfiability model theory SMT function for representing crosstalk according to the attribute value of the quantum chip and the quantum logic gate of the quantum circuit;
and solving the SMT function, and reconstructing the quantum circuit according to the SMT function solution.
Optionally, the obtaining the attribute value of the quantum chip includes:
the coherence time of the quantum chip, the duration of the quantum logic gate operation, and the error rate are obtained.
Optionally, the generating a corresponding satisfaction theory SMT function for characterizing crosstalk includes:
and constructing a first constraint function according to the attribute numerical value of the quantum chip and the quantum logic gate of the quantum circuit, wherein the first constraint function is used for constraining the execution sequence of the quantum logic gate in the quantum circuit.
Optionally, the generating a corresponding satisfaction theory SMT function for characterizing crosstalk further includes:
and constructing a second constraint function according to the attribute numerical value of the quantum chip and the quantum logic gate of the quantum circuit, wherein the second constraint function is used for constraining the time sequence overlapping condition of the quantum logic gate in the quantum circuit.
Optionally, the generating a corresponding satisfaction theory SMT function for characterizing crosstalk further includes:
and constructing a third constraint function according to the attribute value of the quantum chip and the quantum logic gate of the quantum circuit, wherein the second constraint function is used for constraining the decoherence time of the quantum chip in the quantum circuit.
Optionally, the generating a corresponding satisfaction theory SMT function for characterizing crosstalk further includes:
and generating the satisfiability modular theory SMT function according to the first constraint function, the second constraint function and the third constraint function.
Optionally, reconstructing the quantum circuit according to the solution of the SMT function includes:
determining the initial running time of a quantum logic gate in the quantum circuit according to the solution of the satisfaction model theory function;
and determining the operation time of the quantum logic gate, and adding a barrier operation in the quantum circuit according to the initial operation time and the operation time of the quantum logic gate, wherein the barrier operation is used for separating the quantum logic gate.
Still another embodiment of the present application provides a crosstalk scheduling apparatus for a quantum wire, including:
the device comprises an acquisition module, a quantum chip and a control module, wherein the acquisition module is used for acquiring attribute values of the quantum chip, and the quantum chip is used for running a quantum circuit;
the generating module is used for generating a corresponding satisfiability model theory SMT function for representing crosstalk according to the attribute value of the quantum chip and the quantum logic gate of the quantum circuit;
and the reconstruction module is used for solving the SMT function and reconstructing the quantum circuit according to the SMT function solution.
An embodiment of the application provides a storage medium having a computer program stored therein, wherein the computer program is arranged to perform the method of any of the above when run.
An embodiment of the application provides an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the method of any of the above.
Compared with the prior art, the crosstalk optimization method of the quantum circuit provided by the application has the advantages that the attribute value of the quantum chip is obtained, and the quantum chip is used for running the quantum circuit; generating a corresponding satisfiability model theory SMT function for representing crosstalk according to the attribute value of the quantum chip and the quantum logic gate of the quantum circuit; solving the SMT function, and reconstructing the quantum circuit according to the solution of the SMT function, thereby realizing the reconstruction of the quantum circuit according to the SMT function corresponding to crosstalk, reducing the crosstalk influence in the execution process of the quantum circuit, improving the execution efficiency and stability of the quantum circuit, and supplementing the blank of the related technology.
Drawings
Fig. 1 is a hardware block diagram of a computer terminal of a method for optimizing crosstalk of a quantum circuit according to an embodiment of the present application;
fig. 2 is a schematic flow chart of a crosstalk optimization method of a quantum circuit according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a crosstalk optimization device for quantum circuits according to an embodiment of the present application.
Detailed Description
The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.
The embodiment of the application firstly provides a crosstalk optimization method of a quantum circuit, which can be applied to electronic equipment such as a computer terminal, in particular to a common computer, a quantum computer and the like.
The following describes the operation of the computer terminal in detail by taking it as an example. Fig. 1 is a hardware block diagram of a computer terminal of a method for optimizing crosstalk of a quantum circuit according to an embodiment of the present application. As shown in fig. 1, the computer terminal may include one or more (only one is shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a microprocessor MCU or a processing device such as a programmable logic device FPGA) and a memory 104 for storing data, and optionally, a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those skilled in the art that the configuration shown in fig. 1 is merely illustrative and is not intended to limit the configuration of the computer terminal described above. For example, the computer terminal may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.
The memory 104 may be used to store software programs and modules of application software, such as program instructions/modules corresponding to the crosstalk optimization method of the quantum wires in the embodiment of the present application, and the processor 102 executes the software programs and modules stored in the memory 104, thereby performing various functional applications and data processing, that is, implementing the method described above. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located relative to the processor 102, which may be connected to the computer terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission means 106 is arranged to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module for communicating with the internet wirelessly.
It should be noted that a real quantum computer is a hybrid structure, which includes two major parts: part of the computers are classical computers and are responsible for performing classical computation and control; the other part is quantum equipment, which is responsible for running quantum programs so as to realize quantum computation. The quantum program is a series of instruction sequences written by a quantum language such as the qlunes language and capable of running on a quantum computer, so that the support of quantum logic gate operation is realized, and finally, quantum computing is realized. Specifically, the quantum program is a series of instruction sequences for operating the quantum logic gate according to a certain time sequence.
In practical applications, quantum computing simulations are often required to verify quantum algorithms, quantum applications, etc., due to the development of quantum device hardware. Quantum computing simulation is a process of realizing simulated operation of a quantum program corresponding to a specific problem by means of a virtual architecture (namely a quantum virtual machine) built by resources of a common computer. In general, it is necessary to construct a quantum program corresponding to a specific problem. The quantum program, namely the program for representing the quantum bit and the evolution thereof written in the classical language, wherein the quantum bit, the quantum logic gate and the like related to quantum computation are all represented by corresponding classical codes.
Quantum circuits, which are one embodiment of quantum programs, also weigh sub-logic circuits, are the most commonly used general quantum computing models, representing circuits that operate on qubits under an abstract concept, the composition of which includes qubits, circuits (timelines), and various quantum logic gates, and finally the results often need to be read out by quantum measurement operations.
Unlike conventional circuits, which are connected by metal lines to carry voltage or current signals, in a quantum circuit, the circuit can be seen as being connected by time, i.e., the state of the qubit naturally evolves over time, as indicated by the hamiltonian operator, during which it is operated until a logic gate is encountered.
One quantum program is corresponding to one total quantum circuit, and the quantum program refers to the total quantum circuit, wherein the total number of quantum bits in the total quantum circuit is the same as the total number of quantum bits of the quantum program. It can be understood that: one quantum program may consist of a quantum circuit, a measurement operation for the quantum bits in the quantum circuit, a register to hold the measurement results, and a control flow node (jump instruction), and one quantum circuit may contain several tens to hundreds or even thousands of quantum logic gate operations. The execution process of the quantum program is a process of executing all quantum logic gates according to a certain time sequence. Note that the timing is the time sequence in which a single quantum logic gate is executed.
It should be noted that in classical computation, the most basic unit is a bit, and the most basic control mode is a logic gate, and the purpose of the control circuit can be achieved by a combination of logic gates. Similarly, the way in which the qubits are handled is a quantum logic gate. Quantum logic gates are used, which are the basis for forming quantum circuits, and include single-bit quantum logic gates, such as Hadamard gates (H gates, ada Ma Men), bery-X gates (X gates), bery-Y gates (Y gates), bery-Z gates (Z gates), RX gates, RY gates, RZ gates, and the like; two or more bit quantum logic gates, such as CNOT gates, CR gates, CZ gates, iSWAP gates, toffoli gates, and the like. Quantum logic gates are typically represented using unitary matrices, which are not only in matrix form, but also an operation and transformation. The effect of a general quantum logic gate on a quantum state is calculated by multiplying the unitary matrix by the matrix corresponding to the right vector of the quantum state.
Referring to fig. 2, fig. 2 is a schematic flow chart of a crosstalk optimization method of a quantum circuit according to an embodiment of the present application, which may include the following steps:
s201, obtaining attribute values of a quantum chip, wherein the quantum chip is used for running a quantum circuit;
specifically, the attribute values of the quantum chip may include, but are not limited to: the coherence time of the quantum chip, the duration of the quantum logic gate operation, and the error rate.
Illustratively, the coherence time of a single qubit may range from 10 microseconds to 100 microseconds. When two quantum wires are performing 30 microseconds, 50 microseconds, respectively, on the best qubit with 100 microsecond coherence time, the implementation error impact will be significantly higher in the latter compared to the former. Thus, completing the line operation in as short a coherence time as possible will achieve better performance results.
The duration of the quantum logic gate operation and the measurement operation refers to the running duration of the quantum logic gate operation and the quantum measurement operation, and the corresponding error rate refers to the error rate of running errors, and the error rate represents the reliability of the quantum bit.
The quantum chip is a processor of a quantum computer, and can actually run a quantum circuit by setting physical realization of quantum bits and quantum logic gates. In the process of actually operating the quantum circuit by the quantum chip, due to the limitation of hardware conditions, crosstalk can be influenced between quantum logic gates acting on adjacent quantum bits, and the influence on two quantum logic gates such as CNOT gates is larger when crosstalk occurs.
S202, generating a corresponding satisfiability model theory SMT function for representing crosstalk according to the attribute value of the quantum chip and a quantum logic gate of the quantum circuit;
specifically, the crosstalk avoidance problem can be converted into an optimization problem by constructing a constraint function through one or more constraint conditions, and the problem is solved by using an SMT (Satisfiability Modulo Theories, satisfiability modulo theory) function (solver).
In one implementation, a first constraint function may be constructed according to the attribute value of the quantum chip and the quantum logic gate of the quantum circuit, where the first constraint function is used to constrain an execution sequence of the quantum logic gate in the quantum circuit.
Specifically, the first constraint function corresponds to a data dependent constraint condition: representing the data dependency between two quantum operations, a, b, if both quantum operations operate on the same qubit and b uses the output of a, b starts execution after a execution is completed, b depends on a, b being mathematically represented as b > a. Let Q be the set of qubits and G be the set of quantum logic gates. For each gate g, the start time is denoted g.tau, the duration is denoted g.delta, the error rate is denoted g.epsilon.and for each qubit q, a coherence error rate variable q.epsilon.is set. An exemplary first constraint function is as follows:
furthermore, on the basis of constructing the first constraint function, a second constraint function can be constructed according to the attribute value of the quantum chip and the quantum logic gate of the quantum circuit, and the second constraint function is used for constraining the time sequence overlapping condition of the quantum logic gate in the quantum circuit.
Specifically, the second constraint function corresponds to a gate error constraint condition: this constraint sets a crosstalk-dependent error rate for each quantum logic gate, preferably a double quantum logic gate, for tracking whether the two quantum logic gates overlap when executing, i.e. are in the same timing, and the overlapping quantum logic gates may generate crosstalk and cause execution errors. An exemplary second constraint function is as follows:
o ij ＝(g j .τ≤g i .τ+g i .δ∧g i .τ≤g j .τ+g j .δ)
wherein O is ij Representing overlapping representations for tracking g i And g j Whether or not to overlap, canOlp (g) i ) Representation and quantum logic gate g i Set of all quantum logic gate operations overlapped Olp k Represents CanOlp (g) i ) Each non-null subset, notOlp, of the power set (powerset) k Representing complement, notOlp k ＝CanOlp(g i )\Olp k ，E(g j ) Indicating the error rate when one logic gate is not overlapping in time with other operations, i.e. the crosstalk-free independent error rate.
Further, a third constraint function can be constructed according to the attribute value of the quantum chip and the quantum logic gate of the quantum circuit, and the third constraint function is used for constraining the decoherence time of the quantum chip in the quantum circuit.
Specifically, the third constraint function corresponds to a decoherence error constraint condition: the constraint tracks decoherence errors that occur during the decoherence time of each qubit in the quantum circuit. An exemplary third constraint function is as follows:
q i .t＝L(q i ).τ+L(q i ).δ-F(q i ).τ
wherein q i T represents a qubit q i Life (available duration) of F (q) i ) Representing the effect on q i Is the first quantum logic gate of (1), L (q i ) Representing the effect on q i Last quantum logic gate, q i T represents q i The maximum usable time period that can be set.
Further, the satisfiability modulo theory SMT function may be generated according to the first constraint function, the second constraint function, and the third constraint function.
Specifically, the above constraint conditions may be used in combination in one or more of the following ways. Preferably, the SMT function may be generated according to each constraint function described above as follows:
substituting the definition of q.epsilon.gives:
optionally, to test the relative importance of crosstalk and decoherence errors, an additional crosstalk weight factor ωε [0,1] may be considered to obtain:
and S203, solving the SMT function, and reconstructing the quantum circuit according to the SMT function solution.
Specifically, the full name of SMT is Satisfiability Modulo Theories, which can be translated into "satisfiability modulo theory", "satisfiability problem under multiple theory", or "satisfiability problem under specific (background) theory", and its determination algorithm is called SMT solver. Briefly, an SMT formula is a logical formula that incorporates a theoretical background, where propositional variables may represent the theoretical formula. By solving the SMT function, judging whether crosstalk occurs or not and the position where the crosstalk occurs, the BARRIER bar is reasonably utilized to operate two logic gates which are spaced apart and are affected by the crosstalk, meanwhile, the influence of decoherence errors is required to be ensured, and the crosstalk is avoided in a lower coherence time. The SMT solver is in the prior art, and the application is not repeated herein, and the starting operation time of each quantum logic gate can be obtained by solving.
Specifically, the initial running time of the quantum logic gate in the quantum circuit can be determined according to the solution of the satisfaction model theory function; and determining the operation time of the quantum logic gate, and adding a barrier operation in the quantum circuit according to the initial operation time and the operation time of the quantum logic gate, wherein the barrier operation is used for separating the quantum logic gate. The operating duration of the quantum logic gate is fixed, in particular determined by the type of quantum logic gate.
For example, assuming a coherence time of 100 microseconds, according to the starting running time point, 10 two adjacent two-quantum logic gates in the same time sequence are obtained, while executing 1 two-quantum logic gate, if another two-quantum logic gate is executed, crosstalk is likely to occur, for which two logic gates can be separated by using a barrier operation, after one of the two logic gates is completed, then the other is executed, similar to the parallel execution of the two quantum logic gates separated into serial execution. However, performing barrier operations in a single pass increases the total execution time of the quantum logic gate, resulting in a quantum circuit that can be executed at a later point in time within the coherence time and even beyond the coherence time range, and significantly increases decoherence errors. Therefore, in practical application, the SMT function solution can be used for optimization, so that the quantum logic gate which preferably uses barrier operation and the starting operation time point and operation time length thereof are obtained, and crosstalk-generating quantum logic gates are developed by as many barriers as possible in the shortest possible coherence time, so that the crosstalk is relieved and the decoherence influence is balanced.
The quantum chip is used for running the quantum circuit by acquiring the attribute value of the quantum chip; generating a corresponding satisfiability model theory SMT function for representing crosstalk according to the attribute value of the quantum chip and the quantum logic gate of the quantum circuit; solving the SMT function, and reconstructing the quantum circuit according to the solution of the SMT function, thereby realizing the reconstruction of the quantum circuit according to the SMT function corresponding to crosstalk, reducing the crosstalk influence in the execution process of the quantum circuit, improving the execution efficiency and stability of the quantum circuit, and supplementing the blank of the related technology.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a crosstalk optimization device for quantum circuits according to an embodiment of the present application, corresponding to the flow shown in fig. 2, where the device includes:
the obtaining module 301 is configured to obtain an attribute value of a quantum chip, where the quantum chip is used to operate a quantum circuit;
the generating module 302 is configured to generate a corresponding satisfiability model theory SMT function for characterizing crosstalk according to the attribute value of the quantum chip and a quantum logic gate of the quantum circuit;
and the reconstruction module 303 is configured to solve the SMT function, and reconstruct the quantum circuit according to the solution of the SMT function.
Specifically, the obtaining module is specifically configured to:
the coherence time of the quantum chip, the duration of the quantum logic gate operation, and the error rate are obtained.
Specifically, the generating module is specifically configured to:
and constructing a first constraint function according to the attribute numerical value of the quantum chip and the quantum logic gate of the quantum circuit, wherein the first constraint function is used for constraining the execution sequence of the quantum logic gate in the quantum circuit.
Specifically, the generating module is specifically further configured to:
and constructing a second constraint function according to the attribute numerical value of the quantum chip and the quantum logic gate of the quantum circuit, wherein the second constraint function is used for constraining the time sequence overlapping condition of the quantum logic gate in the quantum circuit.
Specifically, the generating module is specifically further configured to:
and constructing a third constraint function according to the attribute value of the quantum chip and the quantum logic gate of the quantum circuit, wherein the second constraint function is used for constraining the decoherence time of the quantum chip in the quantum circuit.
Specifically, the generating module is specifically further configured to:
and generating the satisfiability modular theory SMT function according to the first constraint function, the second constraint function and the third constraint function.
Specifically, the reconstruction module is specifically configured to:
determining the initial running time of a quantum logic gate in the quantum circuit according to the solution of the satisfaction model theory function;
and determining the operation time of the quantum logic gate, and adding a barrier operation in the quantum circuit according to the initial operation time and the operation time of the quantum logic gate, wherein the barrier operation is used for separating the quantum logic gate.
The quantum chip is used for running the quantum circuit by acquiring the attribute value of the quantum chip; generating a corresponding satisfiability model theory SMT function for representing crosstalk according to the attribute value of the quantum chip and the quantum logic gate of the quantum circuit; solving the SMT function, and reconstructing the quantum circuit according to the solution of the SMT function, thereby realizing the reconstruction of the quantum circuit according to the SMT function corresponding to crosstalk, reducing the crosstalk influence in the execution process of the quantum circuit, improving the execution efficiency and stability of the quantum circuit, and supplementing the blank of the related technology.
The embodiment of the application also provides a storage medium, in which a computer program is stored, wherein the computer program is configured to perform the steps of any of the method embodiments described above when run.
Specifically, in the present embodiment, the above-described storage medium may be configured to store a computer program for executing the steps of:
s1, acquiring attribute values of a quantum chip, wherein the quantum chip is used for running a quantum circuit;
s2, generating a corresponding satisfiability model theory SMT function for representing crosstalk according to the attribute value of the quantum chip and the quantum logic gate of the quantum circuit;
and S3, solving the SMT function, and reconstructing the quantum circuit according to the SMT function solution.
Specifically, in the present embodiment, the storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.
An embodiment of the application also provides an electronic device comprising a memory and a processor, characterized in that the memory has stored therein a computer program, the processor being arranged to run the computer program to perform the steps of any of the method embodiments described above.
Specifically, the electronic apparatus may further include a transmission device and an input/output device, where the transmission device is connected to the processor, and the input/output device is connected to the processor.
Specifically, in the present embodiment, the above-described processor may be configured to execute the following steps by a computer program:
s1, acquiring attribute values of a quantum chip, wherein the quantum chip is used for running a quantum circuit;
s2, generating a corresponding satisfiability model theory SMT function for representing crosstalk according to the attribute value of the quantum chip and the quantum logic gate of the quantum circuit;
and S3, solving the SMT function, and reconstructing the quantum circuit according to the SMT function solution.
While the foregoing is directed to embodiments of the present application, other and further embodiments of the application may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (10)
1. A method for crosstalk optimization of a quantum wire, the method comprising:
acquiring attribute values of a quantum chip, wherein the quantum chip is used for running a quantum circuit;
generating a corresponding satisfiability model theory SMT function for representing crosstalk according to the attribute value of the quantum chip and the quantum logic gate of the quantum circuit;
and solving the SMT function, and reconstructing the quantum circuit according to the SMT function solution.
2. The method of claim 1, wherein the obtaining the property value of the quantum chip comprises:
the coherence time of the quantum chip, the duration of the quantum logic gate operation, and the error rate are obtained.
3. The method of claim 1, wherein generating a corresponding satisfiability modulo theory SMT function for characterizing crosstalk comprises:
and constructing a first constraint function according to the attribute numerical value of the quantum chip and the quantum logic gate of the quantum circuit, wherein the first constraint function is used for constraining the execution sequence of the quantum logic gate in the quantum circuit.
4. A method according to claim 3, wherein generating a corresponding satisfiability modulo theory SMT function for characterizing crosstalk, further comprises:
and constructing a second constraint function according to the attribute numerical value of the quantum chip and the quantum logic gate of the quantum circuit, wherein the second constraint function is used for constraining the time sequence overlapping condition of the quantum logic gate in the quantum circuit.
5. The method of claim 4, wherein generating a corresponding satisfiability modulo theory SMT function for characterizing crosstalk, further comprises:
and constructing a third constraint function according to the attribute value of the quantum chip and the quantum logic gate of the quantum circuit, wherein the second constraint function is used for constraining the decoherence time of the quantum chip in the quantum circuit.
6. The method of claim 5, wherein generating a corresponding satisfiability modulo theory SMT function for characterizing crosstalk, further comprises:
and generating the satisfiability modular theory SMT function according to the first constraint function, the second constraint function and the third constraint function.
7. The method of claim 1, wherein the reconstructing the quantum wires from the solution of the SMT function comprises:
determining the initial running time of a quantum logic gate in the quantum circuit according to the solution of the satisfaction model theory function;
and determining the operation time of the quantum logic gate, and adding a barrier operation in the quantum circuit according to the initial operation time and the operation time of the quantum logic gate, wherein the barrier operation is used for separating the quantum logic gate.
8. A crosstalk scheduling apparatus for a quantum wire, the apparatus comprising:
the device comprises an acquisition module, a quantum chip and a control module, wherein the acquisition module is used for acquiring attribute values of the quantum chip, and the quantum chip is used for running a quantum circuit;
the generating module is used for generating a corresponding satisfiability model theory SMT function for representing crosstalk according to the attribute value of the quantum chip and the quantum logic gate of the quantum circuit;
and the reconstruction module is used for solving the SMT function and reconstructing the quantum circuit according to the SMT function solution.
9. A storage medium having a computer program stored therein, wherein the computer program is arranged to perform the method of any of claims 1 to 7 when run.
10. An electronic device comprising a memory and a processor, characterized in that the memory has stored therein a computer program, the processor being arranged to run the computer program to perform the method of any of the claims 1 to 7.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117892830A (en) * | 2024-03-14 | 2024-04-16 | 山东云海国创云计算装备产业创新中心有限公司 | Compensation method for qubit driven crosstalk, qubit compensation method and product |
| CN117892830B (en) * | 2024-03-14 | 2024-05-31 | 山东云海国创云计算装备产业创新中心有限公司 | Compensation method for qubit driven crosstalk, qubit compensation method and product |
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| CN110826719A (en) * | 2019-10-14 | 2020-02-21 | 合肥本源量子计算科技有限责任公司 | Quantum program processing method and device, storage medium and electronic device |
| US20210152189A1 (en) * | 2019-11-18 | 2021-05-20 | International Business Machines Corporation | Instruction scheduling facilitating mitigation of crosstalk in a quantum computing system |
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| CN110826719A (en) * | 2019-10-14 | 2020-02-21 | 合肥本源量子计算科技有限责任公司 | Quantum program processing method and device, storage medium and electronic device |
| US20210152189A1 (en) * | 2019-11-18 | 2021-05-20 | International Business Machines Corporation | Instruction scheduling facilitating mitigation of crosstalk in a quantum computing system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117892830A (en) * | 2024-03-14 | 2024-04-16 | 山东云海国创云计算装备产业创新中心有限公司 | Compensation method for qubit driven crosstalk, qubit compensation method and product |
| CN117892830B (en) * | 2024-03-14 | 2024-05-31 | 山东云海国创云计算装备产业创新中心有限公司 | Compensation method for qubit driven crosstalk, qubit compensation method and product |
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