WO2024066808A1

WO2024066808A1 - Quantum circuit generation method and apparatus, storage medium, and electronic device

Info

Publication number: WO2024066808A1
Application number: PCT/CN2023/114232
Authority: WO
Inventors: 方圆; 冷博洋; 王奥博
Original assignee: 本源量子计算科技（合肥）股份有限公司
Priority date: 2022-09-30
Filing date: 2023-08-22
Publication date: 2024-04-04
Also published as: CN117852659A

Abstract

A quantum circuit generation method and apparatus, a storage medium, and an electronic device. The method comprises: obtaining a target temporary variable required for executing an initial quantum program; determining a target quantum bit according to the target temporary variable, wherein an initial state of the target quantum bit is a |0> state; on the basis of the initial quantum program, determining a target quantum logic gate enabling a final state of the target quantum bit to be the |0> state; and generating a target quantum circuit on the basis of the initial quantum program and the target quantum logic gate. According to embodiments of the present application, by adding a quantum logic gate enabling a final state of a quantum bit corresponding to a temporary variable to be a |0> state into a quantum circuit, the effect of addition of the temporary variable on a calculation result can be eliminated, and the possibility of errors of the calculation result is reduced.

Description

Quantum circuit generation method, device, storage medium and electronic device

This application claims the priority of the Chinese patent application filed with the China Patent Office on September 30, 2022, with application number 202211220055.4 and invention name “Quantum circuit generation method, device, storage medium and electronic device”, all contents of which are incorporated by reference in this application.

Technical Field

The present application belongs to the field of quantum computing technology, and in particular to a quantum circuit generation method, device, storage medium and electronic device.

Background technique

Quantum computing is a new computing model that follows the laws of quantum mechanics to control quantum information units for computing. The most basic principle of quantum computing is the principle of quantum mechanical superposition, which allows the state of quantum information units to be in a superposition state of multiple possibilities, making quantum information processing more efficient than classical information processing. Quantum computing is being applied in more and more fields due to its powerful computing power. For example, it is used to evaluate financial markets and perform financial operations based on the evaluation results.

In the process of quantum computing, in order to save quantum bit resources, temporary variables are generally introduced into the quantum program, and quantum bits are applied for temporary variables during the calculation process, so that the applied bits will be added to the quantum circuit. In the classical field, the addition of temporary variables will not affect the calculation results, but in the quantum field, in order for the temporary variables to be able to operate with other quantum bits in the circuit, a quantum bit needs to be allocated to the temporary variable. However, because the quantum calculation results are obtained by measuring the final state of the quantum circuit, the introduction of temporary variables will affect the final state, thereby affecting the measurement results, and may result in erroneous calculation results. However, there is currently no better method to cancel the calculation of temporary variables in the quantum circuit and reduce the possibility of errors in the calculation results.

Summary of the invention

The purpose of the present application is to provide a quantum circuit generation method, device, storage medium and electronic device, which can eliminate the influence of the addition of temporary variables on the calculation results by adding a quantum logic gate in the quantum circuit that makes the final state of the quantum bit corresponding to the temporary variable be the |0> state, thereby reducing the possibility of errors in the calculation results.

An embodiment of the present application provides a method for generating a quantum circuit, the method comprising:

Obtain the target temporary variables required to execute the initial quantum program;

Determine a target quantum bit according to the target temporary variable, wherein the initial state of the target quantum bit is a |0> state;

Based on the initial quantum program, determining a target quantum logic gate that makes the final state of the target quantum bit a |0> state;

Based on the initial quantum program and the target quantum logic gate, a target quantum circuit is generated.

Optionally, determining a target quantum bit according to the target temporary variable includes:

From the preset quantum bits, an idle quantum bit is allocated to the target temporary variable as the target quantum bit.

Optionally, determining, based on the initial quantum program, a target quantum logic gate that makes the final state of the target quantum bit a |0> state comprises:

Determining a quantum logic gate acting on the target quantum bit according to the initial quantum program;

Based on the determined quantum logic gate, a target quantum logic gate that makes the final state of the target quantum bit a |0> state is determined.

Optionally, determining a quantum logic gate acting on the target quantum bit according to the initial quantum program includes:

Obtaining a topological graph containing the target quantum bit, wherein the topological graph is generated using the initial quantum program, the initial node represents the quantum bit, the other nodes represent the quantum logic gates, and the edges represent the association relationship between the nodes;

Based on the topological graph, a quantum logic gate acting on the target quantum bit is determined.

Optionally, generating a target quantum circuit based on the initial quantum program and the target quantum logic gate includes:

In the current topology graph, determine the adding position of the target quantum logic gate and add the corresponding node;

According to the association relationship in the current topology diagram, determine the node that has an association relationship with the newly added node;

Establishing edges between the determined nodes and the newly added nodes to determine a new topological graph;

Based on the new topological graph, a target quantum circuit is generated.

Optionally, generating a target quantum circuit based on the new topological graph includes:

Determine the quantum logic gate, execution sequence, and action relationship acting on each quantum bit according to the new topological diagram;

Based on the execution sequence and the action relationship, the determined quantum logic gates are sequentially applied to corresponding quantum bits to generate a target quantum circuit.

Optionally, the method further includes:

When the life cycle of the target temporary variable ends, the target quantum bit is released so that the target quantum bit can be reallocated.

Another embodiment of the present application provides a quantum circuit generation device, the device comprising:

An acquisition module, used for obtaining target temporary variables required for executing an initial quantum program;

A first determination module is used to determine a target quantum bit according to the target temporary variable, wherein the initial state of the target quantum bit is a |0> state;

A second determination module is used to determine a target quantum logic gate that makes the final state of the target quantum bit a |0> state based on the initial quantum program;

A generation module is used to generate a target quantum circuit based on the initial quantum program and the target quantum logic gate.

Optionally, the first determining module is specifically configured to:

Optionally, the second determining module includes:

A first determining unit, configured to determine a quantum logic gate acting on the target quantum bit according to the initial quantum program;

The second determining unit is used to determine a target quantum logic gate that makes the final state of the target quantum bit a |0> state based on the determined quantum logic gate.

Optionally, the first determining unit is specifically configured to:

Optionally, the generating module is specifically used for:

According to the association relationship in the current topology map, determine the node that has an association relationship with the newly added node. point;

Based on the new topological graph, a target quantum circuit is generated.

Optionally, the generating module is further specifically used for:

Optionally, the device further comprises:

A release module is used to release the target quantum bit when the life cycle of the target temporary variable ends, so that the target quantum bit can be reallocated.

An embodiment of the present application provides a storage medium, in which a computer program is stored, wherein the computer program is configured to implement any of the above methods when running.

An embodiment of the present application provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to implement any of the above methods.

An embodiment of the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute any of the above-described methods.

Compared with the prior art, the quantum circuit generation method provided by the present application first obtains the target temporary variable required for executing the initial quantum program; determines the target quantum bit according to the target temporary variable; then determines the target quantum logic gate that makes the final state of the target quantum bit |0> state based on the initial quantum program; finally, generates the target quantum circuit based on the initial quantum program and the target quantum logic gate. Through the initial quantum program, the quantum logic gate that makes the final state of the quantum bit corresponding to the temporary variable |0> state is determined and added to the corresponding position, thereby obtaining the final quantum circuit, eliminating the influence of the addition of the temporary variable on the calculation result, thereby reducing the possibility of errors in the calculation result.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application.

FIG1 is a hardware diagram of a computer terminal for a quantum circuit generation method provided in an embodiment of the present application. Structure diagram;

FIG2 is a schematic diagram of a flow chart of a quantum circuit generation method provided in an embodiment of the present application;

FIG3 is a schematic diagram of a topological map generated based on an initial quantum program provided in an embodiment of the present application;

FIG4 is a schematic diagram of a node adding order corresponding to a target quantum logic gate provided in an embodiment of the present application;

FIG5 is a schematic diagram of a topological diagram after adding a node corresponding to a target quantum logic gate provided in an embodiment of the present application;

FIG6 is a schematic diagram of another topological map generated based on an initial quantum program provided in an embodiment of the present application;

FIG7 is a schematic diagram of another topological diagram after adding a node corresponding to a target quantum logic gate provided in an embodiment of the present application;

FIG8 is a schematic diagram of a generated target quantum circuit provided in an embodiment of the present application;

FIG9 is a schematic diagram of allocating quantum bits to temporary variables provided by an embodiment of the present application;

FIG10 is a schematic diagram of the structure of a quantum circuit generation device provided in an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solution, and advantages of the present application more clearly understood, the present application is further described in detail with reference to the accompanying drawings and examples. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field belong to the scope of protection of the present application.

The embodiment of the present application first provides a quantum circuit generation method, which can be applied to electronic devices, such as computer terminals, specifically ordinary computers, quantum computers, etc.

Quantum computers are physical devices that follow the laws of quantum mechanics to perform high-speed mathematical and logical operations, store and process quantum information. When a device processes and calculates quantum information and runs quantum algorithms, it is a quantum computer. Quantum computers have become a key technology under research because they have the ability to process mathematical problems more efficiently than ordinary computers. For example, they can speed up the time to crack RSA (Rivest-Adi Shamir-Leonard Adleman) keys from hundreds of years to a few hours.

The following is a detailed description of quantum computing running on a computer terminal as an example. FIG1 is a hardware structure block diagram of a computer terminal of a quantum circuit generation method provided in an embodiment of the present application. As shown in FIG1 , the computer terminal may include one or more (only one is shown in FIG1 ) processors 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor (MCU, Micro Controller Unit) or a programmable logic device (FPGA, Field Programmable Gate Array)) and a memory 104 for storing data. Optionally, the computer terminal may also include a transmission device 106 and an input/output device 108 for communication functions. It will be appreciated by those skilled in the art that the structure shown in FIG1 is for illustration only and does not limit the structure of the computer terminal. For example, the computer terminal may also include more or fewer components than those shown in FIG1 , or have a configuration different from that shown in FIG1 .

The memory 104 can be used to store software programs and modules of application software, such as program instructions/modules corresponding to the quantum circuit generation method in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, implementing the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the computer terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (Radio Frequency, RF) module, which is used to communicate with the Internet wirelessly. The transmission device 106 can also be an ETH (Ethernet) module, which is used to communicate with the Internet via a wired method.

It should be noted that a true quantum computer is a hybrid structure, which consists of two parts: one part is a classical computer, which is responsible for performing classical calculations and control; the other part is a quantum device, which is responsible for running quantum programs and thus realizing quantum computing. A quantum program is a sequence of instructions written in a quantum language such as QRunes that can be run on a quantum computer, which supports quantum logic gate operations and ultimately realizes quantum computing. Specifically, a quantum program is a sequence of instructions that operate quantum logic gates in a certain sequence.

In practical applications, quantum computing is usually required due to the limitations of the development of quantum device hardware. Simulation to verify quantum algorithms, quantum applications, etc. Quantum computing simulation is the process of simulating the operation of quantum programs corresponding to specific problems by using a virtual architecture (i.e., quantum virtual machine) built with the resources of ordinary computers. Usually, it is necessary to build a quantum program corresponding to a specific problem. The quantum program referred to in the embodiment of the present application is a program written in a classical language to characterize quantum bits and their evolution, in which quantum bits, quantum logic gates, etc. related to quantum computing are represented by corresponding classical codes.

Quantum circuits, as a manifestation of quantum programs, are also called quantum logic circuits. They are the most commonly used general quantum computing model. They represent circuits that operate on quantum bits in an abstract concept. They are composed of quantum bits, circuits (timelines), and various quantum logic gates. Finally, the results often need to be read out through quantum measurement operations.

Unlike traditional circuits that are connected by metal wires to transmit voltage or current signals, in quantum circuits, the circuits can be seen as connected by time, that is, the state of the quantum bit evolves naturally over time, following the instructions of the Hamiltonian operator until it encounters a logic gate and is operated.

A quantum program as a whole corresponds to a total quantum circuit, and the quantum program described in this application refers to the total quantum circuit, wherein the total number of quantum bits in the total quantum circuit is the same as the total number of quantum bits in the quantum program. It can be understood that a quantum program can be composed of a quantum circuit, a measurement operation on the quantum bits in the quantum circuit, a register for storing the measurement results, and a control flow node (jump instruction). A quantum circuit can contain dozens, hundreds, or even thousands of quantum logic gate operations. The execution process of a quantum program is the process of executing all quantum logic gates in a certain sequence. It should be noted that the sequence is the time order in which a single quantum logic gate is executed.

It should be noted that in classical computing, the most basic unit is the bit, and the most basic control mode is the logic gate, which can achieve the purpose of controlling the circuit through the combination of logic gates. Similarly, the way to process quantum bits is quantum logic gates. Using quantum logic gates, quantum states can evolve. Quantum logic gates are the basis of quantum circuits. Quantum logic gates include single-bit quantum logic gates, such as Hadamard gates (H gates, Hadamard gates), Pauli-X gates (X gates), Pauli-Y gates (Y gates), Pauli-Z gates (Z gates), RX gates, RY gates, RZ gates, etc.; two-bit or multi-bit quantum logic gates, such as CNOT gates, CR gates, CZ gates, iSWAP gates, Toffoli gates, etc. Quantum logic gates are generally represented by unitary matrices, which are not only matrix forms, but also operations and transformations. The effect of general quantum logic gates on quantum states is calculated by multiplying the unitary matrix on the left by the matrix corresponding to the right vector of the quantum state.

See FIG. 2 , which is a schematic diagram of a process of a quantum circuit generation method provided in an embodiment of the present application. The diagram may include the following steps:

S201: Obtain target temporary variables required for executing the initial quantum program.

Unlike global variables, temporary variables are variables that are not declared at the beginning of the program, that is, they are declared only when they are used. Temporary variables are automatically destroyed after the function call to which they belong is completed.

It should be noted that temporary variables are variables that are temporarily required when executing a quantum program. Temporary variables may or may not be recorded in the initial quantum program. There may be more than one target temporary variable required to execute the initial quantum program. When the initial quantum program records the target temporary variable, the target temporary variable can be directly obtained from the initial quantum program. Of course, the target temporary variable can also be obtained in other ways, such as obtaining the target temporary variable from pre-recorded temporary variable information. When the target temporary variable is not recorded in the initial quantum program, the initial quantum program is analyzed, and the temporary variable required for the execution of the initial quantum program is used as the target temporary variable, or the target temporary variable is obtained through the information recorded for the initial quantum program.

S202: Determine a target quantum bit according to the target temporary variable, wherein an initial state of the target quantum bit is a |0> state.

In order to allow temporary variables to operate with other qubits in the quantum circuit and realize the corresponding functions of temporary variables, it is necessary to allocate qubits to temporary variables. Specifically, the target qubit can be determined based on the predetermined mapping relationship between temporary variables and qubits, or a random qubit can be selected from the qubits allocated to the temporary variable as the target qubit. When there is more than one target temporary variable, a target qubit is allocated to each target temporary variable. It should be noted that the qubit allocated to the target temporary variable is called the target qubit.

In some possible implementations of the present application, determining a target quantum bit according to the target temporary variable includes:

The pre-set qubits are qubits prepared in advance for temporary variables. These qubits do not overlap with the qubits already defined in the quantum program. For example, the initial quantum program has defined qubits 1-5, a total of five qubits; the pre-set qubits may be qubits 6-8, a total of three qubits. When a temporary variable needs to be assigned qubits, an idle qubit is selected from these qubits (i.e., qubits 6-8) and assigned to the temporary variable. The selected qubit is the target qubit. In a specific implementation of the present application, the pre-set qubits are The sub-bits can be stored in a global pool, which uses a stack structure. When a temporary variable needs to be allocated a qubit and the available bits in the global pool are not empty, a qubit is popped from the top of the stack and allocated to the required temporary variable. For example, a sufficient number of qubits can be set in the global pool in advance based on the temporary variables in the initial quantum program to avoid the situation where qubits need to be allocated for temporary variables and the available bits in the global pool are empty.

S203: Based on the initial quantum program, determine a target quantum logic gate that makes the final state of the target quantum bit a |0> state.

In the implementation mode of the present application, the initial state of the quantum bit is prepared, and information can be prepared on the quantum bit by encoding, and the information is the initial state of the quantum bit. The initial state of the quantum bit will change with the operation of the quantum program (i.e., it evolves over time on the quantum circuit), and the final state of the quantum bit is obtained. The quantum state of the target quantum bit will change, because the entanglement of the quantum state will also change the quantum state of other quantum bits. In order to eliminate the influence of the temporary variable, it is necessary to determine the target quantum logic gate that makes the final state of the target quantum bit |0>.

Based on the initial quantum program, the final state of the target quantum bit can be determined if the influence of the temporary variable is not eliminated. Based on this final state, the quantum logic gate that makes the final state of the target quantum bit |0> can be determined. The determined quantum logic gate is the target quantum logic gate, and there can be more than one target quantum logic gate. In other words, the quantum state of the target quantum bit can be evolved based on the quantum logic gate in the initial quantum program to obtain the final state of the target quantum bit in this case. The final state obtained is also the final state of the target quantum bit without eliminating the influence of the temporary variable. Furthermore, the target quantum logic gate is determined in combination with the final state, so that when the initial state of the target quantum bit is the |0> state, after being processed by the quantum logic gate in the initial quantum program and the target quantum logic gate, the final state of the target quantum bit is still the |0> state. That is, the target quantum logic gate can offset the evolution of the quantum state of the target quantum bit by the quantum logic gate in the initial quantum program.

In some possible implementations of the present application, determining, based on the initial quantum program, a target quantum logic gate that makes the final state of the target quantum bit a |0> state includes:

Based on the initial quantum program, the quantum logic gate acting on the target quantum bit can be determined. The quantum logic gate determined here is the quantum logic gate in the initial quantum program. Specifically, it can be determined by The content recorded in the initial quantum program, or the information obtained based on the initial quantum program, such as the syntax tree, is parsed to determine the quantum logic gate acting on the target quantum bit in the initial quantum program. It should be noted that in the initial quantum program, when the target quantum bit is used as the target bit of a two-bit or multi-bit quantum logic gate, the two-bit or multi-bit quantum logic gate is a quantum logic gate acting on the target quantum bit.

In an embodiment of the present application, a quantum logic gate having the opposite function to the quantum logic gate determined to act on the target quantum bit can be used as the target quantum logic gate. Specifically, the inverse gate of the quantum logic gate acting on the target quantum bit can be used as the target quantum logic gate, wherein the inverse gate of any quantum logic gate is used to realize the evolution opposite to that of the quantum logic gate; or, multiple quantum logic gates can be determined according to the function of the quantum logic gate determined to act on the target quantum bit, so that the multiple quantum logic gates determined can offset the function of the quantum logic gate acting on the target quantum bit, and the multiple quantum logic gates determined are used as the target quantum logic gate. Exemplarily, when the quantum logic gate determined to act on the target quantum bit is a CNOT gate, based on the characteristics of the CNOT gate, the target quantum logic gate determined is also a CNOT gate. The specific determination method can determine the target quantum logic gate according to the mapping relationship between the pre-established quantum logic gate and its corresponding inverse gate.

In some possible implementations of the present application, determining a quantum logic gate acting on the target quantum bit according to the initial quantum program includes:

In the implementation mode of the present application, the topological map is generated by using the initial quantum program. Specifically, the topological map is generated according to the execution order of the programs in the quantum program, reflecting the structure of the quantum program. Exemplarily, the topological map can be a directed acyclic graph or a mathematical model circuit diagram. The topological map contains the target quantum bits. The initial nodes in the topological map represent the quantum bits, that is, the number of initial nodes is the number of quantum bits. The association relationship between the nodes may include the action relationship between the initial node and other nodes, the execution order relationship and constraint relationship between other nodes, and the controlled relationship of the quantum logic gates corresponding to the nodes, etc. Exemplarily, the quantum program is:

circuit<<H(q0)

circuit<<CNOT(q0,aux)

circuit<<CNOT(aux,q1)

circuit<<CNOT(q1,q0)

Among them, circuit is the representation of quantum circuit, << is the program symbol, H and CNOT are the symbols of quantum logic gates, and q0, q1 and aux are the symbols of quantum bits.

circuit<<H(q0) means: in the quantum circuit, the H gate acts on q0.

circuit<<CNOT(q0,aux) means: in the quantum circuit there is a CNOT gate whose control bit is q0 and target bit is aux.

circuit<<CNOT(aux,q1) means: in the quantum circuit there is a CNOT gate whose control bit is aux and target bit is q1.

circuit<<CNOT(q1,q0) means: in the quantum circuit, there is a CNOT gate whose control bit is q1 and target bit is q0.

Based on this quantum program, the generated topology graph can be shown in Figure 3, where init is the initial node, representing quantum bits q0, q1, and q2. Specifically, q0 and q1 are initialized quantum bits, q2 is the target quantum bit corresponding to the temporary variable aux, q0 ₁ represents the first quantum logic gate acting on quantum bit q0 ₀ , and q0 ₂ represents the second quantum logic gate acting on quantum bit q0 _0. The edges between nodes represent the association between nodes. Specifically, the symbol between the initial node and the quantum logic gate is Representing the quantum bits acted upon by quantum logic gates, and the symbols between quantum logic gates The execution timing between quantum logic gates can be characterized. For example, for q0, the H gate is executed first, and then the CNOT gate.

Symbols between quantum logic gates The quantum logic gate pointed to is the controlled quantum logic gate. The quantum bit pointed to by the arrow is the target bit of the controlled quantum logic gate. The quantum bit corresponding to the dot is the control bit of the controlled quantum logic gate. Take the quantum logic gate CNOT corresponding to q2 ₁ as an example. After the H gate is executed, the CNOT gate is executed. The control bit of CNOT is q0 and the target bit is q2. The quantum bit pointed to by the arrow means that the quantum logic gate pointed to by the arrow is the quantum bit as the target bit. The quantum bit corresponding to the dot, that is, the quantum logic gate at the dot is the quantum bit as the control bit.

Taking Figure 3 as an example, based on the topological graph, by traversing the logic gates related to q2, it can be determined that the quantum logic gate acting on the target quantum bit is a CNOT gate. Then, the gate with the opposite function to the CNOT gate or the inverse gate of the CNOT gate is determined as the target quantum logic gate. Based on the properties of the CNOT gate, it can be known that when two CNOT gates are continuously applied to the same quantum bit, it is equivalent to having no effect. Therefore, the target quantum logic gate can be a CNOT gate. The topological graph can clearly reflect the structure of the quantum program. Based on the topological graph structure, the quantum logic gate acting on the target quantum bit can be found relatively quickly and conveniently. When there is more than one gate acting on the target quantum bit, the gates acting on the target quantum bit are traversed step by step in reverse order, that is, traversing upward from the end node determined by the last logic gate related to the target quantum bit in the topological graph to determine the quantum logic gate acting on the target quantum bit.

S204: Generate a target quantum circuit based on the initial quantum program and the target quantum logic gate.

By adding the target quantum logic gate at the corresponding position in the initial quantum program, the target quantum circuit is generated. The position where the target quantum logic gate is added can be determined by the position of the quantum logic gate acting on the target quantum bit in the initial quantum program. Specifically, the position where the target quantum logic gate is added can be adjacent to the quantum logic gate acting on the target quantum bit in the initial quantum program, or the position is relatively close to the quantum logic gate acting on the target quantum bit in the initial quantum program. The principle is that adding the target quantum logic gate cannot change the final state of other quantum bits obtained without adding temporary variables.

In quantum computing, temporary variables have an impact on the calculation results, which is determined by the characteristics of quantum computing itself. Quantum computing obtains results based on the entanglement of quantum states, and temporary variables will participate in the calculation because the quantum states of the quantum bits assigned to them will participate in the calculation, thereby changing the entanglement results of the quantum states, and thus affecting the calculation results. The solution provided by the embodiment of the present application includes a target quantum logic gate in the target quantum circuit. When the target quantum circuit is run, because the initial state of the target quantum bit obtained is the |0> state, during the calculation process, the final state of the target quantum bit is reset to the |0> state through the quantum logic gate, realizing the automatic cancellation of the calculation of the temporary variable, that is, through the newly added target quantum logic gate, the processing of the temporary variable by the entire quantum circuit will not affect other quantum bits, thereby eliminating the influence of the temporary variable on the results of other quantum bits, thereby reducing the possibility of errors in the calculation results.

In a possible implementation of the present application, generating a target quantum circuit based on the initial quantum program and the target quantum logic gate includes:

According to the association relationship in the current topology map, determine the node that has an association relationship with the newly added node;

Based on the new topological graph, a target quantum circuit is generated.

The structure of the topological graph reflects the order in which quantum logic gates are executed. The nodes corresponding to the target quantum logic gates can be added to the topological graph, and the target quantum circuit can be generated based on the topological graph to accurately eliminate Influence of temporary variables. Specifically, the node corresponding to the target quantum logic gate can be added at the determined position after the node corresponding to the quantum logic gate currently acting on the target quantum bit. When there is more than one target quantum logic gate, the corresponding nodes are added in the reverse order of the corresponding quantum logic gates. For example, as shown in FIG. 4, _U1 and _U2 are U gates acting on the target quantum bit. They are the target quantum logic gates corresponding to U ₁ and U ₂ respectively. First add Corresponding nodes, then add It can be seen that after traversing the quantum logic gates acting on the target quantum bits in reverse order in the above embodiment, the corresponding target quantum logic gates can be determined in turn according to the determined order of the quantum logic gates, and the corresponding nodes can be added to the topology graph.

Based on the principle of making the quantum state of the target quantum bit finally | 0 > state, based on the current topological map, the node corresponding to the quantum logic gate acting on the target quantum bit can be determined as the associated node of the newly added node. From the nodes corresponding to the quantum bits affected by the temporary variables, determine the nodes with an associated relationship with the newly added nodes. Add the edges between the determined nodes (including the nodes with an associated relationship with the newly added nodes determined by the above two methods) and the newly added nodes, and the type of edge is related to the associated relationship. Exemplarily, on the basis of Figure 3, according to the adding method provided in the embodiment of the present application, the generated new topological map is shown in Figure 5. In this example, the topological map shown in Figure 3 is the current topological map, and the topological map shown in Figure 5 is a new topological map obtained by adding the nodes corresponding to the target quantum logic gate. From the perspective of execution timing, the CNOT gate represented by q2 ₁ and the CNOT gate represented by q0 ₂ are added between the CNOT gate represented by q2 ₂ . For example, the quantum logic gates associated with the target quantum bit in the two-bit quantum logic gates and multi-bit quantum logic gates in the initial quantum program can be determined, and correspondingly, the other quantum bits associated with the part of the quantum logic gates can represent the quantum bits affected by the temporary variables. For example, for any controlled quantum logic gate, the target bit and the control bit of the controlled quantum logic gate are associated with the controlled quantum logic gate.

When the execution order of some quantum logic gates in a quantum program cannot be changed, in order to ensure the correct execution order of quantum logic gates in the quantum circuit generated based on the topological graph, it is necessary to constrain the execution order of quantum logic gates by edge type in the topological graph. For example, as shown in Figure 6, q1 is the target quantum bit, and the symbol with a dotted line Indicates that there is a constraint relationship between the nodes, which means that the CNOT gate represented by q1 ₁ is executed first, and then the H gate represented by q0 ₂ is executed. When there is a constraint relationship in the topology, in order to achieve automatic cancellation of calculation, it is necessary to add a CNOT gate between the CNOT gate and the second H gate (i.e., the H gate represented by q0 ₂ ). After adding the node corresponding to the CNOT gate (i.e., q1 ₂ ), add the Side symbols of two H gates To ensure that the second H gate is executed after the added CNOT gate, the new topology can be shown in Figure 7.

In a possible implementation of the present application, generating a target quantum circuit based on the new topological graph includes:

According to the new topological diagram, the quantum logic gates, execution timing, and action relationships acting on each quantum bit are determined;

Compile the new topology back to the quantum circuit. First, determine the number of quantum bits based on the number of initial nodes. For each quantum bit, traverse the topology in turn to determine the quantum logic gates acting on the quantum bit, the execution sequence of the quantum logic gates, and the action relationship. Based on the execution sequence and the action relationship, act on the quantum bits in turn with the corresponding quantum logic gates, thereby obtaining the target quantum circuit. For example, after compiling FIG5, the generated quantum circuit diagram can be shown in FIG8. In FIG8, q[0] represents the quantum bit represented by q0 in FIG5, q[1] represents the quantum bit represented by q1 in FIG5, and q[2] represents the quantum bit represented by q2 in FIG5.

In a possible implementation of the present application, the method may further include:

If a separate quantum bit is allocated for each temporary variable, it will lead to a large consumption of quantum resources, and quantum resources are very precious. Therefore, the quantum bits can be reused after the life cycle of the temporary variable ends to achieve the purpose of saving resources. In general, the end of the function where the temporary variable is located can be regarded as the time point when its life cycle ends. Specifically, the memory management of temporary variables can be implemented through the global pool, which is a stack structure. When a temporary variable needs to allocate a quantum bit, the quantum bit is popped from the top of the stack as the target quantum bit. When the life cycle of the temporary variable ends, the quantum bit is recycled to the global pool. For example, the recycled quantum bit is added to the top of the stack.

Exemplarily, memory management of quantum bits through the global pool can be shown in Figure 9. The quantum bits allocated by the global pool for temporary variables are 10 quantum bits q0-q9, aux0-aux2 are all temporary variables, aux0 will call aux1 and aux2, when a variable needs to be allocated with a quantum bit, a quantum bit is popped from the top of the stack, and when the life cycle of the temporary variable ends, the quantum bits occupied by the temporary variable are put back into the stack.

In Figure 9, the main function is used to apply for bits for the temporary variable aux0. At this time, since the top of the global pool is quantum bit q0, quantum bit q0 is allocated to the temporary variable aux0. Then, function 1 can be called to apply for bits for the temporary variable aux1 through function 1. At this time, since the top of the global pool is quantum bit q1, quantum bit q1 is allocated to the temporary variable aux1. At the end of function 1, the quantum bit q1 allocated to the temporary variable aux1 is recovered and added to the top of the stack. Then, function 2 can be called to apply for bits for the temporary variable aux2 through function 2. At this time, since the top of the global pool is quantum bit q1, quantum bit q1 is allocated to the temporary variable aux2. At the end of function 2, the quantum bit q1 allocated to the temporary variable aux2 is recovered and added to the top of the stack. Furthermore, at the end of the main function, the quantum bit q0 allocated to the temporary variable aux0 is recovered and added to the top of the stack.

It can be seen that the embodiment of the present application first obtains the target temporary variable required for executing the initial quantum program; determines the target quantum bit according to the target temporary variable; then determines the target quantum logic gate that makes the final state of the target quantum bit |0> state based on the initial quantum program; finally, generates the target quantum circuit based on the initial quantum program and the target quantum logic gate. Through the initial quantum program, the quantum logic gate that makes the final state of the quantum bit corresponding to the temporary variable |0> state is determined and added to the corresponding position, thereby obtaining the final quantum circuit. When running the quantum circuit, the influence of the temporary variable addition on the calculation result is automatically eliminated, thereby reducing the possibility of errors in the calculation result.

The quantum generation method provided in the embodiment of the present application is applied to quantum computing scenarios with temporary variables, specifically, password cracking, artificial intelligence, biomedicine, financial engineering, aerospace and transportation, etc. In these scenarios, if there are temporary variables, the method provided in the embodiment of the present application can be used to eliminate the influence of temporary variables, reduce the possibility of errors in the calculation results, and promote the development of various fields.

Referring to FIG. 10 , FIG. 10 is a schematic diagram of the structure of a quantum circuit generation device provided in an embodiment of the present application, corresponding to the process shown in FIG. 2 , the device includes:

An acquisition module 1001 is used to obtain a target temporary variable required for executing an initial quantum program;

A first determination module 1002 is used to determine a target quantum bit according to the target temporary variable, wherein the initial state of the target quantum bit is a |0> state;

A second determination module 1003 is used to determine a target quantum logic gate that makes the final state of the target quantum bit a |0> state based on the initial quantum program;

The generating module 1004 is used to generate a target quantum circuit based on the initial quantum program and the target quantum logic gate.

In some possible implementations of the present application, the first determining module 1002 may be specifically used to:

From the pre-set quantum bits, an idle quantum bit is allocated to the target temporary variable as the target quantum bit.

In some possible implementations of the present application, the second determining module 1003 may include:

In some possible implementations of the present application, the first determining unit may be specifically configured to:

In some possible implementations of the present application, the generating module 1004 may be specifically used for:

Based on the new topological graph, a target quantum circuit is generated.

In some possible implementations of the present application, the generating module 1004 may also be specifically used for:

In some possible implementations of the present application, the device may further include:

It can be seen that the embodiment of the present application first obtains the target temporary variable required for executing the initial quantum program; determines the target quantum bit according to the target temporary variable; and then based on the initial quantum program, Determine the target quantum logic gate that makes the final state of the target quantum bit to be |0>state; finally, generate the target quantum circuit based on the initial quantum program and the target quantum logic gate. Through the initial quantum program, determine the quantum logic gate that makes the final state of the quantum bit corresponding to the temporary variable to be |0> state, and add it to the corresponding position, so as to obtain the final quantum circuit. When running the quantum circuit, the influence of the addition of the temporary variable on the calculation result is automatically eliminated, thereby reducing the possibility of errors in the calculation result.

An embodiment of the present application further provides a storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

Specifically, in this embodiment, the above storage medium may be configured to store a computer program for performing the following steps:

S201: Obtaining target temporary variables required for executing the initial quantum program;

S202: Determine a target quantum bit according to the target temporary variable, wherein the initial state of the target quantum bit is a |0> state;

S203: Based on the initial quantum program, determine a target quantum logic gate that makes the final state of the target quantum bit a |0> state;

An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

Specifically, the electronic device may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.

Specifically, in this embodiment, the processor may be configured to perform the following steps through a computer program:

S204: Generate a target quantum wire based on the initial quantum program and the target quantum logic gate road

The embodiment of the present application also proposes a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the steps in any of the above method embodiments.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

A quantum circuit generation method, characterized in that the method comprises:

Obtain the target temporary variables required to execute the initial quantum program;

Determine a target quantum bit according to the target temporary variable, wherein the initial state of the target quantum bit is a |0> state;

Based on the initial quantum program, determining a target quantum logic gate that makes the final state of the target quantum bit a |0> state;

Based on the initial quantum program and the target quantum logic gate, a target quantum circuit is generated.
The method according to claim 1, characterized in that determining the target quantum bit according to the target temporary variable comprises:

From the preset quantum bits, an idle quantum bit is allocated to the target temporary variable as the target quantum bit.
The method according to claim 1 or 2, characterized in that the step of determining, based on the initial quantum program, a target quantum logic gate that makes the final state of the target quantum bit a |0> state comprises:

Determining a quantum logic gate acting on the target quantum bit according to the initial quantum program;

Based on the determined quantum logic gate, a target quantum logic gate that makes the final state of the target quantum bit a |0> state is determined.
The method according to claim 3, characterized in that the step of determining the quantum logic gate acting on the target quantum bit according to the initial quantum program comprises:

Obtaining a topological graph containing the target quantum bit, wherein the topological graph is generated using the initial quantum program, the initial node represents the quantum bit, the other nodes represent the quantum logic gates, and the edges represent the association relationship between the nodes;

Based on the topological graph, a quantum logic gate acting on the target quantum bit is determined.
The method according to claim 4, characterized in that generating a target quantum circuit based on the initial quantum program and the target quantum logic gate comprises:

In the current topology graph, determine the adding position of the target quantum logic gate and add the corresponding node;

According to the association relationship in the current topology diagram, determine the node that has an association relationship with the newly added node;

Establishing edges between the determined nodes and the newly added nodes to determine a new topological graph;

Based on the new topological graph, a target quantum circuit is generated.
The method according to claim 5, characterized in that generating a target quantum circuit based on the new topological graph comprises:

Determine the quantum logic gate, execution sequence, and action relationship acting on each quantum bit according to the new topological diagram;

Based on the execution sequence and the action relationship, the determined quantum logic gates are sequentially applied to corresponding quantum bits to generate a target quantum circuit.
The method according to claim 2, characterized in that the method further comprises:

When the life cycle of the target temporary variable ends, the target quantum bit is released so that the target quantum bit can be reallocated.
A quantum circuit generation device, characterized in that the device comprises:

An acquisition module, used for obtaining target temporary variables required for executing an initial quantum program;

A first determination module is used to determine a target quantum bit according to the target temporary variable, wherein the initial state of the target quantum bit is a |0> state;

A second determination module is used to determine a target quantum logic gate that makes the final state of the target quantum bit a |0> state based on the initial quantum program;

A generation module is used to generate a target quantum circuit based on the initial quantum program and the target quantum logic gate.
A storage medium, characterized in that a computer program is stored in the storage medium, wherein the computer program is configured to implement the method described in any one of claims 1 to 7 when run.
An electronic device comprises a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to implement the method described in any one of claims 1 to 7.