CN115983392A - Method, device, medium and electronic device for determining quantum program mapping relation - Google Patents
Method, device, medium and electronic device for determining quantum program mapping relation Download PDFInfo
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Abstract
The invention discloses a method, a device, a medium and an electronic device for determining a quantum program mapping relation, wherein the method comprises the following steps: the method comprises the steps of obtaining a quantum program to be executed and a quantum chip topological structure, constructing a weighted undirected graph corresponding to the quantum program to be executed, determining a first parameter of each logic quantum bit in the quantum program to be executed according to the weighted undirected graph, obtaining a second parameter of each physical quantum bit in a quantum chip according to the quantum chip topological structure, and finally determining a mapping relation of the quantum program to be executed according to the first parameter, the second parameter and the fidelity of the quantum chip, so that the fidelity corresponding to the mapping relation of the quantum program to be executed is the highest, the problem of randomness of constructing the mapping relation of the quantum program to be executed is solved, the execution times of an algorithm are reduced, the execution performance is optimized, the optimal mapping of the quantum program to be executed can be determined, and the fidelity of the obtained mapping relation is high, and the quantum chip resource utilization is maximized.
Description
Technical Field
The invention belongs to the technical field of quantum computation, and particularly relates to a method, a device, a medium and an electronic device for determining a quantum program mapping relation.
Background
Quantum computers are physical devices that perform high-speed mathematical and logical operations, store and process quantum information in compliance with the laws of quantum mechanics. When a device processes and calculates quantum information and runs quantum algorithms, the device is a quantum computer. Quantum computers are a key technology under study because they have the ability to handle mathematical problems more efficiently than ordinary computers, for example, they can speed up the time to break RSA keys from hundreds of years to hours.
In a Noisy Intermediate-Scale Quantum computation (noise-Scale Quantum) stage, for a plurality of physical qubits on the same physical chip, the states of the physical qubits are unstable, and factors such as noise parameters of a two-bit Quantum logic gate and fading coherent time of the physical qubits interfere with effective utilization of the physical qubits, so that unknown influence is generated on the operation result of the whole Quantum circuit. For example, due to the different decoherence time of each physical qubit, if the depth of the quantum line in which the whole quantum chip can operate is limited because the decoherence time of a certain physical qubit is short, other physical qubit resources are inevitably wasted.
In the prior art, the optimal mapping line of the quantum program to be executed is determined, and usually the mapping relation of the quantum program is constructed randomly, but the random construction of the mapping relation has randomness, so that the actual effect of the algorithm cannot be guaranteed, and the algorithm can obtain a higher-quality mapping relation only through multiple times of random construction.
Based on this, how to determine the mapping relationship of the quantum program to be executed, reduce the execution times of the algorithm, and optimize the execution performance of the algorithm is a problem which needs to be solved urgently.
Disclosure of Invention
The invention aims to provide a quantum program mapping relation determining method, a quantum program mapping relation determining device, a quantum program mapping relation determining medium and an electronic device, aiming at solving the defects in the prior art, solving the problem of randomness existing in the construction of the quantum program mapping relation to be executed, and determining the optimal mapping line of the quantum program to be executed, so that the fidelity of the obtained mapping relation is high, and the resource utilization of a quantum chip is maximized.
One embodiment of the present application provides a method for determining a quantum program mapping relationship, where the method includes:
acquiring a quantum program to be executed and a quantum chip topological structure, wherein the topological structure is used for representing physical quantum bits in the quantum chip and a connection relation between the physical quantum bits;
constructing a weighted undirected graph corresponding to the quantum program to be executed;
determining a first parameter of each logic quantum bit in the quantum program to be executed according to the weighted undirected graph;
acquiring a second parameter of each physical quantum bit in the quantum chip according to the quantum chip topological structure;
and determining the mapping relation of the quantum program to be executed according to the first parameter, the second parameter and the fidelity of the quantum chip, so that the fidelity corresponding to the mapping relation of the quantum program to be executed is the highest.
Optionally, the fidelity of the quantum chip includes a double quantum logic gate fidelity between every two physical qubits in the quantum chip topology and a measurement fidelity corresponding to each physical qubit.
Optionally, the constructing a weighted undirected graph corresponding to the to-be-executed quantum program includes:
acquiring a quantum logic gate in the quantum program to be executed and a logic quantum bit operated by the quantum logic gate;
based on the quantum logic gate and the logic quantum bit operated by the quantum logic gate, constructing a weighted undirected graph corresponding to a quantum program to be executed, wherein the weighted undirected graph comprises: the weights of the vertexes, the undirected edges and the edges are used for representing the logic quantum bits operated by the quantum logic gates, the undirected edges are used for representing the quantum logic gates, and the weights of the edges are determined according to the number of the quantum logic gates operated by the same quantum bits.
Optionally, the determining, according to the weighted undirected graph, a first parameter of each logic qubit in the to-be-executed quantum program specifically includes:
and determining a first parameter of each logic quantum bit according to the degree of each vertex in the weighted undirected graph, wherein the degree is determined according to the sum of adjacent undirected edge weights of each vertex.
Optionally, the obtaining a second parameter of each physical qubit in the quantum chip according to the quantum chip topology includes:
determining the number of each physical quantum bit connection edge according to the quantum chip topological structure;
and determining a second parameter of each physical qubit according to the number of the connection edges of each physical qubit.
Optionally, the determining, according to the first parameter, the second parameter, and the fidelity of the quantum chip, a mapping relationship of the to-be-executed quantum program includes:
determining a first logic quantum bit in the quantum program to be executed according to the first parameter, wherein the first parameter value of the first logic quantum bit is maximum;
determining a first mapping relationship of the first logical qubit based on the second parameter and a fidelity of a quantum chip;
deleting the first logic quantum bit, and determining whether a second logic quantum bit exists in the quantum program to be executed, wherein a first parameter value of the second logic quantum bit is maximum;
and if the second logic quantum bit does not exist in the quantum program to be executed, obtaining the mapping relation of all the logic quantum bits determined by the quantum program to be executed.
Optionally, the method further includes:
if the second logic quantum bit exists in the quantum program to be executed, determining a second mapping relation of the second logic quantum bit based on the current second parameter and the fidelity of the quantum chip;
deleting the second logic quantum bit, updating the logic quantum bit in the quantum program to be executed, and returning to execute the step of determining whether the second logic quantum bit exists in the quantum program to be executed until the second logic quantum bit does not exist in the quantum program to be executed.
One embodiment of the present application provides an apparatus for determining a quantum program mapping relationship, the apparatus including:
the system comprises a first acquisition module, a second acquisition module and a third acquisition module, wherein the first acquisition module is used for acquiring a quantum program to be executed and a quantum chip topological structure, and the topological structure is used for representing physical quantum bits in a quantum chip and a connection relation between the physical quantum bits;
the construction module is used for constructing a weighted undirected graph corresponding to the quantum program to be executed;
a first determining module, configured to determine, according to the weighted undirected graph, a first parameter of each logical qubit in the to-be-executed quantum program;
the second acquisition module is used for acquiring a second parameter of each physical quantum bit in the quantum chip according to the quantum chip topological structure;
and the second determining module is used for determining the mapping relation of the to-be-executed quantum program according to the first parameter, the second parameter and the fidelity of the quantum chip, so that the fidelity corresponding to the mapping relation of the to-be-executed quantum program is the highest.
Optionally, the building module includes:
the acquisition unit is used for acquiring a quantum logic gate in the quantum program to be executed and a logic quantum bit operated by the quantum logic gate;
a constructing unit, configured to construct a weighted undirected graph corresponding to a to-be-executed quantum program based on the quantum logic gate and a logic qubit operated by the quantum logic gate, where the weighted undirected graph includes: the weights of the vertexes, the undirected edges and the edges are used for representing the logic quantum bits operated by the quantum logic gates, the undirected edges are used for representing the quantum logic gates, and the weights of the edges are determined according to the number of the quantum logic gates operated by the same quantum bits.
Optionally, the first determining module specifically includes:
a first determining unit, configured to determine a first parameter of each logical qubit according to a degree of each vertex in the weighted undirected graph, where the degree is determined according to a sum of adjacent undirected edge weights of each vertex.
Optionally, the second obtaining module includes:
a second determining unit, configured to determine, according to the quantum chip topology structure, the number of the connection edges of each physical qubit;
and a third determining unit, configured to determine a second parameter of each physical qubit according to the number of the connection edges of each physical qubit.
Optionally, the second determining module includes:
a fourth determining unit, configured to determine, according to the first parameter, a first logic qubit in the to-be-executed quantum program, where a first parameter value of the first logic qubit is maximum;
a fifth determining unit, configured to determine a first mapping relationship of the first logical qubit based on the second parameter and a fidelity of a quantum chip;
a sixth determining unit, configured to delete the first logic qubit and determine whether a second logic qubit exists in the to-be-executed quantum program, where a first parameter value of the second logic qubit is maximum;
a first determining unit, configured to obtain a mapping relationship of all logic qubits determined by the to-be-executed quantum program if the second logic qubit does not exist in the to-be-executed quantum program.
Optionally, the second determining module further includes:
a second determining unit, configured to determine, if the second logical qubit exists in the to-be-executed quantum program, a second mapping relationship of the second logical qubit based on the current second parameter and a fidelity of a quantum chip;
and the updating unit is used for deleting the second logic quantum bit, updating the logic quantum bit in the to-be-executed quantum program, and returning to execute the step of determining whether the second logic quantum bit exists in the to-be-executed quantum program until the second logic quantum bit does not exist in the to-be-executed quantum program.
A further embodiment of the application provides a storage medium having a computer program stored thereon, wherein the computer program is arranged to perform the method as described in any of the above when executed.
Yet another embodiment of the present application provides an electronic device comprising a memory having a computer program stored therein and a processor configured to execute the computer program to perform the method of any of the above.
Yet another embodiment of the present application provides a quantum computer operating system that implements determination of quantum program mapping relationships according to the method described in any of the above.
The application further provides a quantum computer, and the quantum computer comprises the quantum computer operating system.
Compared with the prior art, the method comprises the steps of firstly obtaining the quantum program to be executed and a quantum chip topological structure, constructing a weighted undirected graph corresponding to the quantum program to be executed, secondly determining a first parameter of each logic quantum bit in the quantum program to be executed according to the weighted undirected graph, thirdly obtaining a second parameter of each physical quantum bit in the quantum chip according to the quantum chip topological structure, and lastly determining the mapping relation of the quantum program to be executed according to the first parameter, the second parameter and the fidelity of the quantum chip, so that the fidelity corresponding to the mapping relation of the quantum program to be executed is highest, the problem of randomness in constructing the mapping relation of the quantum program to be executed is solved, the algorithm execution times are reduced, the execution performance is optimized, and the optimal initial mapping relation of the quantum program to be executed can be determined, so that the fidelity of the obtained mapping relation is high, and the quantum chip resource utilization is maximized.
Drawings
Fig. 1 is a block diagram of a hardware structure of a computer terminal of a method for determining a quantum program mapping relationship according to an embodiment of the present invention;
fig. 2 is a schematic flowchart of a method for determining a quantum program mapping relationship according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a topology structure of a physical qubit of a quantum chip according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a weighted undirected graph according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a quantum program mapping relationship determining apparatus according to an embodiment of the present invention.
Detailed Description
The embodiments described below with reference to the drawings are illustrative only and should not be construed as limiting the invention.
The embodiment of the invention firstly provides a method for determining a quantum program mapping relation, and the method can be applied to electronic equipment, such as a computer terminal, specifically a common computer, a quantum computer and the like.
This will be described in detail below by way of example as it would run on a computer terminal. Fig. 1 is a block diagram of a hardware structure of a computer terminal of a method for determining a quantum program mapping relationship according to an embodiment of the present invention. As shown in fig. 1, the computer terminal may include one or more (only one shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, and optionally, a transmission device 106 for communication functions and an input-output device 108. It will be understood by those skilled in the art that the structure shown in fig. 1 is only an illustration and is not intended to limit the structure of the computer terminal. For example, the computer terminal may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.
The memory 104 may be used to store software programs and modules of application software, such as program instructions/modules corresponding to the method for determining a quantum program mapping relationship in the embodiment of the present application, and the processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, implementing the above-mentioned method. The memory 104 may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory located remotely from the processor 102, which may be connected to a computer terminal over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission device 106 is used to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the computer terminal. In one example, the transmission device 106 includes a Network adapter (NIC) that can be connected to other Network devices through a base station to communicate with the internet. In one example, the transmission device 106 can be a Radio Frequency (RF) module, which is used to communicate with the internet in a wireless manner.
It should be noted that a true quantum computer is a hybrid structure, which includes two major components: one part is a classic computer which is responsible for executing classic calculation and control; the other part is quantum equipment which is responsible for running a quantum program to further realize quantum computation. The quantum program is a string of instruction sequences which can run on a quantum computer and are written by quantum languages such as Qrun languages, so that the support on the operation of a quantum logic gate is realized, and the quantum computation is finally realized. In particular, a quantum program is a sequence of instructions that operate quantum logic gates in a time sequence.
In practical applications, due to the limited development of quantum device hardware, quantum computation simulation is usually required to verify quantum algorithms, quantum applications, and the like. The quantum computing simulation is a process of realizing the simulation operation of a quantum program corresponding to a specific problem by means of a virtual architecture (namely a quantum virtual machine) built by resources of a common computer. In general, it is necessary to build quantum programs for a particular problem. The quantum program referred in the embodiment of the invention is a program written in a classical language for representing quantum bits and evolution thereof, wherein the quantum bits, quantum logic gates and the like related to quantum computation are all represented by corresponding classical codes.
A quantum circuit, which is an embodiment of a quantum program and also a weighing sub-logic circuit, is the most common general quantum computation model, and represents a circuit that operates on a quantum bit under an abstract concept, and the circuit includes the quantum bit, a circuit (timeline), and various quantum logic gates, and finally, a result is often read through a quantum measurement operation.
Unlike conventional circuits that are connected by metal lines to pass either voltage or current signals, in quantum circuits, the lines can be viewed as being connected by time, i.e., the state of a qubit evolves naturally over time, in the process being operated on as indicated by the hamiltonian until a logic gate is encountered.
The quantum program refers to the total quantum circuit, wherein the total number of the quantum bits in the total quantum circuit is the same as the total number of the quantum bits of the quantum program. It can be understood that: a quantum program may consist of quantum wires, measurement operations for quantum bits in the quantum wires, registers to hold measurement results, and control flow nodes (jump instructions), and a quantum wire may contain tens to hundreds or even thousands of quantum logic gate operations. The execution process of the quantum program is a process executed for all the quantum logic gates according to a certain time sequence. It should be noted that timing is the time sequence in which the single quantum logic gate is executed.
It should be noted that, in the classical calculation, the most basic unit is a bit, and the most basic control mode is a logic gate, and the purpose of controlling the circuit can be achieved through the combination of the logic gates. Similarly, the way qubits are handled is quantum logic gates. The quantum state can be evolved by using quantum logic gates, which are the basis for forming quantum circuits, including single-bit quantum logic gates, such as Hadamard gates (H gates, hadamard gates), pauli-X gates (X gates), pauli-Y gates (Y gates), pauli-Z gates (Z gates), RX gates, RY gates, RZ gates, and the like; multi-bit quantum logic gates such as CNOT gates, CR gates, iSWAP gates, toffoli gates, and the like. Quantum logic gates are typically represented using unitary matrices, which are not only matrix-form but also an operation and transformation. The function of a general quantum logic gate on a quantum state is calculated by multiplying a unitary matrix by a matrix corresponding to a quantum state right vector.
Quantum states, i.e. logical states of qubits, are represented in binary in quantum algorithms (or quantum programs), for example, a group of qubits is q0, q1, q2, representing 0 th, 1 st, and 2 nd qubits, and ordered from high to low as q2q1q0, the quantum states corresponding to the group of qubits are the superposition of the eigenstates corresponding to the group of qubits, and the eigenstates corresponding to the group of qubits have 2 qubit numbers to the power of the total number of qubits, i.e. 8 eigenstates (deterministic states): the method comprises the following steps of |000>, |001>, |010>, |011>, |100>, |101>, |110>, |111>, the bit of each eigen state corresponds to a qubit, for example, |000> state, 000 corresponds to q2q1q0 from high to low, and | is a dirac symbol.
Illustrating the logic state of a single qubit in terms of a single qubit
May be at |0>State, |1>State, |0>Sum of states |1>The superimposed state of states (indeterminate state) can be expressed in particular as @>
Where c and d are complex numbers representing the amplitude (magnitude of probability) of the quantum state, the square of the amplitude mode | c- 2 And | d |) 2 Respectively represent |0>State 1>The probability of state, | c- 2 +|d| 2 =1. In short, a quantum state is a superposition of the components of each eigenstate, and is in a uniquely determined eigenstate when the probability of the other eigenstate is 0.
Referring to fig. 2, fig. 2 is a schematic flowchart of a method for determining a quantum program mapping relationship according to an embodiment of the present invention.
The present embodiment provides an embodiment of a method for determining a quantum program mapping relationship, where the method for determining a quantum program mapping relationship includes:
s201: and acquiring a quantum program to be executed and a quantum chip topological structure, wherein the topological structure is used for representing physical quantum bits in the quantum chip and the connection relation between the physical quantum bits.
In particular, the quantum program to be executed is mainly composed of tens to hundreds or even thousands of quantum logic gates. The execution process of the quantum program is a process executed on all the quantum logic gates according to a certain time sequence, and it should be noted that the time sequence is a time sequence in which a single quantum logic gate is executed.
The quantum chip topological structure is used for representing the connection relation between physical quantum bits in the electronic equipment, and the number of the physical quantum bits contained in the topological structure is required to be more than or equal to the number of the logic quantum bits in the quantum program to be executed, so that the quantum chip accords with the execution condition of the quantum program. For the sake of convenience of distinction, the qubit structure in the quantum chip is generally referred to as a physical qubit, and the target bit operated on in the quantum line is referred to as a logical qubit. The mapping relationship between the logic qubits and the physical qubits refers to the relationship of "correspondence" of bits between the logic qubits and the physical qubits.
Illustratively, for a section of the quantum program to be executed CNOT (q [0], q [1 ]) < < CNOT (q [0], q [2 ]) < < CNOT (q [0], q [3 ]) < < CNOT (q [1], q [3 ]) < < CNOT (q [0], q [1 ]) <cnot (q [1], q [3 ]), logical qubits of operation are q [0], q [1], q [2], q [3], respectively, so that the number of physical qubits of the quantum chip that can be adapted to the section of the quantum program to be executed is at least 4.
Referring to fig. 3, fig. 3 is a schematic diagram of a topology structure of a physical qubit of a quantum chip provided in the present application, where the quantum chip includes 6 physical qubits, Q0, Q1, Q2, Q3, Q4, and Q5, and the 6 physical qubits can be coupled through capacitors, and only adjacent physical qubits have a coupling relationship. Wherein Q0 is connected to Q1 and Q3, Q4 is connected to Q1, Q3 and Q5, Q2 is connected to Q1, Q5, and Q5 is connected to Q2 and Q4.
S202: and constructing a weighted undirected graph corresponding to the quantum program to be executed.
Undirected graphs are widely used to represent driven dependencies between events, scheduling between tasks, and the like.
The weighted undirected graph can indicate the importance degree of an edge between vertexes of the undirected graph containing a certain factor or index relative to a certain event, represent the percentage of the certain factor or index, or emphasize the relative importance degree of the certain factor or index.
In a specific implementation, constructing a weighted undirected graph corresponding to a to-be-executed quantum program may include the following steps:
s2021: and acquiring a quantum logic gate in the quantum program to be executed and a logic quantum bit operated by the quantum logic gate.
In particular, a quantum program to be executed may be understood as a sequence of operations, which mainly includes quantum logic gates, qubits for quantum logic gate operations, measurement operations (measures), and the like.
Illustratively, for a section of the quantum program to be executed CNOT (q [0], q [1 ]) < < CNOT (q [0], q [2 ]) < < CNOT (q [0], q [3 ]) < < CNOT (q [1], q [3 ]) < < CNOT (q [0], q [1 ]) <cnot (q [1], q [3 ]), which contain 7 quantum logic gates in total, the logical qubits of the operation are q [0], q [1], q [2], q [3], respectively.
S2022: based on the quantum logic gate and the logic quantum bit operated by the quantum logic gate, constructing a weighted undirected graph corresponding to a quantum program to be executed, wherein the weighted undirected graph comprises: the weights of the vertex, the undirected edge and the edge are determined according to the number of quantum logic gates operating the same quantum bit, wherein the vertex is used for representing the logic quantum bit of the quantum logic gate operation, the undirected edge is used for representing the quantum logic gate, and the weight of the edge is determined according to the number of the quantum logic gates operating the same quantum bit.
Illustratively, based on the quantum program to be executed, the logical qubits of the operation are q [0], q [1], q [2], and q [3], so that the weighted undirected graph corresponding to the quantum program to be executed has 4 vertexes; the quantum program to be executed has CNOT (q 0, q 1), CNOT (q 0, q 2), CNOT (q 0, q 3), CNOT (q 1, q 3), CNOT (q 0, q 1), CNOT (q 1, q 3) 7 quantum logic gates, wherein, the quantum logic gates operating the same quantum bit are 3 CNOT (q 0, q 1), 2 CNOT (q 1, q 3), CNOT (q 0, q 2) and CNOT (q 0, q 3) respectively 1. Therefore, 4 non-directional edges and their corresponding weights can be obtained, which are: a non-directional edge between q0 and q1, the weight of the edge is 3; a non-directional edge between q0 and q2, the weight of the edge is 1; a non-directional edge between q0 and q 3, the weight of the edge is 1; and the weight of the side between q1 and q 3 is 2. Thus, a schematic diagram of a weighted undirected graph as shown in fig. 4 is obtained.
S203: and determining a first parameter of each logic quantum bit in the quantum program to be executed according to the weighted undirected graph.
Specifically, a first parameter of each logic qubit is determined according to a degree of each vertex in the weighted undirected graph, wherein the degree is determined according to a sum of adjacent undirected edge weights of each vertex.
Illustratively, as shown in FIG. 4, there are 4 vertices in the weighted undirected graph, vertices q [0], q [1], q [2], and q [3], respectively. The adjacent non-directional sides of the vertex q [0] have three, which are respectively: a non-directional edge between q0 and q1, having a weight of 3; a non-directional edge between q0 and q2, with a weight of 1; the weight of the non-directional edge between q0 and q 3 is 1. Therefore, the first parameter value of the vertex q [0] is the sum of the weights of the three adjacent undirected edges of the vertex q [0] is 5, and similarly, the first parameter value 5 of the vertex q [1], the first parameter value 1 of the vertex q [2], and the first parameter value 3 of the vertex q [3] are obtained respectively.
S204: and acquiring a second parameter of each physical quantum bit in the quantum chip according to the topological structure of the quantum chip.
Specifically, in the prior art, the quantum chip topology structure may be a one-dimensional chain structure, that is, all physical quantum bits are on one line; it is also possible to present a two-dimensional chain structure, for example a quantum chip topology as shown in fig. 3, i.e. a two-dimensional chain structure.
Obtaining a second parameter of each physical qubit in the quantum chip may comprise:
determining the number of each physical quantum bit connection edge according to the quantum chip topological structure;
and determining a second parameter of each physical qubit according to the number of the connection edges of each physical qubit.
Illustratively, according to the quantum chip topology shown in fig. 3, the relationship of each physical qubit connection edge in the quantum chip is as follows: q < 0> is connected to Q < 1> and Q < 3 >, Q < 4 > is connected to Q < 1>, Q < 3 > and Q < 5 >, Q < 2 > is connected to Q < 1>, Q < 5 >, and Q < 5 > is connected to Q < 2 > and Q < 4 >, whereby the second parameter value of the physical quantum bit Q < 0> is 2, the second parameter value of Q < 1> is 3, the second parameter value of Q < 2 > is 2, the second parameter value of Q < 3 > is 2, the second parameter value of Q < 4 > is 3, and the second parameter value of Q < 5 > is 2.
S205: and determining the mapping relation of the quantum program to be executed according to the first parameter, the second parameter and the fidelity of the quantum chip, so that the fidelity corresponding to the mapping relation of the quantum program to be executed is the highest.
Specifically, the fidelity of the quantum chip includes the fidelity of a dual quantum logic gate between every two physical qubits in the quantum chip topology and the corresponding measurement fidelity of each physical qubit.
Fidelity is the degree of similarity that characterizes the output and reproduction of input signals of electronic equipment, and the higher the fidelity is, the more realistic the sound or the image output by the electronic equipment is. In a quantum chip, the higher the fidelity is, the smaller the noise is, and the smaller the measurement error obtained after running a quantum program is, the closer to the expected execution result is.
Illustratively, referring to fig. 3, fig. 3 is a schematic diagram of a topology of physical qubits in a quantum chip, where the quantum chip includes 6 physical qubits, and measurement fidelity corresponding to Q0, Q1, Q2, Q3, Q4, and Q5 are 0.95, 0.94, 0.93, 0.92, 0.91, and 0.90, respectively.
The method for obtaining the fidelity of the double quantum logic gate between every two physical quantum bits in the quantum chip topological structure specifically comprises the following steps: for physical qubits that can be mapped directly to a dual quantum logic gate with a fidelity that corresponds to the fidelity of the corresponding dual quantum logic gate, for example, one can measure directly the fidelity of the dual quantum logic gate between Q [0] and Q [1] as 0.9, the fidelity of the dual quantum logic gate between Q [0] and Q [3] as 0.9, the fidelity of the dual quantum logic gate between Q [3] and Q [4] as 0.95, the fidelity of the dual quantum logic gate between Q [4] and Q [1] as 0.85, the fidelity of the dual quantum logic gate between Q [1] and Q [2] as 0.8, the fidelity of the dual quantum logic gate between Q [2] and Q [5] as 0.75, and the fidelity of the dual quantum logic gate between Q [4] and Q [5] as 0.7; for the physical quantum bits which cannot be directly mapped to the double-quantum logic gate, the SWAP quantum logic gate is needed to be used for moving the physical quantum bits which cannot be directly mapped to the adjacent position, and then the fidelity of the corresponding double-quantum logic gate is calculated.
Illustratively, for physical qubits Q [0] and Q [1] in a quantum chip topology, CNOT dual-quantum logic gates can be directly mapped, i.e., the fidelity of the dual-quantum logic gates between Q [0] and Q [1] is 0.9; if CNOT dual-quantum logic gates are mapped on the physical quantum bits Q0, Q2, optionally, the paths for obtaining the fidelity of the physical quantum bits Q0, Q2 may be inserting SWAP (Q0, Q1) and CNOT (Q1, Q2), and the fidelity of the SWAP (Q0, Q1) dual-quantum logic gates is the third power of the fidelity of the corresponding CNOT (Q0, Q1), so that the fidelity of the corresponding dual-quantum logic gates of SWAP (Q0, Q1) and CNOT (Q1, Q2) is 0.5832 (0.9 x 0.8). Similarly, if CNOT dual-quantum logic gates are mapped onto physical qubits Q0, Q4, the paths for obtaining the fidelity of physical qubits Q0, Q4 may be SWAP (Q0, Q3) and CNOT (Q3, Q4), so that the fidelity of the dual-quantum logic gates corresponding to CNOT (Q0, Q4) is 0.69255 (0.9 × 0.9.0.95).
According to the above method, taking CNOT dual-quantum logic gate as an example, the following table 1 is a fidelity statistical table of CNOT dual-quantum logic gate applied between quantum bits.
Table 1: applied CNOT double-quantum logic gate fidelity statistical table between quantum bits
Determining the mapping relationship of the to-be-executed quantum program according to the first parameter, the second parameter and the fidelity of the quantum chip may include:
step 1: and determining a first logic quantum bit in the quantum program to be executed according to the first parameter, wherein the value of the first parameter of the first logic quantum bit is maximum.
Specifically, according to fig. 4, a first association container storing the weighted undirected graph vertex and the first parameter is constructed. Alternatively, the first association container may be a storage container of a Standard Template Library (STL), which can provide one-to-one data processing capability.
Storing the weighted undirected graph vertex (logic quantum bit) and the first parameter into a first associated container, wherein the storage information in the first associated container is as follows: q [0]:5, q2 [1]:5, q 2: 1, q2 [3]:3.
and traversing the storage information in the first association container, and determining a first logic quantum bit in the quantum program to be executed, wherein the first parameter value of the first logic quantum bit is the largest.
Specifically, a first parameter value of a logic quantum bit q [0] is 5, a first parameter value of a logic quantum bit q [1] is 5, a first parameter value of a logic quantum bit q [2] is 1, a first parameter value of a logic quantum bit q [3] is 3, and a mapping sequence of the logic quantum bits in the quantum program to be executed is sequentially determined according to the first parameter values.
At this time, the first parameter values of the logic qubit q [0] and the logic qubit q [1] are the same, so that either the logic qubit q [0] or the logic qubit q [1] can be mapped preferentially, and the finally obtained mapping relationship result is not greatly influenced.
Step 2: determining a first mapping relationship for the first logical qubit based on the second parameter and a fidelity of a quantum chip.
Optionally, when the first logical qubit Q [0] is preferentially processed, the physical qubit with the highest second parameter is obtained, that is, the physical qubits Q [1] and Q [4], and the second parameter values of both the physical qubits Q [1] and Q [4] are 3, and meanwhile, since the measurement fidelity of Q [1] is greater than that of Q [4], the first logical qubit Q [0] is mapped to the physical qubit Q [1], and then the first mapping relationship Q [0] - -Q [1] of the first logical qubit Q [0] can be determined.
And step 3: deleting the first logic quantum bit, and determining whether a second logic quantum bit exists in the to-be-executed quantum program, wherein the first parameter value of the second logic quantum bit is the largest.
Illustratively, deleting the first logical qubit q [0] in the first associated container to obtain a second associated container, where the storage information in the second associated container is: q [1]:5, q 2: 1, q 2]: 3.
and determining whether a second logical qubit exists in a current second association container, wherein the second logical qubit has a largest value of the first parameter in the second association container.
And if the second logic quantum bit exists in the to-be-executed quantum program, determining a second mapping relation of the second logic quantum bit based on the current second parameter and the fidelity of the quantum chip.
Specifically, at this point, the second logical qubit q [1]]The first parameter value of (2) is maximum, and the physical quantum bit with the highest fidelity in the current quantum chip is selected for mapping, because q [0]]Is mapped and due to Q [1] in the quantum chip topology]Has been mapped, so needs to be at Q [0]]、Q[2]、Q[3]、Q[4]、Q[5]Finding out the physical quantum bit with the highest fidelity, considering the whole fidelity of the line, and obtaining the following components according to a fidelity calculation method:
the calculation results are shown in table 2 below.
Table 2: current quantum chip fidelity statistical table
As can be seen from the above table,
is highest and is->
Thus the second logical qubit q [1]]Is q [1]]--Q[0]。
Deleting the second logic quantum bit, updating the logic quantum bit in the to-be-executed quantum program, and returning to execute the step of determining whether the second logic quantum bit exists in the to-be-executed quantum program until the second logic quantum bit does not exist in the to-be-executed quantum program.
Following the above example, the second logical qubit q [1] is deleted, and the logical qubit in the to-be-executed quantum program is updated, where the storage information in the second associative container is updated as follows: q [2]:1, q2 [3]:3.
at this time, a second logic quantum bit q [3] exists in the quantum program to be executed, and a second mapping relation of the current second logic quantum bit is determined based on the second logic quantum bit q [3], the current second parameter and the fidelity of the quantum chip.
Specifically, at this point, the second logical qubit q [3]]The first parameter value of (2) is maximum, and the physical quantum bit with highest fidelity in the current quantum chip is selected for mapping, because q0]、q[1]Is mapped and due to Q [0] in the quantum chip topology]、Q[1]Has been mapped, so needs to be at Q [2]]、Q[3]、Q[4]、Q[5]And finding the physical quantum bit with the highest fidelity, considering the overall fidelity of the line, and obtaining the following result according to a fidelity calculation method:
the calculation results are shown in table 3 below.
Table 3: current quantum chip fidelity statistical table
As can be seen from the above table,
is highest and is->
So that the second logical qubit q [3] is now present]Is q [3]]--Q[4]。
According to the method, the current second logic quantum bit q [3] is continuously deleted, the logic quantum bit in the quantum program to be executed is updated, and the step of determining whether the second logic quantum bit exists in the quantum program to be executed is returned to be executed.
Following the above example, deleting the current second logic qubit q [3], updating the logic qubit in the to-be-executed quantum program, where the storage information in the second associative container is updated as follows: q [2]:1.
at this time, a second logic quantum bit q [2] exists in the quantum program to be executed, and a second mapping relation of the current second logic quantum bit is determined based on the second logic quantum bit q [2], the current second parameter and the fidelity of the quantum chip.
Specifically, at this time, the second logical qubit q [2]]The first parameter value of (2) is maximum, and the physical quantum bit with the highest fidelity in the current quantum chip is selected for mapping, because q [0]]、q[1]、q[3]Is mapped and due to Q [0] in the quantum chip topology]、Q[1]、Q[4]Has been mapped, so needs to be at Q [2]]、Q[3]、Q[5]Finding out the physical quantum bit with the highest fidelity, considering the whole fidelity of the line, and obtaining the following components according to a fidelity calculation method:
the calculation results are shown in table 4 below.
Table 4: current quantum chip fidelity statistical table
As can be seen from the above table,
is highest and is->
So that the second logical qubit q [2] is now present]Is q2]--Q[2]。
And 4, step 4: and if the second logic quantum bit does not exist in the quantum program to be executed, obtaining the mapping relation of all the logic quantum bits determined by the quantum program to be executed.
When a second logic quantum bit does not exist in the to-be-executed quantum program, that is, when the information stored in the current second association container is empty, obtaining the mapping relations of all logic quantum bits determined by the to-be-executed quantum program, and arranging the mapping relations determined by the to-be-executed quantum program determined in sequence according to a generation sequence to obtain the initial mapping relation of the to-be-executed quantum program: q < 0> - -Q < 1>, Q < 1> - -Q < 0>, Q < 3 > - -Q < 4 >, and Q < 2 > - -Q < 2 >.
It should be noted that the quantum program to be executed may include a single-bit quantum logic gate, a two-bit quantum logic gate, and a multi-bit quantum logic gate, but before determining the corresponding weighted undirected graph of the quantum program to be executed, the multi-bit quantum logic gate needs to be first converted into a combination of the single-bit quantum logic gate and the two-bit quantum logic gate. Because the single-bit quantum logic gate can directly map the logic quantum bit to the physical quantum bit, the single-bit quantum logic gate obtained after conversion and the single-quantum logic gate existing in the quantum program to be executed before conversion can be deleted (without influencing mapping relation), and then the weighted undirected graph corresponding to the quantum program to be executed is constructed based on the two-bit quantum logic gate obtained after conversion and the two-bit quantum logic gate existing in the quantum program to be executed before conversion. For convenience of description, only one segment of the quantum program to be executed containing the two-bit quantum logic gate is taken as an example.
It can be seen that, compared with the prior art, the method and the device for determining the mapping relationship of the quantum program to be executed have the advantages that firstly, the quantum program to be executed and the topological structure of the quantum chip are obtained, the weighted undirected graph corresponding to the quantum program to be executed is constructed, secondly, the first parameter of each logic quantum bit in the quantum program to be executed is determined according to the weighted undirected graph, secondly, the second parameter of each physical quantum bit in the quantum chip is obtained according to the topological structure of the quantum chip, and finally, the mapping relationship of the quantum program to be executed is determined according to the first parameter, the second parameter and the fidelity of the quantum chip, so that the fidelity corresponding to the mapping relationship of the quantum program to be executed is the highest, the problem of constructing the randomness of the mapping relationship of the quantum program to be executed is solved, the algorithm execution times are reduced, the execution performance is optimized, and the optimal initial mapping relationship of the quantum program to be executed can be determined, so that the fidelity of the obtained mapping relationship is high and the utilization of quantum chip resources is maximized.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a quantum program mapping relationship determining apparatus according to an embodiment of the present invention, and corresponding to the flow shown in fig. 2, the apparatus may include:
a first obtaining module 501, configured to obtain a quantum program to be executed and a quantum chip topology, where the topology is used to represent physical qubits in the quantum chip and a connection relationship between the physical qubits;
a constructing module 502, configured to construct a weighted undirected graph corresponding to a to-be-executed quantum program;
a first determining module 503, configured to determine, according to the weighted undirected graph, a first parameter of each logical qubit in the to-be-executed quantum program;
a second obtaining module 504, configured to obtain a second parameter of each physical qubit in the quantum chip according to the quantum chip topology;
a second determining module 505, configured to determine, according to the first parameter, the second parameter, and the fidelity of the quantum chip, a mapping relationship of the to-be-executed quantum program, so that the fidelity corresponding to the mapping relationship of the to-be-executed quantum program is the highest.
Specifically, the building module includes:
the acquisition unit is used for acquiring a quantum logic gate in the quantum program to be executed and a logic quantum bit operated by the quantum logic gate;
a constructing unit, configured to construct a weighted undirected graph corresponding to a to-be-executed quantum program based on the quantum logic gate and a logic qubit operated by the quantum logic gate, where the weighted undirected graph includes: the weights of the vertex, the undirected edge and the edge are determined according to the number of quantum logic gates operating the same quantum bit, wherein the vertex is used for representing the logic quantum bit of the quantum logic gate operation, the undirected edge is used for representing the quantum logic gate, and the weight of the edge is determined according to the number of the quantum logic gates operating the same quantum bit.
Specifically, the first determining module specifically includes:
a first determining unit, configured to determine a first parameter of each logical qubit according to a degree of each vertex in the weighted undirected graph, where the degree is determined according to a sum of adjacent undirected edge weights of each vertex.
Specifically, the second obtaining module includes:
a second determining unit, configured to determine, according to the quantum chip topology, the number of each physical qubit connection edge;
and a third determining unit, configured to determine a second parameter of each physical qubit according to the number of the connection edges of each physical qubit.
Specifically, the second determining module includes:
a fourth determining unit, configured to determine, according to the first parameter, a first logic qubit in the to-be-executed quantum program, where a first parameter value of the first logic qubit is maximum;
a fifth determining unit, configured to determine a first mapping relationship of the first logical qubit based on the second parameter and a fidelity of a quantum chip;
a sixth determining unit, configured to delete the first logic qubit and determine whether a second logic qubit exists in the to-be-executed quantum program, where a first parameter value of the second logic qubit is maximum;
a first determining unit, configured to obtain a mapping relationship of all logic qubits determined by the to-be-executed quantum program if the second logic qubit does not exist in the to-be-executed quantum program.
Specifically, the second determining module further includes:
a second determining unit, configured to determine, if the second logic qubit exists in the to-be-executed quantum program, a second mapping relationship of the second logic qubit based on the current second parameter and the fidelity of the quantum chip;
and the updating unit is used for deleting the second logic quantum bit, updating the logic quantum bit in the to-be-executed quantum program, and returning to execute the step of determining whether the second logic quantum bit exists in the to-be-executed quantum program until the second logic quantum bit does not exist in the to-be-executed quantum program.
Compared with the prior art, the method includes the steps of firstly obtaining a quantum program to be executed and a quantum chip topological structure, constructing a weighted undirected graph corresponding to the quantum program to be executed, secondly determining a first parameter of each logic quantum bit in the quantum program to be executed according to the weighted undirected graph, thirdly obtaining a second parameter of each physical quantum bit in the quantum chip according to the quantum chip topological structure, and lastly determining the mapping relation of the quantum program to be executed according to the first parameter, the second parameter and the fidelity of the quantum chip, so that the fidelity corresponding to the mapping relation of the quantum program to be executed is highest, the problem of randomness of the mapping relation of the quantum program to be executed is solved, the algorithm execution times are reduced, the execution performance is optimized, and the optimal initial mapping relation of the quantum program to be executed can be determined, so that the fidelity of the obtained mapping relation is high, and the quantum chip resource utilization is maximized.
An embodiment of the present invention further provides a storage medium, where a computer program is stored, where the computer program is configured to execute the steps in any one of the method embodiments described above when the computer program is run.
Specifically, in the present embodiment, the storage medium may be configured to store a computer program for executing the steps of:
s201: acquiring a quantum program to be executed and a quantum chip topological structure, wherein the topological structure is used for representing physical quantum bits in the quantum chip and a connection relation between the physical quantum bits;
s202: constructing a weighted undirected graph corresponding to the quantum program to be executed;
s203: determining a first parameter of each logic quantum bit in the quantum program to be executed according to the weighted undirected graph;
s204: acquiring a second parameter of each physical quantum bit in the quantum chip according to the quantum chip topological structure;
s205: and determining the mapping relation of the quantum program to be executed according to the first parameter, the second parameter and the fidelity of the quantum chip, so that the fidelity corresponding to the mapping relation of the quantum program to be executed is the highest.
Specifically, in this embodiment, the storage medium may include, but is not limited to: various media capable of storing computer programs, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.
An embodiment of the present invention further provides an electronic device, which includes a memory and a processor, where the memory stores a computer program, and the processor is configured to execute the computer program to perform the steps in any one of the method embodiments described above.
Specifically, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.
Specifically, in this embodiment, the processor may be configured to execute the following steps by a computer program:
s201: acquiring a quantum program to be executed and a quantum chip topological structure, wherein the topological structure is used for representing physical quantum bits in the quantum chip and a connection relation between the physical quantum bits;
s202: constructing a weighted undirected graph corresponding to the quantum program to be executed;
s203: determining a first parameter of each logic quantum bit in the quantum program to be executed according to the weighted undirected graph;
s204: acquiring a second parameter of each physical quantum bit in the quantum chip according to the quantum chip topological structure;
s205: and determining the mapping relation of the quantum program to be executed according to the first parameter, the second parameter and the fidelity of the quantum chip, so that the fidelity corresponding to the mapping relation of the quantum program to be executed is the highest.
The embodiment of the invention also provides a quantum computer operating system, and the quantum computer operating system realizes the determination of the quantum program mapping relation according to any one of the method embodiments provided in the embodiment of the invention.
The embodiment of the application also provides a quantum computer, which comprises the quantum computer operating system.
The construction, features and functions of the present invention are described in detail in the embodiments illustrated in the drawings, which are only preferred embodiments of the present invention, but the present invention is not limited by the drawings, and all equivalent embodiments modified or changed according to the idea of the present invention should fall within the protection scope of the present invention without departing from the spirit of the present invention covered by the description and the drawings.
Claims (12)
1. A method for determining quantum program mapping relation is characterized by comprising the following steps:
acquiring a quantum program to be executed and a quantum chip topological structure, wherein the topological structure is used for representing physical quantum bits in the quantum chip and the connection relation between the physical quantum bits;
constructing a weighted undirected graph corresponding to the quantum program to be executed;
determining a first parameter of each logic quantum bit in the quantum program to be executed according to the weighted undirected graph;
acquiring a second parameter of each physical quantum bit in the quantum chip according to the topological structure of the quantum chip;
and determining the mapping relation of the quantum program to be executed according to the first parameter, the second parameter and the fidelity of the quantum chip, so that the fidelity corresponding to the mapping relation of the quantum program to be executed is the highest.
2. The method of claim 1, wherein the fidelity of the quantum chip comprises a double quantum logic gate fidelity between every two physical qubits in the quantum chip topology and a corresponding measured fidelity for each physical qubit.
3. The method according to claim 2, wherein the constructing a weighted undirected graph corresponding to the quantum program to be executed comprises:
acquiring a quantum logic gate in the quantum program to be executed and a logic quantum bit operated by the quantum logic gate;
based on the quantum logic gate and the logic quantum bit operated by the quantum logic gate, constructing a weighted undirected graph corresponding to a quantum program to be executed, wherein the weighted undirected graph comprises: the weights of the vertex, the undirected edge and the edge are determined according to the number of quantum logic gates operating the same quantum bit, wherein the vertex is used for representing the logic quantum bit of the quantum logic gate operation, the undirected edge is used for representing the quantum logic gate, and the weight of the edge is determined according to the number of the quantum logic gates operating the same quantum bit.
4. The method according to claim 3, wherein the determining, according to the weighted undirected graph, a first parameter of each logical qubit in the to-be-executed quantum program specifically includes:
and determining a first parameter of each logic quantum bit according to the degree of each vertex in the weighted undirected graph, wherein the degree is determined according to the sum of adjacent undirected edge weights of each vertex.
5. The method of claim 4, wherein obtaining the second parameter of each physical qubit in the quantum chip according to the quantum chip topology comprises:
determining the number of each physical quantum bit connection edge according to the quantum chip topological structure;
and determining a second parameter of each physical qubit according to the number of the connection edges of each physical qubit.
6. The method of claim 5, wherein determining the mapping relationship of the quantum program to be executed according to the first parameter, the second parameter and the fidelity of the quantum chip comprises:
determining a first logic quantum bit in the quantum program to be executed according to the first parameter, wherein the value of a first parameter of the first logic quantum bit is maximum;
determining a first mapping relationship of the first logical qubit based on the second parameter and a fidelity of a quantum chip;
deleting the first logic quantum bit, and determining whether a second logic quantum bit exists in the quantum program to be executed, wherein a first parameter value of the second logic quantum bit is maximum;
and if the second logic quantum bit does not exist in the quantum program to be executed, obtaining the mapping relation of all the logic quantum bits determined by the quantum program to be executed.
7. The method of claim 6, further comprising:
if the second logic quantum bit exists in the quantum program to be executed, determining a second mapping relation of the second logic quantum bit based on the current second parameter and the fidelity of the quantum chip;
deleting the second logic quantum bit, updating the logic quantum bit in the to-be-executed quantum program, and returning to execute the step of determining whether the second logic quantum bit exists in the to-be-executed quantum program until the second logic quantum bit does not exist in the to-be-executed quantum program.
8. An apparatus for determining a quantum program mapping relationship, the apparatus comprising:
the system comprises a first acquisition module, a second acquisition module and a third acquisition module, wherein the first acquisition module is used for acquiring a quantum program to be executed and a quantum chip topological structure, and the topological structure is used for representing physical quantum bits in a quantum chip and a connection relation between the physical quantum bits;
the construction module is used for constructing a weighted undirected graph corresponding to the quantum program to be executed;
a first determining module, configured to determine, according to the weighted undirected graph, a first parameter of each logical qubit in the to-be-executed quantum program;
the second acquisition module is used for acquiring a second parameter of each physical quantum bit in the quantum chip according to the quantum chip topological structure;
and the second determining module is used for determining the mapping relation of the to-be-executed quantum program according to the first parameter, the second parameter and the fidelity of the quantum chip, so that the fidelity corresponding to the mapping relation of the to-be-executed quantum program is the highest.
9. A storage medium, in which a computer program is stored, wherein the computer program is arranged to perform the method of any of claims 1 to 7 when executed.
10. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and wherein the processor is arranged to execute the computer program to perform the method of any of claims 1 to 7.
11. A quantum computer operating system, wherein the quantum computer operating system implements determination of quantum program mapping relationships according to the method of any one of claims 1 to 7.
12. A quantum computer comprising the quantum computer operating system of claim 11.
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