CN115829047A

CN115829047A - Method and device for determining final mapping of quantum program and quantum computer

Info

Publication number: CN115829047A
Application number: CN202111086091.1A
Authority: CN
Inventors: 窦猛汉; 方圆; 赵东一; 王晶
Original assignee: Origin Quantum Computing Technology Co Ltd
Current assignee: Origin Quantum Computing Technology Co Ltd
Priority date: 2021-09-16
Filing date: 2021-09-16
Publication date: 2023-03-21

Abstract

The invention discloses a method and a device for determining quantum program final mapping and a quantum computer, wherein the method comprises the following steps: the method comprises the steps of obtaining a directed acyclic graph of a quantum program, determining a maximum subgraph set of the quantum program and an isomorphic subgraph set corresponding to the maximum subgraph according to the directed acyclic graph of the quantum program, respectively determining the cost of each isomorphic subgraph in the isomorphic subgraph set mapping to a quantum chip topological structure, and determining the final mapping of the quantum program to be executed according to the cost of each isomorphic subgraph mapping to the quantum chip topological structure, so that the final mapping cost is the lowest, the problem that the whole quantum circuit is affected due to a single physical bit factor is solved, the final mapping circuit of the quantum chip topological structure can also be determined, and the resource utilization of the whole quantum chip is maximized.

Description

Method and device for determining final mapping of quantum program and quantum computer

Technical Field

The invention belongs to the technical field of quantum computation, and particularly relates to a method and a device for determining quantum program final mapping and a quantum computer.

Background

Quantum computers are physical devices that perform high-speed mathematical and logical operations, store and process quantum information in compliance with the laws of quantum mechanics. When a device processes and calculates quantum information and runs quantum algorithms, the device is a quantum computer. Quantum computers are a key technology under study because they have the ability to handle mathematical problems more efficiently than ordinary computers, for example, they can speed up the time to break RSA keys from hundreds of years to hours.

In a noise Intermediate-Scale Quantum computation (noise-Scale Quantum) stage, for a plurality of physical bits on the same physical chip, the states of the physical bits are unstable, and factors such as operation noise of a two-bit Quantum logic gate, measurement noise, and fading coherent time of the physical bits all interfere with effective utilization of the physical bits, thereby generating unknown influence on the operation result of the whole Quantum circuit.

For example, due to the different decoherence time of each physical bit, if the decoherence time of a certain physical bit is short and the operable depth of the quantum line of the whole quantum chip is limited, other physical bit resources are inevitably wasted. Therefore, how to determine the final mapping line of the quantum program to be executed so as to reduce the influence of a single physical bit on the whole quantum circuit and maximize the resource utilization of the whole quantum chip is a problem which needs to be solved urgently.

Disclosure of Invention

The invention aims to provide a quantum program final mapping determining method, a quantum program final mapping determining device and a quantum computer, aiming at solving the defects in the prior art, solving the problem that the whole quantum circuit is influenced by a single physical bit factor, and determining the quantum program final mapping circuit so as to maximize the resource utilization of the whole quantum chip.

One embodiment of the present application provides a method for determining a quantum program final mapping, where the method includes:

acquiring a directed acyclic graph of a quantum program to be executed;

determining a maximum subgraph set of the quantum program to be executed and a isomorphic subgraph set corresponding to the maximum subgraph according to the directed acyclic graph of the quantum program to be executed, wherein the isomorphic subgraph set is a logic bit-physical bit initial mapping relation graph set obtained by the maximum subgraph according to the topological structure of a quantum chip;

respectively determining the cost of each isomorphic subgraph in the set of isomorphic subgraphs mapping to the quantum chip topology;

and determining the final mapping of the quantum program to be executed according to the cost of mapping each isomorphic subgraph to the quantum chip topological structure, so that the cost of the final mapping is the lowest.

Optionally, the obtaining a directed acyclic graph of a to-be-executed quantum program includes:

acquiring nodes in a quantum program to be executed;

determining an incidence relation between the nodes according to the quantum bits of the node operation;

and generating a directed acyclic graph corresponding to the quantum program to be executed according to the nodes and the incidence relation among the nodes, wherein the vertexes in the directed acyclic graph represent the nodes, the edges in the directed acyclic graph represent the incidence relation among the nodes, and the directions of the edges represent the executed time sequence relation of the nodes corresponding to the vertexes connected with the edges.

Optionally, the determining, according to the directed acyclic graph of the quantum program to be executed, the maximum subgraph set of the quantum program to be executed and the isomorphic subgraph set corresponding to the maximum subgraph includes:

traversing the directed acyclic graph of the quantum program to be executed to obtain a maximum subgraph set, wherein the maximum subgraph set comprises N maximum subgraphs, and N is an integer greater than or equal to 1;

and determining isomorphic subgraphs of the N maximum subgraphs in a topological structure of a quantum chip to obtain N isomorphic subgraph sets, wherein the N isomorphic subgraph sets correspond to the N maximum subgraphs one by one.

Optionally, traversing the directed acyclic graph of the to-be-executed quantum program to obtain a maximum subgraph set, including:

generating a first subgraph according to a first node with zero in-degree in the directed acyclic graph;

deleting the first node to obtain a new directed acyclic graph;

determining whether a second node with zero in-degree exists in the new directed acyclic graph;

and if the second node does not exist in the new directed acyclic graph, determining the first subgraph as a maximum subgraph.

Optionally, the method further includes:

if the second node exists in the new directed acyclic graph, determining the adjacency relation between the second node and the first node;

generating a maximum subgraph based on the adjacency and the first node.

Optionally, the generating a maximum subgraph based on the adjacency relation and the first node includes:

expanding the first sub-graph into a second sub-graph based on the adjacency relation between the second node and the first node, and taking the second sub-graph as a new first sub-graph;

and acquiring the new directed acyclic graph after the second node is deleted, and continuously executing the step of determining whether the second node with zero in-degree exists in the new directed acyclic graph.

Optionally, the determining the cost of each isomorphic subgraph in the set of isomorphic subgraphs mapping to the quantum chip topology respectively includes:

respectively acquiring a mapping mode of each isomorphic subgraph mapped to the quantum chip topological structure according to the maximum subgraph set and the isomorphic subgraph set corresponding to the maximum subgraph;

and constructing a cost formula for evaluating the mapping mode and calculating the cost of the mapping mode.

Optionally, the cost formula for evaluating the mapping manner is as follows:

wherein, T ₂ De-coherence time, G, for a quantum chip bit _swap To be the finalThe number of SWAP gates, f, required to be introduced by the mapping mode _double For two-bit quantum logic gate fidelity, f _measure To measure fidelity, a ₁ 、a ₂ 、a ₃ 、a ₄ Is a preset weight coefficient of the cost formula.

One embodiment of the present application provides an apparatus for determining a quantum program final mapping, the apparatus comprising:

the acquisition module is used for acquiring a directed acyclic graph of the quantum program to be executed;

a first determining module, configured to determine, according to the directed acyclic graph of the quantum program to be executed, a maximum subgraph set of the quantum program to be executed and a isomorphic subgraph set corresponding to the maximum subgraph, where the isomorphic subgraph set is a logical bit-physical bit initial mapping relationship graph set obtained by the maximum subgraph according to a topological structure of a quantum chip;

a second determining module, configured to determine a cost for each isomorphic subgraph in the set of isomorphic subgraphs to map to the quantum chip topology, respectively;

and the third determining module is used for determining the final mapping of the quantum program to be executed according to the cost of mapping each isomorphic subgraph to the quantum chip topological structure, so that the cost of the final mapping is the lowest.

Optionally, the obtaining module includes:

the acquisition unit is used for acquiring nodes in the quantum program to be executed;

a determining unit, configured to determine an association relationship between the nodes according to the qubits operated by the nodes;

and the generating unit is used for generating a directed acyclic graph corresponding to the to-be-executed quantum program according to the nodes and the incidence relation among the nodes, wherein vertexes in the directed acyclic graph represent the nodes, edges in the directed acyclic graph represent the incidence relation among the nodes, and the directions of the edges represent the executed time sequence relation of the nodes corresponding to the vertexes connected with the edges.

Optionally, the first determining module includes:

the traversing unit is used for traversing the directed acyclic graph of the quantum program to be executed to obtain a maximum subgraph set, wherein the maximum subgraph set comprises N maximum subgraphs, and N is an integer greater than or equal to 1;

and the obtaining unit is used for determining isomorphic subgraphs of the N maximum subgraphs in the topological structure of the quantum chip to obtain N isomorphic subgraph sets, wherein the N isomorphic subgraph sets correspond to the N maximum subgraphs one by one.

Optionally, the traversal unit includes:

the subgraph unit is used for generating a first subgraph according to a first node with zero in-degree in the directed acyclic graph;

a deleting unit, configured to delete the first node to obtain a new directed acyclic graph;

a judging unit, configured to determine whether a second node with an entry degree of zero exists in the new directed acyclic graph;

a first subgraph determining unit, configured to determine the first subgraph as a maximum subgraph if the second node does not exist in the new directed acyclic graph.

Optionally, the apparatus further comprises:

a second subgraph determining unit, configured to determine, if the second node exists in the new directed acyclic graph, an adjacency relationship between the second node and the first node;

a maximum subgraph generating unit, configured to generate a maximum subgraph based on the adjacency relation and the first node.

Optionally, the maximum subgraph generation unit includes:

the expanding unit is used for expanding the first subgraph into a second subgraph based on the adjacency relation between the second node and the first node, and taking the second subgraph as a new first subgraph;

and a continuous execution unit, configured to acquire the new directed acyclic graph after the second node is deleted, and continuously execute the step of determining whether there is a second node with an entry degree of zero in the new directed acyclic graph.

Optionally, the second determining module includes:

the mapping unit is used for respectively acquiring a mapping mode of each isomorphic subgraph mapped to the quantum chip topological structure according to the maximum subgraph set and the isomorphic subgraph set corresponding to the maximum subgraph;

and the construction unit is used for constructing a cost formula for evaluating the mapping mode and calculating the cost of the mapping mode.

A further embodiment of the application provides a storage medium having a computer program stored thereon, wherein the computer program is arranged to perform the method of any of the above when executed.

Yet another embodiment of the present application provides an electronic device, comprising a memory having a computer program stored therein and a processor configured to execute the computer program to perform the method described in any of the above.

Yet another embodiment of the present application provides a quantum computer operating system that implements determination of a quantum program final mapping according to the method described in any of the above.

Yet another embodiment of the present application provides a quantum computer comprising the quantum computer operating system.

Compared with the prior art, the method includes the steps of firstly obtaining a directed acyclic graph of the quantum program, determining the maximum subgraph set of the quantum program and the isomorphic subgraph set corresponding to the maximum subgraph according to the directed acyclic graph of the quantum program, respectively determining the cost of mapping each isomorphic subgraph in the isomorphic subgraph set to the quantum chip topological structure, and determining the final mapping of the quantum program to be executed according to the cost of mapping each isomorphic subgraph to the quantum chip topological structure, so that the final mapping cost is the lowest, the problem that influence is generated on the whole quantum circuit due to a single physical bit factor is solved, the final mapping circuit of the quantum chip topological structure can also be determined, and the resource utilization of the whole quantum chip is maximized.

Drawings

Fig. 1 is a block diagram of a hardware structure of a computer terminal of a method for determining a quantum program final mapping according to an embodiment of the present invention;

fig. 2 is a schematic flowchart of a method for determining a quantum program final mapping according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating a quantum circuit to be executed according to an embodiment of the present invention;

FIG. 4 is a diagram of a directed acyclic graph corresponding to a to-be-executed quantum circuit according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a topology structure of a physical bit of a quantum chip according to an embodiment of the present invention;

fig. 6 is a schematic diagram of a first subgraph determined based on a first node in the directed acyclic graph shown in fig. 4 according to the embodiment of the present invention;

fig. 7 is a schematic diagram of a new directed acyclic graph obtained after the first node is deleted in fig. 4 according to an embodiment of the present invention;

fig. 8 is a schematic diagram of a second sub-graph obtained by expanding on fig. 6 based on a second node according to the embodiment of the present invention;

fig. 9 is a schematic diagram of a new directed acyclic graph obtained after the second node is deleted in fig. 7 according to an embodiment of the present invention;

fig. 10 is a schematic diagram of a new second sub-graph obtained by expanding on fig. 8 based on a second node according to the embodiment of the present invention;

fig. 11 is a schematic diagram of a new directed acyclic graph obtained after deleting a second node based on fig. 9 according to the embodiment of the present invention;

fig. 12 is a schematic diagram of a second sub-graph determined based on a second node in the directed acyclic graph shown in fig. 11 according to the embodiment of the present invention;

fig. 13 is a schematic diagram of a new directed acyclic graph obtained after deleting a second node based on fig. 11 according to an embodiment of the present invention;

fig. 14 is a schematic diagram of a second sub-graph determined based on a second node in the directed acyclic graph shown in fig. 12 according to the embodiment of the present invention;

fig. 15 is a schematic diagram of a new directed acyclic graph obtained after deleting a second node based on fig. 13 according to the embodiment of the present invention;

fig. 16 is a schematic diagram of a first sub-graph determined based on a first node in the new directed acyclic graph shown in fig. 15 according to the embodiment of the present invention;

fig. 17 is a schematic structural diagram of a device for determining a quantum program final mapping according to an embodiment of the present invention.

Detailed Description

The embodiments described below with reference to the drawings are illustrative only and should not be construed as limiting the invention.

The embodiment of the invention firstly provides a method for determining quantum program final mapping, and the method can be applied to electronic equipment, such as a computer terminal, and specifically, a common computer, a quantum computer and the like.

This will be described in detail below by way of example as it would run on a computer terminal. Fig. 1 is a block diagram of a hardware structure of a computer terminal of a method for determining quantum program final mapping according to an embodiment of the present invention. As shown in fig. 1, the computer terminal may include one or more (only one shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, and optionally, a transmission device 106 for communication functions and an input-output device 108. It will be understood by those skilled in the art that the structure shown in fig. 1 is only an illustration and is not intended to limit the structure of the computer terminal. For example, the computer terminal may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.

The memory 104 may be used to store software programs and modules of application software, such as program instructions/modules corresponding to the determination method for implementing a quantum program final mapping in the embodiment of the present application, and the processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, implements the above-mentioned method. The memory 104 may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory located remotely from the processor 102, which may be connected to a computer terminal over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission device 106 is used for receiving or transmitting data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the computer terminal. In one example, the transmission device 106 includes a Network adapter (NIC) that can be connected to other Network devices through a base station to communicate with the internet. In one example, the transmission device 106 can be a Radio Frequency (RF) module, which is used to communicate with the internet in a wireless manner.

It should be noted that a true quantum computer is a hybrid structure, which includes two major components: one part is a classic computer which is responsible for executing classic calculation and control; the other part is quantum equipment which is responsible for running a quantum program to further realize quantum computation. The quantum program is a string of instruction sequences which can run on a quantum computer and are written by a quantum language such as a Qrun language, so that the support of the operation of the quantum logic gate is realized, and the quantum computation is finally realized. In particular, a quantum program is a sequence of instructions that operate quantum logic gates in a time sequence.

In practical applications, due to the limited development of quantum device hardware, quantum computation simulation is usually required to verify quantum algorithms, quantum applications, and the like. The quantum computing simulation is a process of realizing the simulation operation of a quantum program corresponding to a specific problem by means of a virtual architecture (namely a quantum virtual machine) built by resources of a common computer. In general, it is necessary to build quantum programs for a particular problem. The quantum program referred in the embodiment of the invention is a program written in a classical language for representing quantum bits and evolution thereof, wherein the quantum bits, quantum logic gates and the like related to quantum computation are all represented by corresponding classical codes.

A quantum circuit, which is a commonly used general quantum computing model, represents a circuit that operates on a quantum bit under an abstract concept, and includes the quantum bit, the circuit (timeline), and various quantum logic gates, and finally, it is often necessary to read a result through a quantum measurement operation.

Unlike conventional circuits that are connected by metal lines to pass either voltage or current signals, in quantum circuits, the lines can be viewed as being connected by time, i.e., the state of a qubit evolves naturally over time, in the process being operated on as indicated by the hamiltonian until a logic gate is encountered.

The quantum program refers to the total quantum circuit, wherein the total number of the quantum bits in the total quantum circuit is the same as the total number of the quantum bits of the quantum program. It can be understood that: a quantum program may consist of quantum wires, measurement operations for quantum bits in the quantum wires, registers to hold measurement results, and control flow nodes (jump instructions), and a quantum wire may contain tens to hundreds or even thousands of quantum gate operations. The execution process of the quantum program is a process executed for all the quantum logic gates according to a certain time sequence. It should be noted that timing is the time sequence in which the single quantum logic gate is executed.

It should be noted that in the classical calculation, the most basic unit is a bit, and the most basic control mode is a logic gate, and the purpose of the control circuit can be achieved through the combination of the logic gates. Similarly, the way qubits are handled is quantum logic gates. The evolution of quantum states can be enabled using quantum logic gates, which are the basis for forming quantum circuits, including single-bit quantum logic gates, such as Hadamard gates (H-gates, hadamard gates), pauli-X gates (X-gates), pauli-Y gates (Y-gates), pauli-Z gates (Z-gates), RX-gates, RY-gates, RZ-gates, and so forth; multi-bit quantum logic gates such as CNOT gates, CR gates, isswap gates, toffoli gates, etc. Quantum logic gates are typically represented using unitary matrices, which are not only in matrix form, but also an operation and transformation. The function of a general quantum logic gate on a quantum state is calculated by multiplying a unitary matrix by a matrix corresponding to a quantum state right vector.

The quantum states, i.e. the logical states of qubits, are represented in binary in quantum arithmetic (or quantum program), for example, a group of qubits is q0, q1, q2, representing 0 th, 1 st, and 2 nd qubits, and are ordered from high to low as q2q1q0, the quantum states corresponding to the group of qubits are the superposition of the eigenstates corresponding to the group of qubits, and the eigenstates corresponding to the group of qubits total 2 quanta total power, i.e. 8 eigenstates (deterministic states): the method comprises the following steps of |000>, |001>, |010>, |011>, |100>, |101>, |110>, |111>, the bit of each eigen state corresponds to a qubit, for example, |000> state, 000 corresponds to q2q1q0 from high to low, and | is a dirac symbol.

Illustrating the logic state of a single qubit in terms of a single qubit

May be at |0>State, |1>State, |0>Sum of states |1>The superposition state (indeterminate state) of the states can be specifically expressed as

Where c and d are complex numbers representing the amplitude (probability amplitude) of the quantum state, the square of the amplitude c ² And d ² Respectively represent |0>State 1>Probability of state, | c | non-calculation ² +|d| ² And =1. In short, a quantum state is a superposition of the components of each eigenstate, and is in a uniquely determined eigenstate when the probability of the other eigenstate is 0.

Referring to fig. 2, fig. 2 is a schematic flowchart of a method for determining a quantum program final mapping according to an embodiment of the present invention.

The present embodiment provides an embodiment of a method for determining a quantum program final mapping, where the method for determining a quantum program final mapping includes:

s201: and acquiring a directed acyclic graph of the quantum program to be executed.

In particular, the quantum program to be executed is mainly composed of tens to hundreds or even thousands of quantum logic gates. The execution process of the quantum program is a process executed on all the quantum logic gates according to a certain time sequence, and it should be noted that the time sequence is a time sequence in which a single quantum logic gate is executed.

A directed acyclic graph (DAG graph) is a directed graph, the literal meaning is that the graph has no rings and is a directed graph without loops, and if a non-directed acyclic graph exists, the graph can return to the point A from the point A to the point B through the point C, and then a ring is formed. If the direction from the point C to the point A is changed to the direction from the point A to the point C, the direction becomes a directed acyclic graph which is often used for representing the driving dependency relationship among events, the scheduling among tasks and the like.

The method for obtaining the directed acyclic graph of the quantum program to be executed specifically comprises the following steps:

s2011: and acquiring nodes in the quantum program to be executed.

In particular, a quantum program is understood to be a sequence of operations, which mainly comprises quantum logic gates, measurement operations (measures), etc. The node in the quantum program refers to data having a specific structure in a relative position of the entire program, and may be a quantum logic gate, a Measure operation (Measure), or the like.

Specifically, quantum logic gate nodes in the quantum program can be obtained by traversing the nodes of the quantum program.

For example, referring to fig. 3, fig. 3 is a schematic diagram of a to-be-executed quantum circuit according to an embodiment of the present invention, where a solid black dot represents a control bit of a CNOT quantum logic gate, and a "+" in the solid black circle represents a target bit of the CNOT quantum logic gate, it can be understood that a quantum program corresponds to a total quantum circuit as a whole, and the to-be-executed quantum program according to the embodiment of the present invention refers to the total quantum circuit. Wherein, the quantum program to be executed is CNOT (q [0], q [1 ]) < < CNOT (q [0], q [2 ]) < < CNOT (q [0], q [3 ]) <CNOT (q [1], q [2 ]) < < CNOT (q [1], q [3 ]) <CNOT (q [2], q [3 ])), traversal is started from CNOT (q [0], q [1 ]), and CNOT (q [0], q [1 ]), CNOT (q [0 ]), CNOT (q [2 ]), CNOT (q [0], q [3 ]), CNOT (q [1], q [2 ]), CNOT (q [1], q [3 ]), CNOT (q [2], CNOT (q [3 ]), CNOT (q [2], and Q [3 ]), respectively, in the quantum program to be executed are obtained.

S2012: and determining the incidence relation between the nodes according to the quantum bits operated by the nodes.

Specifically, for each quantum operation node, a next node of the node is determined from all quantum operation nodes sequentially executed by the qubit of the node operation, and an adjacent relationship between the node and the next node is obtained.

Specifically, in the process of traversing the nodes of the quantum wires, the sequence number and the unique identifier of the quantum bit operated by the currently traversed node are recorded, so as to update the last node corresponding to each bit in the traversal process. And recording information of a last node corresponding to each bit and a currently traversed node and an adjacent relation between the last node and the currently traversed node. And the last node corresponding to the quantum bit refers to a precursor node of the currently traversed node of the quantum logic gate.

It should be noted that the unique identifier of the quantum logic gate is marked according to the execution time sequence of the quantum logic gate.

For example, as shown in fig. 3, a to-be-executed quantum circuit diagram is first to traverse nodes of a quantum program in sequence according to quantum bits of node operation. Starting from the first layer of quantum wires, CNOT (q [0], q [1 ]) is traversed, the qubit numbers of the CNOT gate operations are 0 and 1, their unique identifiers are "1", and none of the current first layer CNOT gates has a predecessor node.

When traversing to the beginning of the second layer of the quantum wire, i.e. traversing to the node CNOT (q 0, q 2), the serial numbers of the quantum bits of the CNOT gate operation are 0 and 2, the unique identifier is 2, the predecessor node of the CNOT (q 0, q 2) is CNOT (q 0, q 1), the neighboring relationship between the bits is recorded, and the record is in the form of the unique identifier, which can be recorded as {1,2}, and represents that node 1 and node 2 are neighboring. Then, sequentially traversing to CNOT (q 0, q 3) of the third layer, CNOT (q 1, q 2) of the fourth layer, CNOT (q 1, q 3) of the fifth layer, CNOT (q 2, q 3) of the sixth layer, obtaining quantum bit of each layer of node operation, determining association relation between nodes, and processing flow is the same, and is not repeated herein.

S2013: and generating a directed acyclic graph corresponding to the quantum program to be executed according to the nodes and the incidence relation among the nodes, wherein the vertexes in the directed acyclic graph represent the nodes, the edges in the directed acyclic graph represent the incidence relation among the nodes, and the directions of the edges represent the executed time sequence relation of the nodes corresponding to the vertexes connected with the edges.

Referring to fig. 4, fig. 4 is a schematic diagram of a to-be-executed quantum line corresponding directed acyclic graph according to an embodiment of the present invention. Specifically, a vertex corresponding to the quantum operation node is constructed, an edge between the vertices corresponding to the nodes having the adjacent relationship is constructed, wherein the direction of the edge is pointed to the vertex corresponding to the next node by the vertex corresponding to the previous node in the nodes having the adjacent relationship, and then the directed acyclic graph corresponding to the to-be-executed quantum program is generated according to the nodes and the association relationship between the nodes.

S202: and determining a maximum subgraph set of the quantum program to be executed and a isomorphic subgraph set corresponding to the maximum subgraph according to the directed acyclic graph of the quantum program to be executed, wherein the isomorphic subgraph set is a logic bit-physical bit initial mapping relation graph set obtained by the maximum subgraph according to the topological structure of a quantum chip.

For the sake of distinction, the qubit structure in a quantum chip is generally referred to as a physical bit, and the subject bit operated on in a quantum wire is referred to as a logical bit. The initial mapping relationship between the logical bits and the physical bits refers to the relationship of "corresponding" between the logical bits and the physical bits.

Illustratively, referring to fig. 5, fig. 5 is a schematic diagram of a topology of physical bits of a quantum chip according to an embodiment of the present invention, where the quantum chip includes 8 physical bits, i.e., Q [0], Q [1], Q [2], Q [3], Q [4], Q [5], Q [6], and Q [7], and the 8 physical bits may be coupled through capacitors and only adjacent physical bits have a coupling relationship. Wherein Q0 is connected to Q1 and Q4, Q5 is connected to Q1, Q4 and Q6, Q2 is connected to Q1, Q6 and Q3, and Q7 is connected to Q3 and Q6.

Illustratively, for a quantum program CNOT (Q [0], Q [1 ]) < < CNOT (Q [0], Q [2 ]) < < CNOT (Q [0], Q [3 ]) < < CNOT (Q [1], Q [2 ]) < < CNOT (Q [1], Q [3 ]) < < CNOT (Q [2], Q [3 ]), the logical bits of the operation are Q [0], Q [1], Q [2], Q [3], respectively, the initial mapping relationship between the logical bits and the physical bits can be set to Q [0], Q [1] to Q [1], Q [2] to Q [2], Q [3] to Q [3], and so on.

Specifically, determining the maximum subgraph set of the quantum program to be executed and the isomorphic subgraph set corresponding to the maximum subgraph according to the directed acyclic graph of the quantum program to be executed includes the following steps:

step S2021: and traversing the directed acyclic graph of the quantum program to be executed to obtain a maximum subgraph set, wherein the maximum subgraph set comprises N maximum subgraphs, and N is an integer greater than or equal to 1.

Specifically, the N maximum subgraphs are sequentially arranged according to respective obtained orders to obtain a maximum subgraph set, including:

1. and generating a first subgraph according to a first node with zero in-degree in the directed acyclic graph.

In particular, introductivity is one of the important concepts in graph theory algorithms, and generally refers to the sum of the number of times a certain point in a directed graph is used as an end point of an edge in the graph.

Illustratively, as shown in fig. 4, a to-be-executed quantum line corresponds to a schematic diagram of an acyclic graph, where a first node with an in-degree of zero is CNOT (q [0], q [1 ]), and a first subgraph as shown in fig. 6 is generated, and as shown in fig. 6, for a node corresponding to CNOT (q [0], q [1 ]), two points and an edge are included, where two points refer to a point corresponding to q [0] and a point corresponding to q [1], and an edge refers to an edge between a point corresponding to q [0] and a point corresponding to q [1 ]. The dot corresponding to q [0] represents a logical qubit q [0], the dot corresponding to q [1] represents a logical qubit q [1], and the edge between the dot corresponding to q [0] and the dot corresponding to q [1] may represent a CNOT gate acting on logical qubit q [0] and logical qubit q [1 ].

2. And deleting the first node to obtain a new directed acyclic graph.

Illustratively, following the above example, the first node CNOT (q [0], q [1 ]) with zero in-degree is deleted, and a new directed acyclic graph as shown in FIG. 7 is generated.

3. And determining whether a second node with zero in-degree exists in the new directed acyclic graph.

Specifically, with reference to the method for determining the first node, it is determined whether a second node with zero in-degree exists in the new directed acyclic graph. And if the second node exists in the new directed acyclic graph, determining the adjacent relation between the second node and the first node, and generating a maximum subgraph based on the adjacent relation and the first node.

Said generating a maximum subgraph based on said adjacency and said first node comprises:

and expanding the first subgraph into a second subgraph based on the adjacency relation between the second node and the first node, and taking the second subgraph as a new first subgraph.

Illustratively, according to the new directed acyclic graph shown in FIG. 7, there is a second node CNOT (q [0], q [2 ]) with zero in-degree, and the adjacency relation of the second node CNOT (q [0], q [1 ]) and the first node CNOT is determined. It should be noted that the directed edges between the nodes are used to represent the adjacency relation of the quantum logic gate according to the quantum state evolution timing sequence of the logic qubit, and based on the adjacency relation and the first node, a schematic diagram is generated, as shown in fig. 8, that the first sub-graph is expanded into the second sub-graph.

And acquiring the new directed acyclic graph after the second node is deleted, and continuously executing the step of determining whether a second node with zero degree of income exists in the new directed acyclic graph.

Illustratively, in connection with the above example, the new directed acyclic graph after the second node is deleted is obtained, another new directed acyclic graph as shown in fig. 9 is generated, and the above step 3 is continuously performed to determine whether there is a second node with an introductivity of zero in the another new directed acyclic graph.

4. And if the second node does not exist in the new directed acyclic graph, determining the first subgraph as a maximum subgraph.

Specifically, if the second node does not exist in the new directed acyclic graph, it is indicated that the traversal of the whole quantum program to be executed is completed, and the first sub-graph may be determined as a maximum sub-graph.

If there is a second node with zero in-degree in the new directed acyclic graph, there are two cases: one is that the subgraph can continue to be extended based on the second node, resulting in a larger subgraph than before; and the other is that the subgraph cannot be continued to be expanded based on the second node, and then the current subgraph is the maximum subgraph.

Step S2022: and determining isomorphic subgraphs of the N maximum subgraphs in the topological structure of the quantum chip to obtain N isomorphic subgraph sets, wherein the N isomorphic subgraph sets correspond to the N maximum subgraphs one by one.

Specifically, the isomorphic subgraph is a bit relation graph on a quantum chip, which is obtained by mapping a maximum subgraph based on a topological structure of the quantum chip in the electronic device. For example, assuming that the largest subgraph is "Q [0] - [ Q [1]", and the topology of the quantum chip in the electronic device is "Q [0] - [ Q [1] - [ Q [2] - [ Q [3]", then "Q [0] - [ Q [1]" can be mapped to "Q [0] - [ Q [1]", also can be mapped to "Q [1] - [ Q [2]", also can be mapped to "Q [2] - [ Q [3]", then the isomorphic subgraph of the largest subgraph "Q [0] - [ Q [1]" is: "Q [0] -Q [1]", "Q [1] -Q [2]", and "Q [2] -Q [3]".

The following is a specific application example of the maximum subgraph set determination method provided in the embodiment of the present application.

Illustratively, for a quantum program segment CNOT (q [0], q [1 ]) < < CNOT (q [0], q [2 ]) < < CNOT (q [0], q [3 ]) < < CNOT (q [1], q [2 ]) < < CNOT (q [1], q [3 ]) < < CNOT (q [2], q [3 ]), as shown in fig. 3, a corresponding directed acyclic graph is shown in fig. 4.

The steps for determining the maximum subgraph set according to the directed acyclic graph shown in fig. 4 are as follows:

first, determining a first node with zero in-degree as CNOT (q [0], q [1 ]), as shown in FIG. 6, where FIG. 6 is a schematic diagram of a first sub-graph determined based on the first node in the directed acyclic graph shown in FIG. 4; deleting a first node CNOT (q [0], q [1 ]) with zero in-degree, as shown in FIG. 7, FIG. 7 is a schematic diagram of a new directed acyclic graph obtained after deleting the first node in FIG. 4; according to the new directed acyclic graph shown in fig. 7, there is a second node CNOT (q [0], q [2 ]) with zero in-degree, determine an adjacency relation between the second node and the first node CNOT (q [0], q [1 ]), and generate a schematic diagram shown in fig. 8 based on the adjacency relation and the first node, where fig. 8 is a schematic diagram of a second sub-graph obtained by expanding on fig. 6 based on the second node; obtaining a new directed acyclic graph after deleting the second node, as shown in fig. 9, where fig. 9 is a schematic diagram of the new directed acyclic graph obtained after deleting the second node in fig. 7, and there are second nodes CNOT (q 0, q 3) and CNOT (q 1, q 2) with zero in-degree, so there are two second nodes here. The execution priorities of the nodes corresponding to CNOT (q 0, q 3) and the nodes corresponding to CNOT (q 1, q 2) are determined, and since one point of the nodes corresponding to CNOT (q 0, q 3) is in the second subgraph (as shown in FIG. 8), and two points of the nodes corresponding to CNOT (q 1, q 2) are in the second subgraph, but the edge between the two points is not in the second subgraph, the execution priority of CNOT (q 1, q 2) is lower than the execution priority of CNOT (q 0, q 3). Executing the node corresponding to CNOT (q 0, q 3), i.e. using the point corresponding to q0 as the edge, expanding the second sub-graph as shown in FIG. 10, where FIG. 10 is a schematic diagram of a new second sub-graph obtained by expanding on FIG. 8 based on the second node; and then, executing the node corresponding to CNOT (q 1, q 2), and determining the obtained new second subgraph as a maximum subgraph as shown in FIG. 10, although two points in the node are both in the new second subgraph but the edge between the two points is not in the new first subgraph.

Obtaining a new directed acyclic graph from which a second node CNOT (q [0], q [3 ]) is deleted, generating a schematic diagram of the new directed acyclic graph obtained after deleting one second node based on FIG. 9 as shown in FIG. 11, where there are second nodes CNOT (q [1], q [2 ]) with an in-degree of zero, as shown in FIG. 12, and FIG. 12 is a schematic diagram of a second sub-graph determined based on the second node in the directed acyclic graph shown in FIG. 11; deleting a second node CNOT (q [1], q [2 ]) with zero degree, as shown in FIG. 13, where FIG. 13 is a schematic diagram of a new directed acyclic graph obtained after deleting the second node based on FIG. 11, and according to the new directed acyclic graph shown in FIG. 13, there is a second node CNOT (q [1], q [3 ]) with zero degree, as shown in FIG. 14, and FIG. 14 is a schematic diagram of a second sub-graph determined based on the second node in the directed acyclic graph shown in FIG. 12; deleting a second node CNOT (q [1], q [3 ]) with zero in-degree, as shown in fig. 15, where fig. 15 is a schematic diagram of a new directed acyclic graph obtained after deleting the second node based on fig. 13, and then determining whether the second node exists in the new directed acyclic graph, where the in-degree of the node corresponding to the CNOT (q [2], q [3 ]) is 0, so that the node corresponding to the CNOT (q [2], q [3 ]) is the second node, and two points in the node corresponding to the CNOT (q [2], q [3 ]) are both in the second subgraph (fig. 14) but an edge between the two points is not in the second subgraph, and then determining the obtained second subgraph as shown in fig. 14 as a maximum subgraph.

Taking the node corresponding to CNOT (q 2, q 3) as a new first node, taking the first node including two points (a point corresponding to q2 and a point corresponding to q 3) as two endpoints in the first subgraph, and taking the edge included in the first node as the edge of the first subgraph to obtain the first subgraph, as shown in fig. 16, fig. 16 is a schematic diagram of the first subgraph determined based on the first node in the new directed acyclic graph shown in fig. 15. Deleting nodes corresponding to CNOT (q 2, q 3), obtaining a new directed acyclic graph which is empty, completing traversal at the moment, and determining the first subgraph as a maximum subgraph.

In summary, three maximum subgraphs can be obtained according to a quantum program to be executed as shown in fig. 3: maximum subgraphs (as shown in FIG. 10) respectively composed of CNOT (q 0, q 1) < < CNOT (q 0, q 2) < < CNOT (q 0, q 3); a maximal subgraph composed of CNOT (q [1], q [2 ]) < < CNOT (q [1], q [3 ]) (as shown in FIG. 14); CNOT (q 2, q 3) constitutes the largest subgraph (as shown in FIG. 16), and the largest subgraph set can be obtained by arranging the three largest subgraphs in turn according to the obtained obtaining sequence.

S203: determining a cost of each isomorphic subgraph in the set of isomorphic subgraphs mapped to the quantum chip topology, respectively.

Specifically, the mapping manner in which each isomorphic subgraph is mapped to the quantum chip topology structure can be respectively obtained according to the maximum subgraph set and the isomorphic subgraph set corresponding to the maximum subgraph.

Illustratively, referring to FIG. 5, the quantum chip includes 8 physical bits, Q0, Q1, Q2, Q3, Q4, Q5, Q6, and Q7, wherein Q0 is connected to Q1 and Q4, Q5 is connected to Q1, Q4, and Q6, Q2 is connected to Q1, Q6, and Q3, and Q7 is connected to Q3 and Q6.

Mapping the obtained first maximum subgraph (fig. 10) in the quantum chip shown in fig. 5 to obtain 24 first isomorphic subgraphs, wherein the 24 first isomorphic subgraphs form a first isomorphic subgraph mapping mode set; mapping the obtained second maximum subgraph (fig. 14) in the quantum chip shown in fig. 5 to obtain 32 second isomorphic subgraphs, wherein the 32 second isomorphic subgraphs form a second isomorphic subgraph mapping mode set; mapping the obtained third maximum subgraph (fig. 16) in the quantum chip shown in fig. 5 to obtain 20 third isomorphic subgraphs, where the 20 third isomorphic subgraphs form a third set of isomorphic subgraph mapping modes, and specific forms of each first isomorphic subgraph mapping mode, each second isomorphic subgraph mapping mode, and each third isomorphic subgraph mapping mode are not listed here.

And respectively determining the cost of mapping each isomorphic subgraph in the first isomorphic subgraph mapping mode set, the second isomorphic subgraph mapping mode set and the third isomorphic subgraph mapping mode set to the quantum chip topological structure.

And constructing a cost formula for evaluating the mapping scheme and calculating the cost of the mapping mode.

Wherein the cost formula for evaluating the mapping scheme is:

wherein, T ₂ De-coherence time, G, for a quantum chip bit _swap The number of SWAP gates, f, required to be introduced for the final mapping mode _double For two-bit quantum logic gate fidelity, f _measure To measure fidelity, a ₁ 、a ₂ 、a ₃ 、a ₄ Is a preset weight coefficient of the cost formula.

It should be noted that the cost of each mapping mode is evaluated by the cost formula, multiple factors such as the shortest path, the fidelity of two-bit quantum logic gates, the measurement fidelity, the decoherence time and the like are considered comprehensively, then the consumption cost of each isomorphic sub-graph mapped to the quantum chip topology structure is obtained through weighting and summing in sequence, the isomorphic sub-graph mapping mode with the minimum consumption cost is selected from each set of isomorphic sub-graph mapping modes, then the consumption cost mapped to the quantum chip topology structure in the next set of isomorphic sub-graphs is continuously searched until all logic gates in the whole quantum line to be executed are mapped to physical bits of the quantum chip topology structure.

S204: and determining the final mapping of the quantum program to be executed according to the cost of mapping each isomorphic subgraph to the quantum chip topological structure, so that the cost of the final mapping is the lowest.

Illustratively, the first set of isomorphic subgraph mapping manners includes 24 first isomorphic subgraphs, and each first isomorphic subgraph corresponds to a consumption cost according to the cost formula; the second isomorphic subgraph mapping mode set comprises 32 second isomorphic subgraphs, and each second isomorphic subgraph corresponds to one consumption cost according to the cost formula; the third isomorphic subgraph mapping mode set comprises 20 third isomorphic subgraphs, and each third isomorphic subgraph also corresponds to one consumption cost according to the cost formula; there are 24 × 32 consumption costs between the first set of isomorphic sub-graph mapping modes and the second set of isomorphic sub-graph mapping modes, and there are 32 × 20 consumption costs between the second set of isomorphic sub-graph mapping modes and the third set of isomorphic sub-graph mapping modes. Therefore, 24 × 32 × 20 mapping modes can be combined based on the first set of isomorphic sub-graph mapping modes, the second set of isomorphic sub-graph mapping modes, and the third set of isomorphic sub-graph mapping modes, each mapping mode corresponds to a consumption cost, each consumption cost is determined based on the cost formula, and a mode with the minimum consumption cost can be selected to determine the final mapping of the quantum program to be executed, so that the cost of the final mapping is the lowest.

The embodiment of the application provides a method for determining the final mapping of the quantum program, which is characterized in that the consumption cost of all mapping modes is calculated, then the final mapping with the minimum consumption cost is determined, and the final mapping line of the quantum program to be executed is determined, so that the resource utilization of the whole quantum chip is maximized.

It should be noted that the existence of the single quantum logic gate in the directed acyclic graph of the quantum program to be executed does not affect the construction of the maximum subgraph and the determination of the final mapping, and the maximum subgraph obtained by the directed acyclic graph with the single quantum logic gate is the same as the maximum subgraph obtained by the directed acyclic graph without the single quantum logic gate. Therefore, for simplicity, single quantum logic gates are removed here, and only a directed acyclic graph containing two-bit quantum logic gates is used as an example.

Referring to fig. 17, fig. 17 is a schematic structural diagram of a device for determining a quantum program final mapping according to an embodiment of the present invention, which corresponds to the flow shown in fig. 2, and the device may include:

an obtaining module 1701, configured to obtain a directed acyclic graph of a to-be-executed quantum program;

a first determining module 1702, configured to determine, according to the directed acyclic graph of the quantum program to be executed, a maximum subgraph set of the quantum program to be executed and a isomorphic subgraph set corresponding to the maximum subgraph, where the isomorphic subgraph set is a set of a logical bit-physical bit initial mapping relationship graph obtained by the maximum subgraph according to a topological structure of a quantum chip;

a second determining module 1703, configured to determine a cost of each isomorphic subgraph in the set of isomorphic subgraphs mapping to the quantum chip topology, respectively;

a third determining module 1704, configured to determine a final mapping of the quantum program to be executed according to a cost of mapping each isomorphic sub-graph to the quantum chip topology, so as to minimize the cost of the final mapping.

Specifically, the obtaining module includes:

Specifically, the first determining module includes:

Specifically, the traversal unit includes:

Specifically, the apparatus further comprises:

a second subgraph determining unit, configured to determine an adjacency relationship between the second node and the first node if the second node exists in the new directed acyclic graph;

Specifically, the maximum subgraph generation unit includes:

and a continuous execution unit, configured to obtain the new directed acyclic graph from which the second node is deleted, and continuously execute the step of determining whether there is a second node with an entry degree of zero in the new directed acyclic graph.

Specifically, the second determining module includes:

An embodiment of the present invention further provides a storage medium, where a computer program is stored, where the computer program is configured to execute the steps in any one of the method embodiments described above when the computer program is run.

Specifically, in the present embodiment, the storage medium may be configured to store a computer program for executing the steps of:

s201: acquiring a directed acyclic graph of a quantum program to be executed;

s202: determining a maximum subgraph set of the quantum program to be executed and a isomorphic subgraph set corresponding to the maximum subgraph according to the directed acyclic graph of the quantum program to be executed, wherein the isomorphic subgraph set is a logic bit-physical bit initial mapping relation graph set obtained by the maximum subgraph according to the topological structure of a quantum chip;

s203: respectively determining the cost of each isomorphic subgraph in the set of isomorphic subgraphs mapping to the quantum chip topology;

Specifically, in this embodiment, the storage medium may include, but is not limited to: various media capable of storing computer programs, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.

Compared with the prior art, the method comprises the steps of firstly obtaining the directed acyclic graph of the quantum program, determining the maximum subgraph set of the quantum program and the isomorphic subgraph set corresponding to the maximum subgraph according to the directed acyclic graph of the quantum program, respectively determining the cost of mapping each isomorphic subgraph in the isomorphic subgraph set to the topological structure of the quantum chip, and determining the final mapping of the quantum program to be executed according to the cost of mapping each isomorphic subgraph to the topological structure of the quantum chip, so that the final mapping cost is the lowest, the problem that the whole quantum circuit is affected due to a single physical bit is solved, the final mapping circuit of the topological structure of the quantum chip can also be determined, and the resource utilization of the whole quantum chip is maximized.

An embodiment of the present invention further provides an electronic device, which includes a memory and a processor, where the memory stores a computer program, and the processor is configured to execute the computer program to perform the steps in any one of the method embodiments described above.

Specifically, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.

Specifically, in this embodiment, the processor may be configured to execute the following steps by a computer program:

s201: acquiring a directed acyclic graph of a quantum program to be executed;

The embodiment of the invention also provides a quantum computer operating system, and the quantum computer operating system realizes the determination of the final mapping of the quantum program according to any one of the method embodiments provided in the embodiment of the invention.

The embodiment of the application also provides a quantum computer, which comprises the quantum computer operating system.

The construction, features and functions of the present invention are described in detail in the embodiments illustrated in the drawings, which are only preferred embodiments of the present invention, but the present invention is not limited by the drawings, and all equivalent embodiments modified or changed according to the idea of the present invention should fall within the protection scope of the present invention without departing from the spirit of the present invention covered by the description and the drawings.

Claims

1. A method for determining a quantum program final mapping, the method comprising:

acquiring a directed acyclic graph of a quantum program to be executed;

2. The method according to claim 1, wherein the obtaining a directed acyclic graph of a quantum program to be executed comprises:

acquiring nodes in a quantum program to be executed;

3. The method of claim 2, wherein the determining, according to the directed acyclic graph of the quantum program to be executed, the maximum subgraph set of the quantum program to be executed and the isomorphic subgraph set corresponding to the maximum subgraph includes:

and determining isomorphic subgraphs of the N maximum subgraphs in the topological structure of the quantum chip to obtain N isomorphic subgraph sets, wherein the N isomorphic subgraph sets correspond to the N maximum subgraphs one by one.

4. The method of claim 3, wherein traversing the directed acyclic graph of the quantum program to be executed results in a maximum set of subgraphs, comprising:

deleting the first node to obtain a new directed acyclic graph;

5. The method of claim 4, further comprising:

generating a maximum subgraph based on the adjacency and the first node.

6. The method of claim 5, wherein generating a maximum subgraph based on the adjacency and the first node comprises:

7. The method of claim 1, wherein separately determining a cost of each isomorphic subgraph in the set of isomorphic subgraphs mapping to the quantum chip topology comprises:

respectively obtaining a mapping mode of each isomorphic subgraph mapped to the quantum chip topological structure according to the maximum subgraph set and the isomorphic subgraph set corresponding to the maximum subgraph;

8. The method of claim 7, wherein the cost formula for evaluating the mapping is:

wherein, T ₂ De-coherence time, G, for a quantum chip bit _swap Number of SWAP gates, f, required to be introduced for the final mapping mode _double For two-bit quantum logic gate fidelity, f _measure To measure fidelity, a ₁ 、a ₂ 、a ₃ 、a ₄ Is a preset weight coefficient of the cost formula.

9. An apparatus for determining a quantum program final map, the apparatus comprising:

the first determining module is used for determining a maximum subgraph set of the quantum program to be executed and an isomorphic subgraph set corresponding to the maximum subgraph according to the directed acyclic graph of the quantum program to be executed, wherein the isomorphic subgraph set is a logic bit-physical bit initial mapping relation graph set obtained by the maximum subgraph according to a topological structure of a quantum chip;

10. A storage medium, in which a computer program is stored, wherein the computer program is arranged to perform the method of any of claims 1 to 8 when executed.

11. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and wherein the processor is arranged to execute the computer program to perform the method of any of claims 1 to 8.

12. A quantum computer operating system, wherein the quantum computer operating system implements determination of a quantum program final mapping according to the method of any one of claims 1 to 8.

13. A quantum computer, characterized in that it comprises the quantum computer operating system of claim 12.