CN115907023A - Method and device for determining target mapping of to-be-executed quantum program and quantum computer - Google Patents
Method and device for determining target mapping of to-be-executed quantum program and quantum computer Download PDFInfo
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Abstract
The invention discloses a method and a device for determining target mapping of a to-be-executed quantum program and a quantum computer, wherein the method comprises the following steps of: the method comprises the steps of obtaining a directed acyclic graph of a quantum program to be executed and an initial mapping relation between a logic bit and a physical bit, determining an execution sequence of a logic gate set to be mapped of the quantum program to be executed according to the directed acyclic graph of the quantum program to be executed, determining the cost of mapping each logic gate in the logic gate set to be mapped to a quantum chip topological structure according to the execution sequence and the initial mapping relation, adjusting target mapping of the quantum program to be executed according to the cost of mapping each logic gate to the quantum chip topological structure, so that the cost of the target mapping is the lowest, the problem that the quantum chip topological structure is affected due to a single physical bit factor is solved, and the optimal mapping line of the quantum chip topological structure can be determined, so that the resource utilization of the whole quantum chip is maximized.
Description
Technical Field
The invention belongs to the technical field of quantum computing, and particularly relates to a method and a device for determining target mapping of a to-be-executed quantum program and a quantum computer.
Background
Quantum computers are physical devices that perform high-speed mathematical and logical operations, store, and process quantum information following quantum mechanics laws. When a device processes and calculates quantum information and runs quantum algorithms, the device is a quantum computer. Quantum computers are a key technology under study because they have the ability to handle mathematical problems more efficiently than ordinary computers, for example, they can speed up the time to break RSA keys from hundreds of years to hours.
In a noise Intermediate-Scale Quantum computation (noise-Scale Quantum) stage, for a plurality of physical bits on the same physical chip, the states of the physical bits are unstable, and factors such as operation noise of a two-bit Quantum logic gate, measurement noise, and fading coherent time of the physical bits all interfere with effective utilization of the physical bits, thereby generating unknown influence on the operation result of the whole Quantum circuit.
For example, due to the different decoherence time of each physical bit, if the decoherence time of a certain physical bit is short and the operable depth of the quantum line of the whole quantum chip is limited, other physical bit resources are inevitably wasted. Therefore, how to determine the optimal mapping line of the quantum program to be executed so as to reduce the influence of a single physical bit on the whole quantum circuit and maximize the resource utilization of the whole quantum chip is a problem which needs to be solved urgently.
Disclosure of Invention
The invention aims to provide a method, a device and a quantum computer for determining target mapping of a to-be-executed quantum program, so as to solve the defects in the prior art, solve the problem that the whole quantum circuit is influenced by a single physical bit factor, and determine the optimal mapping circuit of a topological structure of a quantum chip, so that the resource utilization of the whole quantum chip is maximized.
One embodiment of the present application provides a method for determining target mapping of a quantum program to be executed, where the method includes:
acquiring a directed acyclic graph of a quantum program to be executed and an initial mapping relation between a logic bit and a physical bit;
determining an execution sequence of a set of logic gates to be mapped of the quantum program to be executed according to the directed acyclic graph of the quantum program to be executed;
respectively determining the cost of mapping each logic gate in the logic gate set to be mapped to a quantum chip topological structure according to the execution sequence and the initial mapping relation;
and adjusting the target mapping of the quantum program to be executed according to the cost of mapping each logic gate to the quantum chip topological structure, so that the cost of the target mapping is the lowest.
Optionally, the obtaining a directed acyclic graph of a to-be-executed quantum program includes:
acquiring nodes in a quantum program to be executed;
determining an incidence relation between the nodes according to the quantum bits of the node operation;
and generating a directed acyclic graph corresponding to the quantum program to be executed according to the nodes and the incidence relation among the nodes, wherein the vertexes in the directed acyclic graph represent the nodes, the edges in the directed acyclic graph represent the incidence relation among the nodes, and the directions of the edges represent the executed time sequence relation of the nodes corresponding to the vertexes connected with the edges.
Optionally, the set of logic gates to be mapped includes:
a first set of regular logic gates, wherein the first set of regular logic gates comprises: the single-bit quantum logic gate and the two-bit quantum logic gate with adjacent logic bits;
a second set of regular logic gates, wherein the second set of regular logic gates comprises: and the two-bit quantum logic gate with non-adjacent logic bits.
Optionally, the determining an execution order of the to-be-mapped logic gate set of the to-be-executed quantum program includes:
setting the execution sequence of a first regular logic gate set of a node with zero in-degree in the directed acyclic graph as a first priority and setting the execution sequence of a second regular logic gate set of the node with zero in-degree in the directed acyclic graph as a second priority according to the directed acyclic graph of the quantum program to be executed;
and deleting the first regular logic gate set of which the execution sequence is divided, continuously executing the step of setting the execution sequence of the first regular logic gate set of the node with zero degree in the directed acyclic graph as a first priority, and setting the execution sequence of the second regular logic gate set of the node with zero degree in the directed acyclic graph as a second priority until the execution sequence of the logic gate set to be mapped is divided.
Optionally, the determining the cost of mapping each logic gate in the to-be-mapped logic gate set to the quantum chip topology respectively includes:
respectively acquiring a mapping scheme of each logic gate mapped to a quantum chip topological structure according to the execution sequence and the initial mapping relation;
a cost formula for evaluating the mapping scheme is constructed and the cost of the mapping scheme is calculated.
Optionally, the adjusting, according to the cost of mapping each logic gate to the quantum chip topology, the target mapping of the quantum program to be executed so as to minimize the cost of the target mapping includes:
according to the quantum chip topological structure and the initial mapping relation, traversing and calculating the cost of each logic gate mapped to the quantum chip topological structure in the forward direction according to the execution sequence, and dynamically adjusting the mapping relation of the quantum program to be executed until the forward traversal according to the execution sequence is completed to obtain a target forward mapping relation;
according to the target forward mapping relation, reversely traversing and calculating the cost of each logic gate mapped to the quantum chip topological structure according to the execution sequence, and dynamically adjusting the mapping relation of the quantum program to be executed until the reverse traversal according to the execution sequence is completed to obtain a target reverse mapping relation;
and continuing to carry out forward and reverse alternate iterative mapping, and repeating the step of dynamically adjusting the mapping relation of the quantum program to be executed so as to minimize the cost of the target mapping.
Optionally, the evaluating the cost expression of the mapping scheme is:
wherein, T 2 De-coherence time, G, for a quantum chip bit swap The number f of swap logic gates required to be introduced for mapping all logic gates in the logic gate set to be mapped double For two-bit quantum logic gate fidelity, f measure To measure fidelity, a 1 、a 2 、a 3 、a 4 Is a preset weight coefficient of the cost expression.
One embodiment of the present application provides an apparatus for determining a target mapping of a quantum program to be executed, the apparatus comprising:
the acquisition module is used for acquiring a directed acyclic graph of the quantum program to be executed and an initial mapping relation between the logic bit and the physical bit;
the first determining module is used for determining the execution sequence of the logic gate set to be mapped of the quantum program to be executed according to the directed acyclic graph of the quantum program to be executed;
a second determining module, configured to respectively determine, according to the execution order and the initial mapping relationship, a cost of mapping each logic gate in the set of logic gates to be mapped to a quantum chip topology;
and the adjusting module is used for adjusting the target mapping of the quantum program to be executed according to the cost of mapping each logic gate to the quantum chip topological structure, so that the cost of the target mapping is the lowest.
Optionally, the obtaining module includes:
the acquisition unit is used for acquiring nodes in the quantum program to be executed;
a determining unit, configured to determine an association relationship between the nodes according to the qubits operated by the nodes;
and the generating unit is used for generating a directed acyclic graph corresponding to the to-be-executed quantum program according to the nodes and the incidence relation among the nodes, wherein vertexes in the directed acyclic graph represent the nodes, edges in the directed acyclic graph represent the incidence relation among the nodes, and the directions of the edges represent the executed time sequence relation of the nodes corresponding to the vertexes connected with the edges.
Optionally, the first determining module includes:
the dividing unit is used for setting the execution sequence of a first regular logic gate set of a node with zero degree of income in the directed acyclic graph as a first priority and setting the execution sequence of a second regular logic gate set of the node with zero degree of income in the directed acyclic graph as a second priority according to the directed acyclic graph of the quantum program to be executed;
and the iteration unit is used for deleting the first regular logic gate set of which the execution sequence is divided, continuously executing the step of setting the execution sequence of the first regular logic gate set of the node with zero degree of income in the directed acyclic graph as a first priority, and setting the execution sequence of the second regular logic gate set of the node with zero degree of income in the directed acyclic graph as a second priority until the execution sequence of the logic gate set to be mapped is divided.
Optionally, the second determining module includes:
the mapping unit is used for respectively acquiring a mapping scheme of each logic gate mapped to a quantum chip topological structure according to the execution sequence and the initial mapping relation;
and the evaluation unit is used for constructing a cost formula for evaluating the mapping scheme and calculating the cost of the mapping scheme.
Optionally, the adjusting module includes:
the forward traversing unit is used for forward traversing and calculating the cost of each logic gate mapped to the quantum chip topological structure according to the execution sequence according to the quantum chip topological structure and the initial mapping relation, and dynamically adjusting the mapping relation of the quantum program to be executed until the forward traversing is completed according to the execution sequence to obtain a target forward mapping relation;
the backward traversal unit is used for performing backward traversal according to the execution sequence and calculating the cost of each logic gate mapped to the quantum chip topological structure according to the target forward mapping relation, and dynamically adjusting the mapping relation of the quantum program to be executed until the backward traversal according to the execution sequence is completed to obtain a target backward mapping relation;
and the adjusting unit is used for continuing forward and reverse alternate iterative mapping and repeating the step of dynamically adjusting the mapping relation of the quantum program to be executed so as to ensure that the cost of the target mapping is the lowest.
A further embodiment of the application provides a storage medium having a computer program stored thereon, wherein the computer program is arranged to perform the method of any of the above when executed.
Yet another embodiment of the present application provides an electronic device comprising a memory having a computer program stored therein and a processor configured to execute the computer program to perform the method of any of the above.
Yet another embodiment of the present application provides a quantum computer operating system that enables determination of a target mapping of a quantum program to be executed according to the method described in any of the above.
Yet another embodiment of the present application provides a quantum computer comprising the quantum computer operating system.
Compared with the prior art, the method includes the steps of firstly obtaining a directed acyclic graph of the quantum program to be executed and an initial mapping relation between logic bits and physical bits, determining an execution sequence of a set of logic gates to be mapped of the quantum program to be executed according to the directed acyclic graph of the quantum program to be executed, respectively determining the cost of each logic gate in the set of logic gates to be mapped to a quantum chip topological structure according to the execution sequence and the initial mapping relation, adjusting target mapping of the quantum program to be executed according to the cost of each logic gate mapped to the quantum chip topological structure, so that the cost of the target mapping is the lowest, solving the problem that influence is caused on the quantum circuit due to a single physical bit factor, determining the optimal mapping circuit of the quantum chip topological structure, and maximizing resource utilization of the whole quantum chip.
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Fig. 1 is a block diagram of a hardware structure of a computer terminal for executing a method for determining quantum program target mapping according to an embodiment of the present invention;
fig. 2 is a schematic flowchart of a method for determining target mapping of a to-be-executed quantum program according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a topology structure of a physical bit of a quantum chip according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a quantum circuit to be executed according to an embodiment of the present invention;
FIG. 5 is a diagram of a directed acyclic graph corresponding to a to-be-executed quantum line according to an embodiment of the present invention;
FIG. 6 is a diagram of another quantum circuit to be implemented according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of an apparatus for determining target mapping of a to-be-executed quantum program according to an embodiment of the present invention.
Detailed Description
The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention and are not to be construed as limiting the present invention.
The embodiment of the invention firstly provides a method for determining target mapping of a to-be-executed quantum program, and the method can be applied to electronic equipment, such as a computer terminal, specifically a common computer, a quantum computer and the like.
The following description will be made in detail by taking the example of the operation on a computer terminal. Fig. 1 is a block diagram of a hardware structure of a computer terminal for executing a method for determining quantum program target mapping according to an embodiment of the present invention. As shown in fig. 1, the computer terminal may include one or more (only one shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, and optionally, a transmission device 106 for communication functions and an input-output device 108. It will be understood by those skilled in the art that the structure shown in fig. 1 is only an illustration and is not intended to limit the structure of the computer terminal. For example, the computer terminal may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.
The memory 104 may be used to store software programs and modules of application software, such as program instructions/modules corresponding to the determination method for implementing a quantum program target mapping to be executed in the embodiment of the present application, and the processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, implementing the above-described method. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 can further include memory located remotely from the processor 102, which can be connected to a computer terminal over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission device 106 is used for receiving or transmitting data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the computer terminal. In one example, the transmission device 106 includes a Network adapter (NIC) that can be connected to other Network devices through a base station to communicate with the internet. In one example, the transmission device 106 can be a Radio Frequency (RF) module, which is used to communicate with the internet in a wireless manner.
It should be noted that a true quantum computer is a hybrid structure, which includes two major components: one part is a classic computer which is responsible for executing classic calculation and control; the other part is quantum equipment which is responsible for running a quantum program to further realize quantum computation. The quantum program is a string of instruction sequences which can run on a quantum computer and are written by a quantum language such as a Qrun language, so that the support of the operation of the quantum logic gate is realized, and the quantum computation is finally realized. In particular, a quantum program is a sequence of instructions that operate quantum logic gates in a time sequence.
In practical applications, due to the development of hardware limited to quantum devices, quantum computation simulation is usually required to verify quantum algorithms, quantum applications, and the like. The quantum computing simulation is a process of realizing the simulation operation of a quantum program corresponding to a specific problem by means of a virtual architecture (namely a quantum virtual machine) built by resources of a common computer. In general, it is necessary to build quantum programs for a particular problem. The quantum program referred in the embodiment of the invention is a program written in a classical language for representing quantum bits and evolution thereof, wherein the quantum bits, quantum logic gates and the like related to quantum computation are all represented by corresponding classical codes.
A quantum circuit, which is an embodiment of a quantum program and also a weighing sub-logic circuit, is the most common general quantum computation model, and represents a circuit that operates on a quantum bit under an abstract concept, and the circuit includes the quantum bit, a circuit (timeline), and various quantum logic gates, and finally, a result is often read through a quantum measurement operation.
Unlike conventional circuits that are connected by metal lines to pass either voltage or current signals, in quantum circuits, the lines can be viewed as being connected by time, i.e., the state of a qubit evolves naturally over time, in the process being operated on as indicated by the hamiltonian until a logic gate is encountered.
The quantum program refers to the total quantum circuit, wherein the total number of the quantum bits in the total quantum circuit is the same as the total number of the quantum bits of the quantum program. It can be understood that: a quantum program may consist of quantum wires, measurement operations for quantum bits in the quantum wires, registers to hold measurement results, and control flow nodes (jump instructions), and a quantum wire may contain tens to hundreds or even thousands of quantum logic gate operations. The execution process of the quantum program is a process executed for all the quantum logic gates according to a certain time sequence. It should be noted that timing is the time sequence in which the single quantum logic gate is executed.
It should be noted that in the classical calculation, the most basic unit is a bit, and the most basic control mode is a logic gate, and the purpose of the control circuit can be achieved through the combination of the logic gates. Similarly, the way qubits are handled is quantum logic gates. The quantum state can be evolved by using quantum logic gates, which are the basis for forming quantum circuits, including single-bit quantum logic gates, such as Hadamard gates (H gates, hadamard gates), pauli-X gates (X gates), pauli-Y gates (Y gates), pauli-Z gates (Z gates), RX gates, RY gates, RZ gates, and the like; multi-bit quantum logic gates such as CNOT gates, CR gates, iSWAP gates, toffoli gates, and the like. Quantum logic gates are typically represented using unitary matrices, which are not only matrix-form but also an operation and transformation. The function of a general quantum logic gate on a quantum state is calculated by multiplying a unitary matrix by a matrix corresponding to a quantum state right vector.
The quantum states, i.e. the logical states of qubits, are represented in binary in quantum arithmetic (or quantum program), for example, a group of qubits is q0, q1, q2, representing 0 th, 1 st, and 2 nd qubits, and are ordered from high to low as q2q1q0, the quantum states corresponding to the group of qubits are the superposition of the eigenstates corresponding to the group of qubits, and the eigenstates corresponding to the group of qubits total 2 quanta total power, i.e. 8 eigenstates (deterministic states): the method comprises the following steps of |000>, |001>, |010>, |011>, |100>, |101>, |110>, |111>, the bit of each eigenstate corresponds to the qubit, for example, |000> state, the high position to the low position of 000 correspond to q2q1q0, and | is a Dirac symbol.
Describing, in a single qubit, the logic state of a single qubit
May be at |0>State, |1>State, |0>Sum of states |1>The superimposed state of states (indeterminate state) can be expressed in particular as @>
Wherein c and d areComplex number representing amplitude (probability amplitude) of quantum state, square c of amplitude 2 And d 2 Respectively represent |0>State, |1>The probability of state, | c- 2 +|d| 2 And =1. In short, a quantum state is a superposition of the eigenstates, and is in a uniquely determined eigenstate when the probability of the other eigenstates is 0.
Referring to fig. 2, fig. 2 is a schematic flowchart of a method for determining target mapping of a to-be-executed quantum program according to an embodiment of the present invention.
The present embodiment provides an embodiment of a method for determining target mapping of a to-be-executed quantum program, where the method for determining target mapping of a to-be-executed quantum program includes:
s201: and acquiring a directed acyclic graph of the quantum program to be executed and an initial mapping relation between the logic bit and the physical bit.
In particular, the quantum program to be executed is mainly composed of tens to hundreds or even thousands of quantum logic gates. The execution process of the quantum program is a process executed on all the quantum logic gates according to a certain time sequence, and it should be noted that the time sequence is a time sequence in which a single quantum logic gate is executed.
For the sake of distinction, the qubit structure in a quantum chip is generally referred to as a physical bit, and the subject bit operated on in a quantum wire is referred to as a logical bit. The initial mapping relationship between the logical bits and the physical bits refers to the relationship of "corresponding" between the logical bits and the physical bits.
Illustratively, referring to fig. 3, fig. 3 is a schematic diagram of a topology of physical bits of a quantum chip according to an embodiment of the present invention, where the quantum chip includes 8 physical bits, i.e., Q [0], Q [1], Q [2], Q [3], Q [4], Q [5], Q [6], and Q [7], and the 8 physical bits can be coupled through capacitors and only have a coupling relationship between adjacent physical bits. Wherein Q0 is connected to Q1 and Q4, Q5 is connected to Q1, Q4 and Q6, Q2 is connected to Q1, Q6 and Q3, and Q7 is connected to Q3 and Q6.
Illustratively, for a quantum program CNOT (Q [0], Q [1 ]) < < CNOT (Q [2], Q [4 ]) < < CNOT (Q [2], Q [3 ]) < < CNOT (Q [0], Q [2 ]) < < CNOT (Q [2], Q [4 ]) < < CNOT (Q [1], Q [4 ]) < < CNOT (Q [0], Q [1 ]) < < CNOT (Q [1 ]), and the logical bits of the operation are Q [0], Q [1], Q [2], Q [3], Q [4], respectively, the initial mapping relationship between the logical bits and the physical bits can be set as Q [0] to Q [0], Q [1 to Q [1], Q [2 to Q [2], Q [3 to Q [3], Q [4 to Q [4], and so on.
A directed acyclic graph (DAG graph) is a directed graph, the literal meaning is that the graph has no rings and is an acyclic directed graph, and if the directed graph has a non-directed acyclic graph, the directed graph can return to the point A from the point A to the point B through the point C, and then a ring is formed. If the direction from the point C to the point A is changed to the direction from the point A to the point C, the direction becomes a directed acyclic graph which is often used for representing the driving dependency relationship among events, the scheduling among tasks and the like.
The method for obtaining the directed acyclic graph of the quantum program to be executed specifically comprises the following steps:
s2011: and acquiring nodes in the quantum program to be executed.
In particular, a quantum program is understood to be a sequence of operations, which mainly comprises quantum logic gates, measurement operations (measures), etc. The node in the quantum program refers to data having a specific structure in a relative position of the entire program, and may be a quantum logic gate, a Measure operation (Measure), or the like.
Specifically, quantum logic gate nodes in the quantum program can be obtained by traversing the nodes of the quantum program.
For example, referring to fig. 4, fig. 4 is a schematic diagram of a to-be-executed quantum circuit according to an embodiment of the present invention, it can be understood that a quantum program corresponds to a total quantum circuit as a whole, and the to-be-executed quantum program according to the embodiment of the present invention refers to the total quantum circuit. Wherein, the quantum program to be executed is CNOT (q [0], q [1 ]) < < CNOT (q [2], q [4 ]) <CNOT (q [2], q [3 ]) <CNOT (q [0], q [2 ]) <CNOT (q [2], q [4 ]) <CNOT (q [1], q [4 ]) <CNOT (q [0], q [1 ]), and the nodes 1 to 7 in the quantum program to be executed are CNOT (q [0], q [1 ]), CNOT (q [2], q [4 ]), CNOT (q [2], q [3 ]), CNOT (q [0], q [2 ]), CNOT (q [2], q [4 ]), CNOT (q [1], q [4 ]), CNOT (q [0], q [1 ]).
S2012: and determining the incidence relation between the nodes according to the quantum bits operated by the nodes.
Specifically, for each quantum operation node, a next node of the node is determined from all quantum operation nodes sequentially executed by the qubit of the node operation, and an adjacent relationship between the node and the next node is obtained.
Specifically, in the process of traversing the nodes of the quantum wires, the sequence number and the unique identifier of the quantum bit of the currently traversed node operation are recorded, so as to update the last node corresponding to each bit in the traversal process. And recording the information of the last node corresponding to each bit and the currently traversed node and the adjacent relation between the last node and the currently traversed node. And the last node corresponding to the quantum bit refers to a precursor node of the currently traversed node of the quantum logic gate.
It should be noted that the unique identifier of the quantum logic gate is marked according to the execution time sequence of the quantum logic gate.
For example, as shown in fig. 4, a to-be-executed quantum circuit diagram is first to traverse nodes of a quantum program in sequence according to quantum bits of node operation. Starting from the first layer of the quantum wire, CNOT (q 0, q 1) is traversed, the sequence numbers of the quantum bits of CNOT gate operation are 0 and 1, and the unique identifier is '1'; CNOT (q 2, q 4), the quantum bit serial numbers of CNOT gate operation are 2 and 4, the unique identifier is "2", and no predecessor node exists in the current first layer CNOT gate.
When traversing to the beginning of the second layer of quantum wires, i.e., traversing to node CNOT (q 2, q 3), the quantum bit sequence numbers of CNOT gate operation are 2 and 3, the unique identifier is 3, and at this time, the predecessor node of CNOT (q 2, q 3) is CNOT (q 2, q 4), the adjacency relation between bits is recorded, which is recorded in the form of unique identifier, which can be marked as {2,3}, indicating that node 2 and node 3 are adjacent. Then, sequentially traversing to CNOT (q 0, q 2) of the third layer, CNOT (q 2, q 4) of the fourth layer, CNOT (q 1, q 4) of the fifth layer, CNOT (q 0, q 1) of the sixth layer, obtaining quantum bit of each layer of node operation, determining association relation between nodes, and processing flow is the same, and is not repeated herein.
S2013: and generating a directed acyclic graph corresponding to the quantum program to be executed according to the nodes and the incidence relation among the nodes, wherein the vertexes in the directed acyclic graph represent the nodes, the edges in the directed acyclic graph represent the incidence relation among the nodes, and the directions of the edges represent the executed time sequence relation of the nodes corresponding to the vertexes connected with the edges.
Referring to fig. 5, fig. 5 is a schematic diagram of a to-be-executed quantum line corresponding directed acyclic graph according to an embodiment of the present invention. Specifically, a vertex corresponding to the quantum operation node is constructed, an edge between the vertices corresponding to the nodes having the adjacent relationship is constructed, wherein the direction of the edge is pointed to the vertex corresponding to the next node by the vertex corresponding to the previous node in the nodes having the adjacent relationship, and then the directed acyclic graph corresponding to the to-be-executed quantum program is generated according to the nodes and the association relationship between the nodes.
S202: and determining the execution sequence of the logic gate set to be mapped of the quantum program to be executed according to the directed acyclic graph of the quantum program to be executed.
It should be noted that the set of logic gates to be mapped includes a first set of regular logic gates, where the first set of regular logic gates includes: the single-bit quantum logic gate and the two-bit quantum logic gate with adjacent logic bits; a second set of regular logic gates, wherein the second set of regular logic gates comprises: and the two-bit quantum logic gate with non-adjacent logic bits.
Specifically, whether the bits of the two-bit qubit logic gate are adjacent or not can be determined by using the distance between two corresponding qubits operated by the two-bit qubit logic gate, wherein the distance between the two qubits can be represented by the number of spaced qubits between the two qubits. As shown in FIG. 3, qubits Q [0] and Q [1] are separated by 0 qubits, whose distance can be represented as 0; qubits Q1 and Q3 are separated by 1 qubit, whose distance can be expressed as 1; qubits Q0 and Q3 are separated by 2 qubits, and their distance can be expressed as 2. Thus, by determining whether the distance between two qubits is 0, it can be determined whether the bits of the two-bit qubit logic gate are adjacent.
The determining the execution order of the logic gate sets to be mapped of the quantum programs to be executed includes:
setting the execution sequence of a first regular logic gate set of a node with zero in-degree in the directed acyclic graph as a first priority, and setting the execution sequence of a second regular logic gate set of the node with zero in-degree in the directed acyclic graph as a second priority according to the directed acyclic graph of the quantum program to be executed.
It should be noted that the quantum program to be executed may include a single-bit quantum logic gate, a two-bit quantum logic gate, and a multi-bit quantum logic gate, but before determining the execution order of the set of logic gates to be mapped of the quantum program to be executed, the multi-bit quantum logic gate needs to be first converted into a combination of the single-bit quantum logic gate and the two-bit quantum logic gate. Because the single-bit quantum logic gate can directly map the logic bit to the physical bit, the single-bit quantum logic gate obtained after conversion and the single-bit quantum logic gate existing in the quantum program to be executed before conversion can be deleted (or preferentially executed), and then the directed acyclic graph of the quantum program to be executed is constructed based on the two-bit quantum logic gate obtained after conversion and the two-bit quantum logic gate existing in the quantum program to be executed before conversion. For convenience of explanation, a directed acyclic graph including two-bit quantum logic gates is used as an example.
Exemplarily, referring to fig. 5, fig. 5 is a schematic diagram of a to-be-executed quantum circuit corresponding to a directed acyclic graph according to an embodiment of the present invention, according to the directed acyclic graph shown in fig. 5, nodes with zero in-degree are CNOT (q 0, q 1) and CNOT (q 2, q 4), respectively, where logic bits of CNOT (q 0, q 1) operations are adjacent and are first regular logic gates, and therefore, an execution order thereof is set as a first priority; where the logic bits of the CNOT (q 2, q 4) operation are not adjacent, are the second regular logic gates, and thus their execution order is set to the second priority.
And deleting the first regular logic gate set of which the execution sequence is divided, continuously executing the step of setting the execution sequence of the first regular logic gate set of the node with zero degree in the directed acyclic graph as a first priority, and setting the execution sequence of the second regular logic gate set of the node with zero degree in the directed acyclic graph as a second priority until the execution sequence of the logic gate set to be mapped is divided.
Specifically, as described in the above example, since the first regular logic gate set does not affect the resource utilization rate of the entire quantum line during the operation process, and can be directly executed, in the process of dividing the execution order, the first regular logic gate set whose execution order is divided, that is, CNOT (q [0], q [1 ]), may be deleted, the step of setting the execution order of the first regular logic gate set of the nodes whose introductivity is zero in the directed acyclic graph as the first priority and setting the execution order of the second regular logic gate set of the nodes whose introductivity is zero in the directed acyclic graph as the second priority may be continuously executed. And finally, completing the execution sequence division, wherein the logic gate set of the first priority comprises: CNOT (q 0, q 1), CNOT (q 2, q 3) and CNOT (q 0, q 1); the set of logic gates of the second priority comprises: CNOT (q 2, q 4), CNOT (q 0, q 2), CNOT (q 2, q 4) and CNOT (q 1, q 4).
S203: and respectively determining the cost of mapping each logic gate in the logic gate set to be mapped to the quantum chip topological structure according to the execution sequence and the initial mapping relation.
Specifically, the cost of each logic gate mapping to the quantum chip topology can be divided into a fixed cost and a switching cost. Wherein, the fixed cost may include the decoherence time, fidelity, etc. of the quantum chip bit; the switching cost comprises the number of swap logic gates required to be introduced for mapping all logic gates in the logic gate set to be mapped. Since the fixed cost of the quantum chip in the process of operating the quantum circuit is determined by the physical characteristics of the chip, the quantum chip can be described by taking only the exchange cost of operating the quantum circuit in the quantum chip as an example.
Respectively determining the cost of each logic gate in the logic gate set to be mapped to the quantum chip topological structure according to the execution sequence and the initial mapping relation, wherein the cost comprises the following steps:
and 1, respectively acquiring a mapping scheme of each logic gate mapped to a quantum chip topological structure according to the execution sequence and the initial mapping relation.
Specifically, a quantum line to be executed is first converted into a directed acyclic graph structure, and then a node with zero in-degree is selected from the corresponding directed acyclic graph, which can be recorded as an operation layer to represent the current quantum logic gate operation to be executed. An iterative loop process follows: judging whether the operation layer is empty, if so, indicating that the mapping of the whole quantum line to be executed is finished, and finishing the mapping; if the operation layer is not empty, a logic gate which can be directly executed is searched from the operation layer, the logic gate which can be directly executed represents the logic gate which directly maps the logic bit to the physical bit without introducing any swap logic gate operation according to the current mapping relation; if the logic gate which can be directly executed exists in the operation layer, the logic gate which can be directly executed is deleted from the operation layer, then the operation layer is updated according to the logic gate of the latter item of the logic gate which can be directly executed, and the loop returns to the loop starting position, and the second iteration loop is started; if no logic gate capable of being directly executed exists in the operation layer, it is indicated that the logic gate in the operation layer cannot be mapped under the current mapping condition, at this time, swap logic gate operation needs to be introduced, and the purpose of introducing the swap logic gate is to change the mapping relation and realize quantum state transfer, so as to improve the current mapping environment.
Illustratively, referring to the directed acyclic graph shown in fig. 5, firstly, the nodes of the quantum logic gates to be executed currently in the operation layer are determined to be CNOT (q [0], q [1 ]) and CNOT (q [2], q [4 ]), respectively, the logic gates that can be executed directly, i.e., CNOT (q [0], q [1 ]) are searched from the nodes, CNOT (q [0], q [1 ]) is deleted from the operation layer, and then the operation layer is updated according to the consequent logic gates CNOT (q [0], q [2 ]), CNOT (q [1], q [4 ]) of the directly executable logic gates CNOT (q [0], q [1 ]), CNOT (q [1 ]), which are all out of 0 degrees, so that the operation layer cannot be updated temporarily, i.e., the current operation layer is still CNOT (q [2], q [4 ]), and the loop start position is returned to the above, and the mapping relationship between the current operation layer and the current environment of the current operation layer can be performed dynamically and the quantum logic gates can be improved.
Illustratively, according to the initial mapping relationships Q [0] - -Q [0], Q [1] - -Q [1], Q [2] - -Q [2], Q [3] - -Q [3], Q [4] - -Q [4], if CNOT (Q [2], Q [4 ]) is to be executed, there are various schemes for introducing swap logic gates, such as: through inserting swap logic gate between Q4 and Q0, and then inserting swap logic gate between Q0 and Q1, mapping logic bit Q4 to physical bit Q1, achieving the purpose of executing CNOT (Q2, Q4), the mapping relations at this time are Q0-Q4, Q1-Q0, Q2-Q2, Q3-Q3, Q4-Q1; or through inserting swap logic gate between Q2 and Q1, and then through inserting swap logic gate between Q0 and Q1, mapping logic bit Q2 to physical bit Q0, and also achieving the purpose of executing CNOT (Q2, Q4), the mapping relations at this time are Q0-Q1, Q1-Q2, Q2-Q0, Q3-Q3, Q4-Q4; it should be noted that, the logic gates of the operation layer are all nodes with zero in-degree, and there are many mapping schemes for implementing CNOT (q 2, q 4), which are not exhaustive, but in the practical application of the present application, all swap insertion schemes that are feasible need to be searched, and then the final target mapping is determined by evaluating different costs of each mapping scheme.
2, constructing a cost formula for evaluating the mapping scheme and calculating the cost of the mapping scheme.
Alternatively, the cost formula of the mapping scheme may be constructed:
evaluating each by the above cost formulaAnd the cost of the mapping scheme comprehensively considers factors in multiple aspects such as the shortest path, the fidelity of a two-bit quantum logic gate, the fidelity of measurement, the decoherence time and the like, then the final consumption cost of each swap scheme is obtained through weighted summation, and the swap logic gate insertion scheme with the minimum consumption cost is finally selected to update the current mapping. And then returning to the operation layer to judge whether logic gates capable of being directly executed exist, and repeating the steps until all logic gates in the whole quantum line to be executed are mapped to physical bits of the quantum chip topological structure. Wherein, T 2 De-coherence time, G, for a quantum chip bit swap The number f of swap logic gates required to be introduced for mapping all logic gates in the logic gate set to be mapped double For two-bit quantum logic gate fidelity, f measure To measure fidelity, a 1 、a 2 、a 3 、a 4 Is a preset weight coefficient of the cost expression.
S204: and adjusting the target mapping of the quantum program to be executed according to the cost of mapping each logic gate to the topological structure of the quantum chip so as to ensure that the cost of the target mapping is the lowest.
Specifically, according to the quantum chip topological structure and the initial mapping relation, traversing and calculating the cost of each logic gate mapped to the quantum chip topological structure in the forward direction according to the execution sequence, and dynamically adjusting the mapping relation of the quantum program to be executed until the forward traversal according to the execution sequence is completed to obtain a target forward mapping relation;
according to the target forward mapping relation, reversely traversing and calculating the cost of each logic gate mapped to the quantum chip topological structure according to the execution sequence, and dynamically adjusting the mapping relation of the quantum program to be executed until the reverse traversal according to the execution sequence is completed to obtain a target reverse mapping relation;
and continuing to carry out forward and reverse alternate iterative mapping, and repeating the step of dynamically adjusting the mapping relation of the quantum program to be executed so as to minimize the cost of the target mapping.
Illustratively, referring to FIG. 6, FIG. 6 is a diagram of another to-be-executed quantum circuit provided by the embodiment of the present invention, according to the initial mapping relationships Q [0] - -Q [0], Q [1] - -Q [1], Q [2] - -Q [2], Q [3] - -Q [3], Q [4] - -Q [4], CNOT (Q [0], Q [1 ]), CNOT (Q [2], Q [4 ]), CNOT (Q [0], Q [2 ]), CNOT (Q [2], Q [4 ]), CNOT (Q [1], Q [3 ]) are traversed forward in the execution sequence. Firstly, traversing CNOT (q 0, q 1) in forward direction according to the execution sequence, and the current mapping relation is not changed because the logic bits are adjacent; when traversing to CNOT (q [2], q [4 ]), in one possible approach: mapping the logic bit Q4 to the physical bit Q1 by inserting swap logic gate between Q4 and Q0, and then inserting swap logic gate between Q0 and Q1, so as to achieve the purpose of performing CNOT (Q2, Q4), the mapping relations at this time are Q0-Q4, Q1-Q0, Q2-Q2, Q3-Q3, Q4-Q1; continuously traversing to CNOT (Q [0], Q [2 ]), and based on the current mapping relation, realizing mapping of the logical bit Q [2] to the physical bit Q [3] by inserting a swap logic gate in Q [2] and Q [3], so as to achieve the purpose of executing CNOT (Q [0], Q [2 ]), wherein the mapping relation at the moment is Q [0] - -Q [4], Q [1] - -Q [0], Q [3] - -Q [2], Q [2] - -Q [3], Q [4] - -Q [1]; continuously traversing to CNOT (Q2, Q4), based on the current mapping relation, realizing mapping of the logical bit Q2 to the physical bit Q2 by inserting swap logic gates in Q2 and Q3, and achieving the purpose of performing CNOT (Q2, Q4), wherein the mapping relation at this time is Q [0] -Q4, Q [1] -Q0, Q [2] -Q2, Q [3] -Q [3], Q [4] -Q1; and continuously traversing to CNOT (Q [1], Q [3 ]), and based on the current mapping relation, mapping the logic bit Q [3] to the physical bit Q [1] by inserting a swap logic gate in Q [2] and Q [3] and then inserting the swap logic gate between Q [1] and Q [2], and also achieving the purpose of executing CNOT (Q [1], Q [3 ]), wherein the obtained target forward mapping relation is Q [0] -Q [4], Q [1] -Q [0], Q [4] -Q [2], Q [2] -Q [3], and Q [3] -Q [1].
At this time, the target forward mapping relations are Q [0] - -Q [4], Q [1] - -Q [0], Q [4] - -Q [2], Q [2] - -Q [3], Q [3] - -Q [1], CNOT (Q [1], Q [3 ]), CNOT (Q [2], Q [4 ]), CNOT (Q [0], Q [2 ]), CNOT (Q [2], Q [4 ]), CNOT (Q [0], Q [1 ]) are reversely traversed according to the execution sequence, the cost of each logic gate mapped to the quantum chip topology is calculated, the mapping relation of the to-be-executed quantum program is dynamically adjusted, for example, the physical bits mapped under the current target forward mapping relation by CNOT (Q [1], Q [3 ]) are adjusted, then the last mapping relation, namely the current target forward mapping relation, and the physical reverse bits mapped under the last mapping relation of each logic gate are continuously adjusted until the target reverse mapping relation is obtained after the target forward mapping relation is traversed according to the execution sequence, namely: q < 0> -Q < 4 >, Q < 1> -Q < 0>, Q < 4 > -Q < 2 >, Q < 2 > -Q < 3 >, Q < 3 > -Q < 1 >.
Then continuing to carry out forward and reverse alternate iterative mapping, repeating the step of dynamically adjusting the mapping relation of the quantum program to be executed, and according to a cost formula:
and calculating the mapping cost of each mapping scheme to minimize the cost of the target mapping.
It should be noted that, multiple schemes of introducing swap logic gates may exist between two non-adjacent bits, but the fidelity, noise, etc. of each scheme are different, and only the scheme with a small number of swap logic gates and high fidelity is selected to be introduced, the execution accuracy of the quantum circuit to be executed can be effectively ensured, and if in the mapping process, the logic bits with less operation can be mapped to the physical bits with shorter decoherence time, the maximization of the resource utilization of the physical bits can be realized, and the operation accuracy of the quantum circuit is also improved. Therefore, by presetting a weight coefficient, the quantum line execution accuracy can be effectively ensured by selecting the logic bits with high fidelity, introducing a small number of swap logic gates and mapping the logic bits with less operation to the physical bits with shorter decoherence time.
For the whole mapping algorithm, forward sequence mapping and reverse sequence mapping can be performed twice on quantum lines to be executed, and the method is a two-way heuristic mapping algorithm idea. The quantum line mapping problem is an NP-hard problem in a high-bit and high-depth measuring sub-line scene, so that the possibility of finding an optimal solution in the high-bit and high-depth measuring sub-line scene is extremely low, and a bidirectional heuristic mapping algorithm is a mainstream idea for solving the problem. The main method of the bidirectional heuristic mapping algorithm is to give an initial mapping relation at random, then gradually perform iterative optimization, and approach the optimal solution continuously, wherein theoretically, the more the iteration times, the better the optimization effect. The initial mapping determines the starting point of the algorithm optimization, so that a limited number of iterations are possible under the condition of comprehensively considering the time cost, and the initial mapping has a great influence on the result of the final mapping. However, based on the prior art, an initial mapping which is considered globally cannot be given, so that global logic gate information in the whole quantum circuit to be executed can be considered comprehensively through forward mapping and reverse mapping, forward traversal mapping is performed through random mapping to obtain a target forward mapping relation, then reverse traversal mapping is performed through the target forward mapping relation again to update the initial mapping, and forward and reverse alternate iterative mapping or limited forward and reverse alternate iterative mapping is performed continuously to minimize the cost of the target mapping.
Compared with the prior art, the method includes the steps of firstly obtaining a directed acyclic graph of the quantum program to be executed and an initial mapping relation between logic bits and physical bits, determining an execution sequence of a set of logic gates to be mapped of the quantum program to be executed according to the directed acyclic graph of the quantum program to be executed, respectively determining the cost of each logic gate in the set of logic gates to be mapped to a quantum chip topological structure according to the execution sequence and the initial mapping relation, adjusting target mapping of the quantum program to be executed according to the cost of each logic gate mapped to the quantum chip topological structure, so that the cost of the target mapping is the lowest, solving the problem that influence is caused on the quantum circuit due to a single physical bit factor, determining the optimal mapping circuit of the quantum chip topological structure, and maximizing resource utilization of the whole quantum chip.
Referring to fig. 7, fig. 7 is a schematic structural diagram of an apparatus for determining target mapping of a to-be-executed quantum program according to an embodiment of the present invention, which corresponds to the flow shown in fig. 2, and the apparatus may include:
an obtaining module 701, configured to obtain a directed acyclic graph of a to-be-executed quantum program and an initial mapping relationship between a logic bit and a physical bit;
a first determining module 702, configured to determine, according to the directed acyclic graph of the to-be-executed quantum program, an execution order of a to-be-mapped logic gate set of the to-be-executed quantum program;
a second determining module 703, configured to respectively determine, according to the execution order and the initial mapping relationship, a cost of mapping each logic gate in the set of logic gates to be mapped to a quantum chip topology;
an adjusting module 704, configured to adjust a target mapping of the quantum program to be executed according to a cost of mapping each logic gate to the quantum chip topology, so as to minimize the cost of the target mapping.
Specifically, the obtaining module includes:
the acquisition unit is used for acquiring nodes in the quantum program to be executed;
a determining unit, configured to determine an association relationship between the nodes according to the qubits operated by the nodes;
and the generating unit is used for generating a directed acyclic graph corresponding to the to-be-executed quantum program according to the nodes and the incidence relation among the nodes, wherein vertexes in the directed acyclic graph represent the nodes, edges in the directed acyclic graph represent the incidence relation among the nodes, and the directions of the edges represent the executed time sequence relation of the nodes corresponding to the vertexes connected with the edges.
Specifically, the first determining module includes:
the dividing unit is used for setting the execution sequence of a first regular logic gate set of a node with zero degree of income in the directed acyclic graph as a first priority and setting the execution sequence of a second regular logic gate set of the node with zero degree of income in the directed acyclic graph as a second priority according to the directed acyclic graph of the quantum program to be executed;
and the iteration unit is used for deleting the first regular logic gate set of which the execution sequence is divided, continuously executing the step of setting the execution sequence of the first regular logic gate set of the node with zero in-degree in the directed acyclic graph as a first priority, and setting the execution sequence of the second regular logic gate set of the node with zero in-degree in the directed acyclic graph as a second priority until the execution sequence of the logic gate set to be mapped is divided.
Specifically, the second determining module includes:
the mapping unit is used for respectively acquiring a mapping scheme of each logic gate mapped to a quantum chip topological structure according to the execution sequence and the initial mapping relation;
and the evaluation unit is used for constructing a cost formula for evaluating the mapping scheme and calculating the cost of the mapping scheme.
Specifically, the adjusting module includes:
the forward traversing unit is used for forward traversing and calculating the cost of each logic gate mapped to the quantum chip topological structure according to the execution sequence according to the quantum chip topological structure and the initial mapping relation, and dynamically adjusting the mapping relation of the quantum program to be executed until the forward traversing is completed according to the execution sequence to obtain a target forward mapping relation;
the backward traversal unit is used for performing backward traversal according to the execution sequence and calculating the cost of each logic gate mapped to the quantum chip topological structure according to the target forward mapping relation, and dynamically adjusting the mapping relation of the quantum program to be executed until the backward traversal according to the execution sequence is completed to obtain a target backward mapping relation;
and the adjusting unit is used for continuing forward and reverse alternate iterative mapping and repeating the step of dynamically adjusting the mapping relation of the quantum program to be executed so as to ensure that the cost of the target mapping is the lowest.
Compared with the prior art, the method includes the steps of firstly obtaining a directed acyclic graph of the quantum program to be executed and an initial mapping relation between logic bits and physical bits, determining an execution sequence of a set of logic gates to be mapped of the quantum program to be executed according to the directed acyclic graph of the quantum program to be executed, respectively determining the cost of each logic gate in the set of logic gates to be mapped to a quantum chip topological structure according to the execution sequence and the initial mapping relation, adjusting target mapping of the quantum program to be executed according to the cost of each logic gate mapped to the quantum chip topological structure, so that the cost of the target mapping is the lowest, solving the problem that influence is caused on the quantum circuit due to a single physical bit factor, determining the optimal mapping circuit of the quantum chip topological structure, and maximizing resource utilization of the whole quantum chip.
An embodiment of the present invention further provides a storage medium, where a computer program is stored in the storage medium, where the computer program is configured to, when executed, perform the steps in any one of the above method embodiments.
Specifically, in the present embodiment, the storage medium may be configured to store a computer program for executing the steps of:
s201: acquiring a directed acyclic graph of a quantum program to be executed and an initial mapping relation between a logic bit and a physical bit;
s202: determining an execution sequence of a set of logic gates to be mapped of the quantum program to be executed according to the directed acyclic graph of the quantum program to be executed;
s203: respectively determining the cost of each logic gate in the logic gate set to be mapped to the quantum chip topological structure according to the execution sequence and the initial mapping relation;
s204: and adjusting the target mapping of the quantum program to be executed according to the cost of mapping each logic gate to the quantum chip topological structure, so that the cost of the target mapping is the lowest.
Specifically, in this embodiment, the storage medium may include, but is not limited to: various media capable of storing computer programs, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.
Compared with the prior art, the method includes the steps of firstly obtaining a directed acyclic graph of the quantum program to be executed and an initial mapping relation between logic bits and physical bits, determining an execution sequence of a set of logic gates to be mapped of the quantum program to be executed according to the directed acyclic graph of the quantum program to be executed, respectively determining the cost of each logic gate in the set of logic gates to be mapped to a quantum chip topological structure according to the execution sequence and the initial mapping relation, adjusting target mapping of the quantum program to be executed according to the cost of each logic gate mapped to the quantum chip topological structure, so that the cost of the target mapping is the lowest, solving the problem that influence is caused on the quantum circuit due to a single physical bit factor, determining the optimal mapping circuit of the quantum chip topological structure, and maximizing resource utilization of the whole quantum chip.
An embodiment of the present invention further provides an electronic device, which includes a memory and a processor, where the memory stores a computer program, and the processor is configured to execute the computer program to perform the steps in any one of the method embodiments described above.
Specifically, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.
Specifically, in this embodiment, the processor may be configured to execute the following steps by a computer program:
s201: acquiring a directed acyclic graph of a quantum program to be executed and an initial mapping relation between a logic bit and a physical bit;
s202: determining an execution sequence of a set of logic gates to be mapped of the quantum program to be executed according to the directed acyclic graph of the quantum program to be executed;
s203: respectively determining the cost of each logic gate in the logic gate set to be mapped to the quantum chip topological structure according to the execution sequence and the initial mapping relation;
s204: and adjusting the target mapping of the quantum program to be executed according to the cost of mapping each logic gate to the quantum chip topological structure, so that the cost of the target mapping is the lowest.
The embodiment of the invention also provides a quantum computer operating system, which realizes the determination of the target mapping of the quantum program to be executed according to any one of the method embodiments provided in the embodiment of the invention.
The embodiment of the application also provides a quantum computer, which comprises the quantum computer operating system.
Compared with the prior art, the method comprises the steps of firstly obtaining a directed acyclic graph of the quantum program to be executed and an initial mapping relation between a logic bit and a physical bit, determining an execution sequence of a logic gate set to be mapped of the quantum program to be executed according to the directed acyclic graph of the quantum program to be executed, respectively determining the cost of each logic gate in the logic gate set to be mapped to a quantum chip topological structure according to the execution sequence and the initial mapping relation, adjusting the target mapping of the quantum program to be executed according to the cost of each logic gate mapped to the quantum chip topological structure, so that the cost of the target mapping is the lowest, solving the problem that the single physical bit factor influences the quantum circuit, determining the optimal mapping circuit of the quantum chip topological structure, and maximizing the resource utilization of the whole quantum chip.
The present invention has been described in detail with reference to the embodiments shown in the drawings, and it is therefore intended that the present invention not be limited to the exact forms and details shown and described, but that various changes and modifications can be made without departing from the spirit and scope of the invention.
Claims (12)
1. A method for determining target mapping of a quantum program to be executed, the method comprising:
acquiring a directed acyclic graph of a quantum program to be executed and an initial mapping relation between a logic bit and a physical bit;
determining an execution sequence of a set of logic gates to be mapped of the quantum program to be executed according to the directed acyclic graph of the quantum program to be executed;
respectively determining the cost of each logic gate in the logic gate set to be mapped to the quantum chip topological structure according to the execution sequence and the initial mapping relation;
and adjusting the target mapping of the quantum program to be executed according to the cost of mapping each logic gate to the quantum chip topological structure, so that the cost of the target mapping is the lowest.
2. The method according to claim 1, wherein the obtaining a directed acyclic graph of a quantum program to be executed comprises:
acquiring nodes in a quantum program to be executed;
determining an incidence relation between the nodes according to the quantum bits of the node operation;
and generating a directed acyclic graph corresponding to the quantum program to be executed according to the nodes and the incidence relation among the nodes, wherein the vertexes in the directed acyclic graph represent the nodes, the edges in the directed acyclic graph represent the incidence relation among the nodes, and the directions of the edges represent the executed time sequence relation of the nodes corresponding to the vertexes connected with the edges.
3. The method of claim 2, wherein the set of logic gates to be mapped comprises:
a first set of regular logic gates, wherein the first set of regular logic gates comprises: the single-bit quantum logic gate and the two-bit quantum logic gate with adjacent logic bits;
a second set of regular logic gates, wherein the second set of regular logic gates comprises: and the two-bit quantum logic gate with non-adjacent logic bits.
4. The method of claim 3, wherein determining an execution order of the set of logic gates to be mapped for the quantum program to be executed comprises:
setting the execution sequence of a first regular logic gate set of a node with zero in-degree in the directed acyclic graph as a first priority and setting the execution sequence of a second regular logic gate set of the node with zero in-degree in the directed acyclic graph as a second priority according to the directed acyclic graph of the quantum program to be executed;
deleting the first regular logic gate set of which the execution sequence is divided, continuously executing the step of setting the execution sequence of the first regular logic gate set of the node with zero in-degree in the directed acyclic graph as a first priority, and setting the execution sequence of the second regular logic gate set of the node with zero in-degree in the directed acyclic graph as a second priority until the execution sequence of the logic gate set to be mapped is divided completely.
5. The method of claim 4, wherein separately determining the cost of each logic gate in the set of logic gates to be mapped to map to the quantum chip topology comprises:
respectively acquiring a mapping scheme of each logic gate mapped to a quantum chip topological structure according to the execution sequence and the initial mapping relation;
a cost formula is constructed that evaluates the mapping scheme and calculates the cost of the mapping scheme.
6. The method of claim 5, wherein adjusting the target mapping of the quantum program to be executed according to the cost of mapping each logic gate to the quantum chip topology to minimize the cost of the target mapping comprises:
according to the quantum chip topological structure and the initial mapping relation, traversing and calculating the cost of each logic gate mapped to the quantum chip topological structure in the forward direction according to the execution sequence, and dynamically adjusting the mapping relation of the quantum program to be executed until the forward traversal according to the execution sequence is completed to obtain a target forward mapping relation;
according to the target forward mapping relation, reversely traversing and calculating the cost of each logic gate mapped to the quantum chip topological structure according to the execution sequence, and dynamically adjusting the mapping relation of the quantum program to be executed until the reverse traversal according to the execution sequence is completed to obtain a target reverse mapping relation;
and continuing to carry out forward and reverse alternate iterative mapping, and repeating the step of dynamically adjusting the mapping relation of the quantum program to be executed so as to minimize the cost of the target mapping.
7. The method of claim 6, wherein evaluating the cost expression for the mapping scheme is:
wherein, T 2 De-coherence time, G, for a quantum chip bit swap The number f of swap logic gates required to be introduced for mapping all logic gates in the logic gate set to be mapped double For two-bit quantum logic gate fidelity, f measure To measure fidelity, a 1 、a 2 、a 3 、a 4 Is a preset weight coefficient of the cost expression.
8. An apparatus for determining a target mapping for a quantum program to be executed, the apparatus comprising:
the acquisition module is used for acquiring a directed acyclic graph of the quantum program to be executed and an initial mapping relation between a logic bit and a physical bit;
the first determining module is used for determining the execution sequence of the logic gate set to be mapped of the quantum program to be executed according to the directed acyclic graph of the quantum program to be executed;
a second determining module, configured to determine, according to the execution order and the initial mapping relationship, a cost of mapping each logic gate in the set of logic gates to be mapped to a quantum chip topology structure;
and the adjusting module is used for adjusting the target mapping of the quantum program to be executed according to the cost of mapping each logic gate to the quantum chip topological structure, so that the cost of the target mapping is the lowest.
9. A storage medium, in which a computer program is stored, wherein the computer program is arranged to perform the method of any of claims 1 to 7 when executed.
10. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and wherein the processor is arranged to execute the computer program to perform the method of any of claims 1 to 7.
11. A quantum computer operating system, characterized in that it enables the determination of a quantum program target map to be executed according to the method of any one of claims 1 to 7.
12. A quantum computer comprising the quantum computer operating system of claim 11.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110941255.8A CN115907023A (en) | 2021-08-17 | 2021-08-17 | Method and device for determining target mapping of to-be-executed quantum program and quantum computer |
| PCT/CN2022/112765 WO2023020487A1 (en) | 2021-08-17 | 2022-08-16 | Method for mapping quantum program and quantum chip, quantum operating system and computer |
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