CN114912619A - Quantum computing task scheduling method and device and quantum computer operating system - Google Patents
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Abstract
The application belongs to the field of quantum computing, and discloses a quantum computing task scheduling method, a quantum computing task scheduling device and a quantum computer operating system, wherein the method comprises the following steps: acquiring a current topological structure of the quantum chip; obtaining a plurality of quantum computing tasks, wherein: the sum of the quantum bit numbers required by each quantum computing task is less than or equal to the quantum bit number contained in the current topological structure; processing the quantum wire corresponding to each quantum computing task into a first quantum wire, wherein the first quantum wire is an executable quantum wire which can be executed on the quantum chip; and sending the first quantum circuit to quantum computer hardware to realize the calculation of each quantum calculation task, and obtaining the scheduling result of each quantum calculation task according to the calculation result. The method and the device can improve the utilization efficiency of quantum chip computing resources, improve task scheduling efficiency and improve quantum computing efficiency.
Description
Technical Field
The application belongs to the field of quantum computing, and particularly relates to a quantum computing task scheduling method and device and a quantum computer operating system.
Background
Quantum computers are physical devices that perform high-speed mathematical and logical operations, store and process quantum information in compliance with the laws of quantum mechanics. When a device processes and calculates quantum information and runs a quantum algorithm, the device is a quantum computer. Quantum computers are a key technology under study because they have the ability to handle mathematical problems more efficiently than ordinary computers, for example, they can speed up the time to break RSA keys from hundreds of years to hours.
When task scheduling is carried out in the current quantum computing, only waiting time of quantum computing tasks and completely available complete quantum chips are considered, and the tasks are scheduled one by one to unoccupied quantum chips in a mode of firstly submitting first running.
Disclosure of Invention
The application aims to provide a quantum computing task scheduling method and device and a quantum computer operating system, so as to solve the defects in the prior art, improve the utilization efficiency of quantum chip computing resources, improve the task scheduling efficiency and improve the quantum computing efficiency.
One aspect of the present application provides a quantum computing task scheduling method, including:
acquiring a current topological structure of the quantum chip;
obtaining a plurality of quantum computing tasks, wherein: the sum of the quantum bit numbers required by each quantum computing task is less than or equal to the quantum bit number contained in the current topological structure;
processing the quantum wire corresponding to each quantum computing task into a first quantum wire, wherein the first quantum wire is an executable quantum wire which can be executed on the quantum chip;
and sending the first quantum circuit to quantum computer hardware to realize the calculation of each quantum calculation task, and obtaining the scheduling result of each quantum calculation task according to the calculation result.
As above, in the quantum computing task scheduling method, optionally, the processing the quantum wire corresponding to each quantum computing task as a first quantum wire includes:
and directly combining the quantum wires to obtain a first quantum wire.
In the foregoing quantum computing task scheduling method, optionally, the processing a quantum wire corresponding to each quantum computing task as a first quantum wire includes:
optimizing each quantum line;
and merging the optimized quantum wires to obtain a first quantum wire.
The quantum computing task scheduling method described above, wherein optionally, the optimizing processing for each quantum wire includes:
one or a combination of simplified optimization of each of the quantum wires and quantum logic gate decomposition optimization.
As above, the method for scheduling quantum computation tasks, wherein optionally, the processing a quantum wire corresponding to each quantum computation task as a first quantum wire further includes:
and compiling each combined quantum line to obtain a first quantum line.
As above, in the quantum computing task scheduling method, optionally, the merging the quantum wires includes:
determining mapping bits corresponding to quantum bits contained in each quantum circuit according to the current topological structure of the quantum chip;
updating the quantum bit in the quantum wire according to the mapping bit to obtain an updated quantum wire;
and integrating the updated quantum wires according to the mapping bits in time sequence.
As above, in the quantum computing task scheduling method, optionally, the obtaining a scheduling result of each quantum computing task according to a computing result includes:
obtaining quantum states representing the results of the calculations;
acquiring a sub-quantum state corresponding to a mapping bit corresponding to each quantum computing task in the quantum state acquisition;
and obtaining the probability corresponding to each sub-quantum state as a scheduling result corresponding to the quantum computing task.
The quantum computing task scheduling method as described above, wherein optionally, the obtaining a quantum state representing the computation result includes:
determining the eigenstates of all mapping bits corresponding to each quantum line;
and obtaining the measuring probability corresponding to each eigen state.
Another aspect of the present application provides a quantum computing task scheduling apparatus, including:
the first acquisition module is used for acquiring the current topological structure of the quantum chip;
a second obtaining module, configured to obtain a plurality of quantum computing tasks, wherein: the number of quantum bits required by each quantum computing task is less than or equal to the number of quantum bits contained in the current topological structure;
a first processing module, configured to process a quantum wire corresponding to each quantum computing task into a first quantum wire, where the first quantum wire is an executable quantum wire executable on the quantum chip;
and the second processing module is used for sending the first quantum circuit to quantum computer hardware to realize the calculation of each quantum calculation task and obtaining the scheduling result of each quantum calculation task according to the calculation result.
A further aspect of the application provides a storage medium having a computer program stored thereon, wherein the computer program is arranged to perform the method of any of the above when executed.
Yet another aspect of the application provides an electronic device comprising a memory having a computer program stored therein and a processor configured to execute the computer program to perform the method of any of the above.
In another aspect, the present application provides a quantum computer operating system, which implements the scheduling of the quantum computing task according to any one of the foregoing quantum computing task scheduling methods.
Yet another aspect of the present application provides a quantum computer comprising the quantum computer operating system described above.
Compared with the prior art, the method and the device have the advantages that in the quantum computing task scheduling process, the current topological structure of the quantum chip is obtained firstly; then, a plurality of quantum computing tasks are obtained according to the current topological structure, quantum wires corresponding to the quantum computing tasks are processed into a first quantum wire, the first quantum wire is sent to quantum computer hardware to realize the computation of the quantum computing tasks, and the scheduling result of the quantum computing tasks is obtained according to the computation result. In the whole process, the quantum computing tasks which can be processed currently are determined based on the current topological structure of the quantum chip, then the quantum circuits corresponding to the quantum computing tasks are processed into a first quantum circuit, and the first quantum circuit is sent and executed at one time, so that the scheduling processing of the quantum computing tasks is completed at one time, the utilization rate of computing resources of the quantum chip is integrally improved, the efficiency of scheduling the quantum computing tasks is improved, and the computing efficiency of quantum computing is jointly improved.
Drawings
Fig. 1 is a block diagram of a hardware structure of a computer terminal of a quantum computing task scheduling method according to an embodiment of the present disclosure;
fig. 2 is a schematic flowchart of a quantum computing task scheduling method according to an embodiment of the present disclosure;
fig. 3.1 is a schematic diagram of a quantum wire for a first quantum computing task of an embodiment of the present application;
fig. 3.2 is a schematic diagram of a quantum wire for a second quantum computing task of an embodiment of the present application;
FIG. 3.3 is a quantum wire schematic of a third quantum computing task of an embodiment of the present application;
FIG. 4 is a schematic diagram of a first quantum wire according to an embodiment of the present application;
fig. 5 is a quantum computing task scheduling apparatus according to another embodiment of the present application.
Detailed Description
The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
The embodiment of the application firstly provides a quantum computing task scheduling method, and the method can be applied to electronic equipment, such as a computer terminal, specifically a common computer, a quantum computer and the like.
The following description will be made in detail by taking the example of the operation on a computer terminal. Fig. 1 is a block diagram of a hardware structure of a computer terminal of a quantum computing task scheduling method according to an embodiment of the present application. As shown in fig. 1, the computer terminal may include one or more (only one shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, and optionally, a transmission device 106 for communication functions and an input-output device 108. It will be understood by those skilled in the art that the structure shown in fig. 1 is only an illustration and is not intended to limit the structure of the computer terminal. For example, the computer terminal may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.
The memory 104 may be configured to store software programs and modules of application software, such as program instructions/modules corresponding to the quantum computing task scheduling method in the embodiment of the present application, and the processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, implementing the foregoing methods. The memory 104 may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory located remotely from the processor 102, which may be connected to a computer terminal over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission device 106 is used to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the computer terminal. In one example, the transmission device 106 includes a Network adapter (NIC) that can be connected to other Network devices through a base station to communicate with the internet. In one example, the transmission device 106 can be a Radio Frequency (RF) module, which is used to communicate with the internet in a wireless manner.
It should be noted that a true quantum computer is a hybrid structure, which includes two major components: one part is a classic computer which is responsible for executing classic calculation and control; the other part is quantum equipment which is responsible for running a quantum program to further realize quantum computation. The quantum program is a string of instruction sequences which can run on a quantum computer and are written by quantum languages such as Qrun languages, so that the support on the operation of a quantum logic gate is realized, and the quantum computation is finally realized. In particular, a quantum program is a sequence of instructions that operate quantum logic gates in a time sequence.
A quantum circuit, which is a commonly used general quantum computing model, represents a circuit that operates on a quantum bit under an abstract concept, and includes the quantum bit, the circuit (timeline), and various quantum logic gates, and finally, it is often necessary to read a result through a quantum measurement operation.
Unlike conventional circuits that are connected by metal lines to pass voltage or current signals, in quantum circuits, the lines can be viewed as being connected by time, i.e., the state of a qubit evolves naturally over time, in the process being operated on as indicated by the hamiltonian until a logic gate is encountered.
A quantum program corresponds to an overall quantum circuit as a whole, and the quantum program refers to the overall quantum circuit, wherein the total number of quantum bits in the overall quantum circuit is the same as the total number of quantum bits of the quantum program. It can be understood that: a quantum program may consist of quantum wires, measurement operations for quantum bits in the quantum wires, registers to hold measurement results, and control flow nodes (jump instructions), and a quantum wire may contain tens to hundreds or even thousands of quantum gate operations. The execution process of the quantum program is a process executed for all the quantum logic gates according to a certain time sequence. It should be noted that timing is the time sequence in which the single quantum logic gate is executed.
It should be noted that in the classical calculation, the most basic unit is a bit, and the most basic control mode is a logic gate, and the purpose of the control circuit can be achieved through the combination of the logic gates. Similarly, the way qubits are handled is quantum logic gates. The quantum state can be evolved using quantum logic gates, which are the basis for forming quantum circuits, and which are generally represented using unitary matrices, which are not only matrix forms, but also an operation and transformation. The quantum logic gate is defined in terms of the number of qubits acted upon. A single-bit qubit logic gate, as defined as acting on a qubit, is common as a basic single-qubit logic gate: hadamard gate (H gate, Aldamard gate), Pauli-X gate (X gate), Pauli-Y gate (Y gate), Pauli-Z gate (Z gate), RX gate, RY gate, RZ gate, etc.; the definition acting on the two qubits is a two-bit quantum logic gate, such as a common basic two-bit quantum logic gate, such as a CNOT gate, a CR gate, a CZ gate, and an istap gate, an operation matrix corresponding to the basic two-bit quantum logic gate is 4 x 4 dimensional, and element values in the operation matrix are determined at the same time, and any two-bit quantum logic gate U acting on the two qubits is also 4 x 4 dimensional, but the element values in the operation matrix are not determined, and are set by a programmer as required; a multi-bit quantum logic gate such as a toffee gate, etc.
It should be noted that, the quantum chip is hardware for realizing quantum computation by driving quantum bits to work with physical signals, and the equipment for generating physical signals built around the quantum chip is strictly matched with the quantum bits contained in the quantum chip. The equipment for generating physical signals and the quantum chip built on the periphery of the quantum chip are used as physical hardware equipment and can be controlled and driven only once at a moment. In the existing quantum computing task scheduling process, the physical hardware devices are sequentially scheduled to realize the computation of the computer tasks of the physical hardware devices by taking any quantum computing task as a unit. The process greatly reduces the efficiency of scheduling quantum computing tasks, cannot ensure the full utilization of computing resources of quantum chips, and further influences the computing efficiency of quantum computing.
Based on this, as shown in the schematic flow diagram of the quantum computing task scheduling method shown in fig. 2, an embodiment of the present application provides a quantum computing task scheduling method, where the method includes:
s1, acquiring the current topological structure of the quantum chip;
specifically, a quantum chip is a processor in a quantum computer for performing quantum computation, and quantum bits contained in the quantum chip are processing units of the processor. Under the development of quantum chip hardware manufacturing technology, the increase and utilization of the quantum bit number contained in the quantum chip are one of the factors restricting quantum computing power, so that the quantum bit on the quantum chip needs to be reasonably and fully called in quantum computing task scheduling.
The topological structure of the quantum chip reflects the spatial characteristics of the quantum bits on the quantum chip, the spatial characteristics determine the usable condition of the quantum chip as a computing resource, and the spatial characteristics of the quantum bits comprise the number, the positions and the connection relations of the quantum bits contained in the quantum chip.
The current topological structure of the quantum chip reflects the current available use condition of the quantum chip as a computing resource and can be determined according to the available condition of quantum bits on the quantum chip. The qubit availability scenarios illustratively include: the occupation of a qubit, and the fact whether it can be used depending on the fidelity of the qubit.
S2, obtaining a plurality of quantum computing tasks, wherein: the sum of the quantum bit numbers required by each quantum computing task is less than or equal to the quantum bit number contained in the current topological structure;
specifically, the quantum computation task is represented by a quantum line, the number of quantum bits included in the quantum line represents a quantum bit resource required for executing a corresponding quantum computation task, and a quantum computation task matching the current topology of the quantum chip can be obtained according to the sum of the number of quantum bits included in each quantum line.
Illustratively, the sum of the quantum bit numbers required by each quantum computing task is equal to the quantum bit number included in the current topology.
S3, processing the quantum wire corresponding to each quantum computing task into a first quantum wire, where the first quantum wire is an executable quantum wire executable on the quantum chip;
on one hand, the current computing resources of the quantum chip which need to be met are executed on the quantum chip, and the current computing resources are determined by the quantum bit quantity contained in the current topological structure of the quantum chip; on the other hand, it is necessary to satisfy the requirement that the quantum logic gate included in the quantum circuit can be implemented on the quantum chip, for example, if one or two quantum logic gates included in the quantum circuit correspond to two characteristic bits, and an edge connection is required between two mapping bit bits when the two characteristic bits are mapped to the quantum chip, the two quantum logic gates can be directly implemented on the quantum chip. A quantum wire composed of quantum logic gates that can be directly executed on a quantum chip is an executable quantum wire.
And S4, sending the first quantum circuit to quantum computer hardware to realize the calculation of each quantum calculation task, and obtaining the scheduling result of each quantum calculation task according to the calculation result.
Specifically, the quantum computer hardware is the quantum chip and the device for generating physical signals built around the quantum chip. The result of quantum computation performed by the quantum chip is contained in the quantum state of the qubit, so that the scheduling result of each of the quantum computation tasks can be obtained by analyzing the quantum state of the qubit.
In addition, based on the feature that the device for generating physical signals and the quantum chip built around the quantum chip can only be controlled and driven once at a time, the quantum circuit corresponding to each quantum computation task is processed into a first quantum circuit, and then the first quantum circuit is sent once, an instruction signal for realizing the first quantum circuit is applied to the physical hardware device, the physical hardware device is controlled and driven to work, and then the execution of the first quantum circuit, namely the computation of each quantum computation task, can be realized, and the scheduling efficiency of the quantum computation tasks is greatly improved through simultaneous scheduling of multiple tasks in the whole process.
Through the steps S1 to S4, the embodiment of the present application provides a quantum computing task scheduling method, including: acquiring a current topological structure of the quantum chip; obtaining a plurality of quantum computing tasks, wherein: the sum of the quantum bit numbers required by each quantum computing task is less than or equal to the quantum bit number contained in the current topological structure; processing the quantum wire corresponding to each quantum computing task into a first quantum wire, wherein the first quantum wire is an executable quantum wire which can be executed on the quantum chip; and sending the first quantum circuit to quantum computer hardware to realize the calculation of each quantum calculation task, and obtaining the scheduling result of each quantum calculation task according to the calculation result.
In the whole process, the quantum computing tasks which can be processed currently are determined based on the current topological structure of the quantum chip, then the quantum circuits corresponding to the quantum computing tasks are processed into a first quantum circuit, and the first quantum circuit is sent and executed at one time, so that the scheduling processing of the quantum computing tasks is completed at one time, the utilization rate of computing resources of the quantum chip is integrally improved, the efficiency of scheduling the quantum computing tasks is improved, and the computing efficiency of quantum computing is jointly improved.
As an embodiment of the present invention, in the step S3, in the process of processing the quantum wire corresponding to each quantum computation task into one first quantum wire, the quantum wires corresponding to each quantum computation task may be directly merged, or the quantum wires corresponding to each quantum computation task may be optimized and then merged.
The above described optimization process of quantum wires, illustratively, simplified optimization of quantum wires, and quantum logic gate decomposition optimization; illustratively, simplified optimization of quantum wires may enable the removal of redundant quantum logic gates in the quantum wires; quantum logic gate decomposition optimizations include, but are not limited to, decomposition of multiple quantum logic gates, any single quantum logic gate, any two quantum logic gate included in a quantum line.
The merging processing of the quantum lines corresponding to the quantum computing tasks may be sequential splicing merging processing of the quantum lines, that is, the quantum lines corresponding to the quantum computing tasks are sequentially connected together as a whole; other approaches may be adopted, such as in an implementation manner of the embodiment of the present application, the merging process for each quantum wire includes:
determining mapping bits corresponding to quantum bits contained in each quantum circuit according to the current topological structure of the quantum chip; updating the quantum bit in the quantum wire according to the mapping bit to obtain an updated quantum wire; and integrating the updated quantum wires according to the mapping bits in time sequence. It is understood that the mapping bits are the qubits in the current topology of the qubit, i.e. the qubits on the qubit.
Illustratively, the acquired 3 quantum computation tasks, illustratively, the quantum wires H (q [0]) of the 1 st quantum computation task as shown in FIG. 3.1])、H(q[1])、CNOT(q[1],q[0])、H(q[2])、Measure(q[0])、Measure(q[1])、Measure(q[2]) Symbol in FIG. 3.1
Which represents the measurement operation on the quantum wire and will not be described further.
The quantum lines H (q 0), H (q 1), CNOT (q 1, q 2), Measure (q 0), Measure (q 1), Measure (q 2) of the 2 nd quantum computing task shown in FIG. 3.2.
The quantum lines H (q 0), H (q 1), CZ (q 0, q 2), H (q 2), Measure (q 0), Measure (q 1), Measure (q 2) of the 3 rd quantum computing task shown in FIG. 3.3.
The number of bits required for the quantum wire of the 1 st quantum computing task is 3 (i.e., n1 is 3), the number of bits required for the quantum wire of the 2 nd quantum computing task is 3 (i.e., n2 is 3), and the number of bits required for the quantum wire of the 3 rd quantum computing task is 3 (i.e., n3 is 3); let 9 qubits be included in the current topology of a quantum chip. Determining mapping bits corresponding to the quantum bits included in each quantum circuit according to the current topological structure of the quantum chip, which can be represented by a mapping relation reflecting a sequence number relation of the quantum bits, as shown in the following table:
at this time, mapping bits corresponding to Q0, Q1, and Q2 of the quantum wire of the 1 st quantum computing task are Q0, Q1, and Q2, respectively; the mapped bits corresponding to Q0, Q1, and Q2 of the quantum wires of the 2 nd quantum computing task are Q3, Q4, and Q5, respectively; the mapped bits corresponding to Q0, Q1, and Q2 of the quantum wires of the 3 rd quantum computing task are Q6, Q7, and Q8, respectively; it can be known that the qubits and mapping bits of the quantum wires of the quantum computing task can establish a one-to-one correspondence relationship through the qubit sequence numbers (i.e., the values at the bottom right corner of each qubit identifier), while the identifiers such as Q0 and Q1 are only identifiers for distinguishing the qubits, and can be set as required by those skilled in the art.
Continuing with fig. 3.1, 3.2, and 3.3 as an example, a process of updating the quantum bits within the quantum wires according to the mapping bits to obtain updated quantum wires is described.
Specifically, mapping bits corresponding to Q0, Q1, and Q2 of the quantum wire of the 1 st quantum computing task shown in FIG. 3.1 are Q0, Q1, and Q2, respectively, and then the quantum wires shown in FIG. 3.1 are updated to H (Q0), H (Q1), CNOT (Q1, Q0), H (Q2), Measure (Q0), Measure (Q1), Measure (Q2).
The mapped bits corresponding to Q0, Q1, and Q2 of the quantum lines of the 2 nd quantum computing task shown in FIG. 3.2 are Q3, Q4, and Q5, respectively, and then the quantum lines shown in FIG. 3.2 are updated to H (Q3), H (Q4), CNOT (Q4, Q5), Measure (Q3), Measure (Q4), Measure (Q5).
The mapped bits corresponding to Q0, Q1, and Q2 of the quantum lines of the 3 rd quantum computing task shown in FIG. 3.3 are Q6, Q7, and Q8, respectively, and then the quantum lines shown in FIG. 3.3 are updated to H (Q6), H (Q7), CZ (Q6, Q8), H (Q8), Measure (Q6), Measure (Q7), Measure (Q8).
Then, integrating the updated quantum wires according to the mapping bits in time sequence, which specifically includes:
and splicing the updated quantum circuits to obtain a quantum sub-circuit corresponding to all the mapping bits, and adjusting the quantum sub-circuit according to the time sequence to complete the integration of the updated quantum circuits according to the time sequence.
The following are exemplary: the total sublines are as follows:
H(Q[0])、H(Q[1])、CNOT(Q[1],Q[0])、H(Q[2])、Measure(Q[0])、Measure(Q[1])、Measure(Q[2])、H(Q[3])、H(Q[4])、CNOT(Q[4],Q[5])、Measure(Q[3])、Measure(Q[4])、Measure(Q[5])、H(Q[6])、H(Q[7])、CZ(Q[6],Q[8])、H(Q[8])、Measure(Q[6])、Measure(Q[7])、Measure(Q[8])。
the adjusting the quantum sub-circuit in time sequence means that quantum logic gates with the same time sequence in the quantum sub-circuit are sequentially placed according to mapping bit numbers, and exemplarily, quantum circuits obtained by adjusting the quantum sub-circuit in time sequence are as follows, and are shown in fig. 4:
H(Q[0])、H(Q[1])、H(Q[2])、H(Q[3])、H(Q[4])、H(Q[6])、H(Q[7])、CNOT(Q[1],Q[0])、CNOT(Q[4],Q[5])、CZ(Q[6],Q[8])、H(Q[8])、Measure(Q[0])、Measure(Q[1])、Measure(Q[2])、Measure(Q[3])、Measure(Q[4])、Measure(Q[5])、Measure(Q[6])、Measure(Q[7])、Measure(Q[8])。
the timing sequence refers to the order of the quantum logic gates in the quantum circuit, and due to the parallelism of the quantum bit operations, if the quantum logic gates acting on different quantum bits can operate in parallel at the same time, the quantum logic gates are in the same timing sequence. For more information on the timing of the quantum wires, reference may be made to chinese patent application No. CN201911117541.1, application date 2019, 11/15/the specification portion entitled "method, system, storage medium, and electronic device for displaying quantum wires in a graphic manner", which is not described in detail herein.
As an implementation manner of this embodiment, the processing the quantum wire corresponding to each quantum computing task as a first quantum wire further includes: and compiling each merged quantum wire to obtain a first quantum wire which can be executed on the quantum chip.
Specifically, on the one hand, the current computing resources of the quantum chip which need to be satisfied can be executed on the quantum chip, and the current computing resources are determined by the quantum bit number contained in the current topological structure of the quantum chip; on the other hand, it needs to be satisfied that the quantum logic gates included in the quantum circuit can be implemented in the quantum bits on the quantum chip, for example, if one or two quantum logic gates included in the quantum circuit correspond to two characteristic bits, and when the two characteristic bits are mapped to the quantum chip, an edge connection is required between two mapped bit bits, then the two quantum logic gates can be directly implemented on the quantum chip, and the quantum circuit composed of the quantum logic gates that can be directly implemented on the quantum chip is an executable quantum circuit.
As an implementation manner of this embodiment, the step S4, sending the first quantum wire to the quantum computer hardware to implement the computation of each quantum computation task and obtaining the scheduling result of each quantum computation task according to the computation result, is the stage of executing the quantum computation task and analyzing the result. The process of executing the quantum computing task is the process of driven execution of the quantum chip and the device for generating the physical signal built around the quantum chip, and is not expanded in detail here. And the scheduling result for each of the quantum computing tasks obtained from the computation result may be introduced by the following procedure.
S41, obtaining quantum state representing the calculation result;
specifically, the quantum states representing the calculation results are quantum states of all mapping bits, and can be represented by eigenstates of the mapping bits and amplitudes corresponding to the eigenstates.
It should be noted that the quantum computation result needs to be obtained by statistical measurement, and the measured probability is the probability that the qubit is in the eigenstate, and the probability is the square of the amplitude. Obtaining the quantum states representing the computation results requires determining the eigenstates of all the mapped bits corresponding to each of the quantum wires and obtaining the measurement probabilities corresponding to each of the eigenstates.
Exemplarily, the first quantum wire obtained for the embodiment includes 9 quantum bits, which are respectively: q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8; corresponding eigenstates have a total of 2 9 And if the measured probability of each eigen state is denoted as P, the quantum state of the group of mapping bits is preliminarily expressed as:
s42, acquiring the quantum state corresponding to the mapping bit corresponding to each quantum computing task in the quantum state acquisition;
specifically, taking the first quantum computing task as an example, the mapping bits are Q0, Q1, and Q2, and the corresponding sub-quantum states are 8, that is, 2 3 3 the number of qubits required for the first quantum computing task, | XXXXXXX 000, respectively>、|XXXXXX001>、|XXXXXX010>、|XXXXXX011>、|XXXXXX100>、|XXXXXX101>、|XXXXXX110>、|XXXXXX111>(ii) a Wherein "X" represents 0 or 1, each sub-quantum state comprising 64 eigenstates, i.e. comprising 2 6 And 6, an eigenstate is a mapping bit of the quantum chip corresponding to other quantum computing tasks.
And S43, obtaining the probability corresponding to each sub-quantum state as the scheduling result corresponding to the quantum computing task.
Specifically, the sum of the probabilities of all the eigenstates included in each sub-quantum state is taken as the probability of the sub-quantum state; and obtaining the probability of all the quantum states of the first quantum computing task as the scheduling result of the first quantum computing task.
Obtaining the scheduling result of each quantum computation task according to the computation result is completed through steps S41 to S41.
As shown in fig. 5, another embodiment of the present application provides a quantum computing task scheduling apparatus, including:
a first obtaining module 501, configured to obtain a current topological structure of a quantum chip;
a second obtaining module 502, configured to obtain a plurality of quantum computing tasks, where: the quantum bit number required by each quantum computing task is less than or equal to the quantum bit number contained in the current topological structure;
a first processing module 503, configured to process the quantum wire corresponding to each quantum computing task into a first quantum wire, where the first quantum wire is an executable quantum wire that can be executed on the quantum chip;
the second processing module 504 is configured to send the first quantum wire to quantum computer hardware to implement computation of each quantum computation task, and obtain a scheduling result of each quantum computation task according to a computation result.
The quantum computing task which can be processed currently can be determined based on the current topological structure of the quantum chip, then the quantum circuit corresponding to each quantum computing task is processed into the first quantum circuit, and the first quantum circuit is sent and executed at one time, so that the scheduling processing of the plurality of quantum computing tasks is completed at one time, the utilization rate of computing resources of the quantum chip is integrally improved, the efficiency of scheduling the quantum computing tasks is improved, and the computing efficiency of quantum computing is jointly improved.
Another embodiment of the present application provides a storage medium having a computer program stored therein, wherein the computer program is configured to perform the steps of any of the above method embodiments when executed.
Specifically, in the present embodiment, the storage medium may be configured to store a computer program for executing the steps of:
s101, acquiring a current topological structure of a quantum chip;
s102, obtaining a plurality of quantum computing tasks, wherein: the sum of the quantum bit numbers required by each quantum computing task is less than or equal to the quantum bit number contained in the current topological structure;
s103, processing the quantum wire corresponding to each quantum computing task into a first quantum wire, where the first quantum wire is an executable quantum wire executable on the quantum chip;
and S104, sending the first quantum circuit to quantum computer hardware to realize the calculation of each quantum calculation task, and obtaining the scheduling result of each quantum calculation task according to the calculation result.
Specifically, in this embodiment, the storage medium may include, but is not limited to: various media capable of storing computer programs, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.
Another embodiment of the present application provides an electronic device, comprising a memory having a computer program stored therein and a processor configured to execute the computer program to perform the steps of any of the above method embodiments.
Specifically, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.
Specifically, in this embodiment, the processor may be configured to execute the following steps by a computer program:
s101, acquiring a current topological structure of the quantum chip;
s102, obtaining a plurality of quantum computing tasks, wherein: the sum of the quantum bit numbers required by each quantum computing task is less than or equal to the quantum bit number contained in the current topological structure;
s103, processing the quantum wire corresponding to each quantum computing task into a first quantum wire, where the first quantum wire is an executable quantum wire executable on the quantum chip;
and S104, sending the first quantum circuit to quantum computer hardware to realize the calculation of each quantum calculation task, and obtaining the scheduling result of each quantum calculation task according to the calculation result.
Another embodiment of the present application provides a quantum computer operating system, wherein the quantum computer operating system implements the scheduling of the quantum computing task according to the quantum computing task scheduling method described in any one of the above method embodiments.
Another embodiment of the present application provides a quantum computer comprising the quantum computer operating system described in the above embodiment.
The construction, features and functions of the present application are described in detail in the embodiments illustrated in the drawings, which are only preferred embodiments of the present application, but the present application is not limited by the drawings, and all equivalent embodiments that can be modified or changed according to the idea of the present application are within the scope of the present application without departing from the spirit of the present application.
Claims (13)
1. A quantum computing task scheduling method, the method comprising:
acquiring a current topological structure of the quantum chip;
obtaining a plurality of quantum computing tasks, wherein: the sum of the quantum bit numbers required by each quantum computing task is less than or equal to the quantum bit number contained in the current topological structure;
processing the quantum wire corresponding to each quantum computing task into a first quantum wire, wherein the first quantum wire is an executable quantum wire which can be executed on the quantum chip;
and sending the first quantum circuit to quantum computer hardware to realize the calculation of each quantum calculation task, and obtaining the scheduling result of each quantum calculation task according to the calculation result.
2. The method of claim 1, wherein the processing the quantum wire corresponding to each quantum computation task as a first quantum wire comprises:
and directly combining the quantum wires to obtain a first quantum wire.
3. The method of claim 1, wherein the processing the quantum wire corresponding to each quantum computation task as a first quantum wire comprises:
optimizing each quantum line;
and carrying out merging processing on each optimized quantum line optimization processing to obtain a first quantum line.
4. The quantum computing task scheduling method of claim 3, wherein the optimizing each of the quantum wires comprises:
one or a combination of simplified optimization of each of the quantum wires and quantum logic gate decomposition optimization.
5. The quantum computing task scheduling method according to any one of claims 2 or 3, wherein the processing of the quantum wire corresponding to each quantum computing task as a first quantum wire further comprises:
and compiling each combined quantum line to obtain a first quantum line.
6. The quantum computing task scheduling method according to any one of claims 2 or 3, wherein the merging process for each of the quantum wires includes:
determining mapping bits corresponding to quantum bits contained in each quantum circuit according to the current topological structure of the quantum chip;
updating the quantum bit in the quantum wire according to the mapping bit to obtain an updated quantum wire;
and integrating the updated quantum wires according to the mapping bits in time sequence.
7. The method according to claim 6, wherein the obtaining the scheduling result of each quantum computing task according to the computing result comprises:
obtaining quantum states representing the results of the calculations;
acquiring a sub-quantum state corresponding to a mapping bit corresponding to each quantum computing task in the quantum state acquisition;
and obtaining the probability corresponding to each sub-quantum state as a scheduling result corresponding to the quantum computing task.
8. The quantum computing task scheduling method of claim 7, wherein the obtaining quantum states representing the computation results comprises:
determining the eigenstates of all mapping bits corresponding to each quantum line;
and obtaining the measuring probability corresponding to each eigen state.
9. A quantum computing task scheduling apparatus, the apparatus comprising:
the first acquisition module is used for acquiring the current topological structure of the quantum chip;
a second obtaining module for obtaining a plurality of quantum computing tasks, wherein: the quantum bit number required by each quantum computing task is less than or equal to the quantum bit number contained in the current topological structure;
a first processing module, configured to process a quantum wire corresponding to each quantum computing task into a first quantum wire, where the first quantum wire is an executable quantum wire that can be executed on the quantum chip;
and the second processing module is used for sending the first quantum circuit to quantum computer hardware to realize the calculation of each quantum calculation task and obtaining the scheduling result of each quantum calculation task according to the calculation result.
10. A storage medium, in which a computer program is stored, wherein the computer program is arranged to perform the method of any of claims 1 to 8 when executed.
11. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and wherein the processor is arranged to execute the computer program to perform the method of one of claims 1 to 8.
12. A quantum computer operating system, wherein the quantum computer operating system implements the scheduling of the quantum computing task according to the quantum computing task scheduling method of any one of claims 1 to 8.
13. A quantum computer comprising the quantum computer operating system of claim 12.
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| US18/276,096 US20240119329A1 (en) | 2021-02-07 | 2022-01-28 | Quantum computer operating system, quantum computer and readable storage medium |
| PCT/CN2022/074798 WO2022166851A1 (en) | 2021-02-07 | 2022-01-28 | Quantum computer operating system, quantum computer, and readable storage medium |
| EP22749130.5A EP4290419A1 (en) | 2021-02-07 | 2022-01-28 | Quantum computer operating system, quantum computer, and readable storage medium |
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