CN112115655A - Quantum line compiling method and device based on quantum chip coupling topological structure - Google Patents
Quantum line compiling method and device based on quantum chip coupling topological structure Download PDFInfo
- Publication number
- CN112115655A CN112115655A CN202010887028.7A CN202010887028A CN112115655A CN 112115655 A CN112115655 A CN 112115655A CN 202010887028 A CN202010887028 A CN 202010887028A CN 112115655 A CN112115655 A CN 112115655A
- Authority
- CN
- China
- Prior art keywords
- coupling
- quantum
- gate
- adjusted
- topological structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Evolutionary Computation (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computing Systems (AREA)
- Data Mining & Analysis (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Computational Mathematics (AREA)
- Artificial Intelligence (AREA)
- Geometry (AREA)
- Logic Circuits (AREA)
Abstract
The application discloses a quantum circuit compiling method and device based on a quantum chip coupling topological structure, which are used for solving the problem that application barriers are generated due to the limitation of the coupling relation between physical bits in the process of applying the design of a quantum circuit to a quantum computer. Determining a coupling topological structure corresponding to each physical bit in a quantum chip; traversing all gate operations to be executed of the quantum lines according to the coupling topological structure, and determining the gate operation needing to be adjusted of the coupling topological structure as the gate operation to be adjusted; adjusting the coupling topological structure through SWAP gate operation according to the gate operation to be adjusted; and restoring the adjusted coupling topological structure through SWAP gate operation to complete the compiling of the quantum circuit.
Description
Technical Field
The present application relates to the field of quantum computing, and in particular, to a quantum circuit compiling method and device based on a quantum chip coupling topology.
Background
In the application process of a quantum computer, a quantum algorithm is usually designed through a quantum circuit, and then a quantum chip is used for specific implementation.
For the sake of distinction, the qubit structure in a quantum chip is generally referred to as a physical bit, and the subject bit operated on in a quantum wire is referred to as a qubit.
In a quantum computer, the design of gate operation of any logic can be realized through two basic types of gate operation, namely single-bit gate operation and two-bit gate operation, and the combination of the two basic types of gate operation. Wherein the single-bit gate operation includes an X gate, a T gate, etc., and the two-bit gate operation includes a SWAP, etc.
However, in practical applications, the two-bit gate operation can only be implemented between two physical bits with a coupling relationship, and the physical bits actually corresponding to the two-bit gate operation designed in the quantum wire may not have a coupling relationship, i.e., the application limit of the two-bit gate operation is not met. Therefore, certain obstacles are often encountered in applying the design of quantum wires to quantum computers.
Disclosure of Invention
The embodiment of the application provides a quantum wire compiling method and device based on a quantum chip coupling topological structure, which are used for solving the problem that application barriers are generated due to the limitation of the coupling relation between physical bits in the process of applying the design of a quantum wire to a quantum computer.
The quantum circuit compiling method based on the quantum chip coupling topological structure provided by the embodiment of the application comprises the following steps:
determining a coupling topological structure corresponding to each physical bit in the quantum chip;
traversing all gate operations to be executed of the quantum lines according to the coupling topological structure, and determining the gate operation needing to be adjusted of the coupling topological structure as the gate operation to be adjusted;
adjusting the coupling topological structure through SWAP gate operation according to the gate operation to be adjusted;
and restoring the adjusted coupling topological structure through SWAP gate operation to complete the compiling of the quantum circuit.
In one example, according to the coupling topology, traversing all gate operations to be performed by the quantum wire, and determining a gate operation requiring adjustment of the coupling topology as a gate operation to be adjusted includes: determining whether the quantum bit corresponding to the gate operation has a coupling relation or not according to the coupling topological structure aiming at all gate operations to be executed by the quantum line; and determining the gate operation corresponding to the quantum bit without the coupling relation as the gate operation to be adjusted.
In one example, adjusting the coupling topology by SWAP gate operation according to the gate operation to be adjusted includes: determining a plurality of corresponding SWAP gate operations when the coupling topological structure is adjusted according to the quantum bit corresponding to the gate operation to be adjusted; and adjusting each quantum bit in the coupling topological structure through the operation of the plurality of SWAP gates, and establishing a coupling relation between the quantum bits corresponding to the operation of the gate to be adjusted.
In one example, determining, according to the qubit corresponding to the gate operation to be adjusted, a plurality of SWAP gate operations corresponding to when the coupling topology is adjusted includes: determining two quantum bits corresponding to the gate operation to be adjusted; and determining a plurality of corresponding SWAP gate operations when the coupling topological structure is adjusted according to the distance between the two quantum bits in the coupling topological structure.
In one example, determining a number of SWAP gate operations corresponding to the adjustment of the coupling topology based on the distance between the two qubits in the coupling topology comprises: and determining the number of the SWAP gate operations required for adjusting the coupling topological structure and the execution sequence among the SWAP gate operations according to the distance between the two qubits in the coupling topological structure.
In one example, the distance is positively correlated to the number of SWAP gate operations required.
In one example, the SWAP gate operations are used to gradually reduce the distance between two qubits corresponding to the gate operation to be adjusted.
In one example, adjusting each qubit in a coupling topology structure through the SWAP gate operations to establish a coupling relationship between the qubits corresponding to the gate operations to be adjusted includes: and exchanging the sequence of the two corresponding qubits through each SWAP gate operation until a coupling relation exists between the two qubits corresponding to the gate operation to be adjusted.
In one example, recovering the adjusted coupling topology through a SWAP gate operation includes: and recovering the adjusted coupling topological structure according to the number of the needed SWAP gate operations and the reverse order of the execution order among the SWAP gate operations.
The quantum circuit compiling device based on the quantum chip coupling topological structure provided by the embodiment of the application comprises:
the determining module is used for determining a coupling topological structure corresponding to each physical bit in the quantum chip;
the traversal module traverses all gate operations to be executed of the quantum circuit according to the coupling topological structure, determines the gate operation needing to be adjusted on the coupling topological structure and takes the gate operation as the gate operation to be adjusted;
the adjusting module adjusts the coupling topological structure through SWAP gate operation according to the gate operation to be adjusted;
and the recovery module recovers the adjusted coupling topological structure through the SWAP gate operation to complete the compiling of the quantum circuit.
The embodiment of the application provides a quantum circuit compiling method and device based on a quantum chip coupling topological structure, and the method and device at least have the following beneficial effects: by using the characteristic of SWAP gate operation, the coupling relationship can be established between two quantum bits which do not have the coupling relationship in the physical bit coupling topological structure through exchange, and the smooth execution of all two-bit gate operations in a quantum circuit is realized. The compiling method for the quantum circuit solves the obstacle of the quantum circuit applied to the quantum chip in a simple implementation mode, and provides a good solution for the smooth implementation of various quantum algorithms.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a flowchart of a quantum wire compiling method based on a quantum chip coupling topology according to an embodiment of the present application;
fig. 2 is a schematic diagram of an UCSB five-bit superconducting quantum chip provided in an embodiment of the present application;
fig. 3 is a schematic diagram of a physical bit coupling topology of an UCSB five-bit superconducting quantum chip according to an embodiment of the present application;
fig. 4 is a schematic diagram illustrating the operation of a two-bit gate in a quantum wire according to an embodiment of the present disclosure;
fig. 5 is a diagram illustrating the compilation of quantum wires corresponding to fig. 4 according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a quantum wire compiling apparatus based on a quantum chip coupling topology according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail and completely with reference to the following specific embodiments of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 is a flowchart of a quantum wire compiling method based on a quantum chip coupling topology according to an embodiment of the present application, which specifically includes the following steps:
s101: and determining a coupling topological structure corresponding to each physical bit in the quantum chip.
In this embodiment, the server may determine, according to a structure of a physical bit in a quantum chip of the quantum computer, a coupling topology corresponding to the physical bit structure.
Fig. 2 is a schematic diagram of an UCSB five-bit superconducting quantum chip, and fig. 3 is a schematic diagram of a physical bit coupling topology of the UCSB five-bit superconducting quantum chip.
In FIG. 2, the quantum chip includes Q0～Q4Five physical bits, which are capacitively coupled, have a coupling relationship only between adjacent physical bits.
In fig. 3, q 0-q 4 represent qubits in the coupling topology corresponding to the five physical bits in fig. 2, respectively, and the bidirectional arrow between two qubits represents the coupling relationship between two qubits. As can be seen from fig. 3, in the coupling topology, there is a coupling relationship between every two adjacent qubits, i.e., between q0 and q1, between q1 and q2, between q2 and q3, and between q3 and q 4. In addition to this, no other coupling relationship exists.
S102: and traversing all gate operations to be executed of the quantum lines according to the coupling topological structure, and determining the gate operation needing to be adjusted of the coupling topological structure as the gate operation to be adjusted.
In the embodiment of the present application, the server may compile all gate operations of the quantum line design during the application process in the quantum chip according to the designed quantum line, so as to avoid that the gate operations that do not meet the coupling relationship limit of the physical bit in the gate operations of the quantum line affect the application of the quantum algorithm.
Specifically, for all the gate operations to be executed in the quantum wire, the server may determine, according to the determined coupling topology, whether the gate operation is a gate operation that does not meet the physical bit coupling relationship limit. The gate operation to be executed represents the gate operation which is designed in advance in the quantum circuit and is to be applied to the quantum chip, and the limitation that the physical bit coupling relation is not met indicates that no coupling relation exists between the physical bits corresponding to the gate operation.
If the gate operation meets the physical bit coupling relationship limit, the gate operation can be directly applied in the quantum chip without additional adjustment of the coupling topology. If the gate operation does not meet the physical bit coupling relationship limit, the gate operation cannot be directly applied to the quantum chip, and the coupling topological structure needs to be adjusted to be applied, so that the server can mark the gate operation needing to be adjusted as the gate operation to be adjusted.
In one embodiment, since the single-bit gate operation does not have the problem of physical bit coupling relationship limitation, the gate operation requiring the adjustment of the coupling topology mentioned in the embodiments of the present application is typically a two-bit gate operation.
For all gate operations to be executed in the quantum wires, the server may determine two qubits corresponding to each gate operation according to the coupling topology, and determine whether a coupling relationship exists between the two qubits. If there is a coupling relationship, the gate operations corresponding to the two qubits can be directly applied. If the coupling relation does not exist, the gate operation corresponding to the two quantum bits is the gate operation to be adjusted.
Fig. 4 is a schematic diagram showing the operation of a two-bit gate in a quantum wire.
In fig. 4, q0 to q4 respectively represent five qubits corresponding to fig. 3, and a coupling relationship exists between every two adjacent qubits. Fig. 4 also includes three two-bit gate operations, where a dot represents one qubit corresponding to the two-bit gate operation, and a plus ″) connected to the dot represents another qubit corresponding to the two-bit gate operation.
The two-bit controlled NOT-NOT (i, j) will be described as an example. I in CONTROL-NOT (i, j) represents the number of CONTROL qubits in the two qubits corresponding to the two-bit gate operation, i.e. the dots in fig. 4, and j represents the number of target qubits in the two qubits corresponding to the two-bit gate operation, i.e. the plus sign in fig. 4. Thus, the three two-bit gate operations in FIG. 4 are denoted CONTROL-NOT (q0, q1), CONTROL-NOT (q1, q3) and CONTROL-NOT (q1, q4), respectively.
As can be seen from fig. 3 and 4, the physical bit Q0And Q1There is a coupling relationship between the two, the gate operation CONTROL-NOT (Q0, Q1) can be directly applied, the physical bit Q1And Q3Q, Q1And Q4If no coupling relation exists between the two gate operations, the gate operations CONTROL-NOT (q1, q3) and CONTROL-NOT (q1, q4) are applied after the coupling topological structure is adjusted, and the gate operations are to be adjusted.
S103: and adjusting the coupling topological structure through the SWAP gate operation according to the gate operation to be adjusted.
In the embodiment of the application, the server can adjust the coupling topological structure by adding the SWAP gate operation according to the determined gate operation to be adjusted, so as to realize the application of the gate operation to be adjusted in the quantum chip. The SWAP gate operation is a commonly used two-bit gate operation, and can perform a SWAP operation on two qubits.
In one embodiment, the server may determine, according to a relationship between two qubits corresponding to the gate operation to be adjusted and the topology, a number of SWAP gate operations that need to be added when adjusting the coupling topology. Then, the server can adjust the position of each quantum bit in the coupling topological structure through the determined operation of the plurality of SWAP gates, and exchange two nonadjacent quantum bits into two adjacent physical bits to establish a coupling relation between the two quantum bits corresponding to the operation of the gate to be adjusted, so as to realize the application of the operation of the gate to be adjusted.
That is, by switching the sequence of two adjacent qubits each time through the SWAP gate operation, until the positional relationship of two qubits corresponding to the gate operation to be adjusted is changed from non-adjacent to adjacent, a coupling relationship can be provided between the two qubits, so as to implement the application of the gate operation to be adjusted.
Specifically, the server may determine a distance between two qubits corresponding to the gate operation to be adjusted, and determine a plurality of SWAP gate operations corresponding to the adjustment of the coupling topology according to the obtained distance. Wherein the distance between two qubits can be represented by the number of qubits spaced between the two qubits.
As shown in fig. 4, qubits q1 and q3 are separated by 1 qubit, and their distance can be represented as 1, and qubits q1 and q4 are separated by 2 qubits, and their distance can be represented as 2.
In one embodiment, the server may determine the number of SWAP gate operations required to adjust the coupling topology and the execution order between the plurality of SWAP gate operations according to the distance between two qubits in the coupling topology, with the rule of shortening the distance between the two qubits.
The distance between two quantum bits corresponding to the gate operation to be adjusted and the required number of SWAP gate operations form a positive correlation relationship, and the farther the distance is, the more the required number of SWAP gate operations is, and the closer the distance is, the less the required number of SWAP gate operations is.
And aiming at the adjustment process of the coupling topological structure by one gate operation to be adjusted, the SWAP gate operation is used for gradually reducing the distance between two corresponding quantum bits. That is, each SWAP gate operation may reduce the distance between the qubits of the two targets by 1 until the distance between the two qubits is 0. The server may then determine an order of execution between the plurality of SWAP gate operations based on the need for progressive reduction of distance by the SWAP gate operations.
It should be noted that, since the SWAP gate operation can only be performed between two qubits having a coupling relationship, when the server adjusts the coupling topology through the SWAP gate operation, only two adjacent qubits in the coupling topology can be exchanged, but not arbitrarily.
Taking the above CONTROL-NOT (q1, q4) as an example, if the distance between two qubits q1 and q4 corresponding to the gate operation to be adjusted is 2 qubits apart, and the distance is 2, the number of SWAP gate operations required for the gate operation to be adjusted can be determined to be 2. Thus, according to the requirement of the SWAP gate operation to gradually reduce the distance between qubits 1 and 4, the server may first SWAP qubits q3 and q4 using a first SWAP gate operation SWAP (q3, q4) such that the order of the five qubits is changed from q0, q1, q2, q3, q4 to q0, q1, q2, q4, q3, and then SWAP qubits q2 and q4 using a second SWAP gate operation SWAP (q2, q4) such that the order of the five qubits is changed from q0, q1, q2, q4, q3 to q0, q1, q4, q2, q 3. Then, after adjustment, a coupling relationship is established between the two qubits q1 and q4 corresponding to the CONTROL-NOT (q1, q4) gate operation, and the CONTROL-NOT (q1, q4) gate operation can be applied.
The server can also adopt the first SWAP gate operation SWAP (q1, q2) to exchange with the second SWAP gate operation SWAP (q1, q3), and can also realize the adjustment of the topology structure with the same effect.
S104: and restoring the adjusted coupling topological structure through SWAP gate operation to complete the compiling of the quantum circuit.
In the embodiment of the application, after the server finishes the application of the gate operation to be adjusted in the quantum chip, in order to avoid logic confusion of quantum bits in the quantum chip, the adjusted coupling topological structure can be restored through the SWAP gate operation, so as to maintain a normal logic sequence. By this point, the server can determine that the compilation process for the quantum wires is complete.
In an embodiment, the server may execute the same SWAP gate operation again according to the number of SWAP gate operations required for adjusting the coupling topology and the corresponding execution order determined in S102 and according to the reverse order of the execution order, so as to achieve the recovery of the adjusted coupling topology.
Taking the CONTROL-NOT (q1, q4) as an example, through adjustment of SWAP (q3, q4) and SWAP (q2, q4) by two SWAP gate operations, in the current coupling topology, the order of five qubits is q0, q1, q4, q2, q 3. After the CONTROL-NOT (q1, q4) is performed, the server can restore the coupling topology by reversing the sequence of SWAP (q2, q4) and SWAP (q3, q4) and then restoring the sequence of five qubits to q0, q1, q2, q3, q 4.
Fig. 5 is a diagram showing the compilation of quantum wires corresponding to fig. 4.
Following the example of controlling the NOT gate CONTROL-NOT (i, j) with two bits as described above, in fig. 5, the two ends of the connecting line are crossed by a cross sign "x" to indicate the SWAP gate operation.
CONTROL-NOT (q0, q1) can be directly applied to the quantum chip, and is NOT changed after being compiled, so that the two-bit operation gate in fig. 4 is the same as that in fig. 5.
CONTROL-NOT (q1, q3) in fig. 4 corresponds to the two-bit gate operation within the left-hand dashed box in fig. 5. CONTROL-NOT (q1, q3) after compilation, two SWAP gate operations are inserted. After the first SWAP gate operation is switched, the qubits q1 and q3 have a coupling relationship, CONTROL-NOT (q1, q3) is performed, and then the second SWAP gate operation restores the coupling topology.
CONTROL-NOT (q1, q4) in fig. 4 corresponds to the two-bit gate operation within the dashed box on the right in fig. 5. CONTROL-NOT (q1, q4) after compilation, four SWAP gate operations are inserted, wherein after the first SWAP gate operation is exchanged twice with the second SWAP gate operation, qubits q1 are coupled to q4, CONTROL-NOT (q1, q4) is performed, and then the third SWAP gate operation and the fourth SWAP gate operation restore the coupled topology.
In the embodiment of the application, by using the characteristics of the SWAP gate operation, a coupling relationship can be established between two quantum bits which do not have the coupling relationship in the physical bit coupling topological structure, and the smooth execution of all the two-bit gate operations in the quantum line is realized. The compiling method for the quantum circuit solves the obstacle of the quantum circuit applied to the quantum chip in a simple implementation mode, and provides a good solution for the smooth implementation of various quantum algorithms.
Based on the same inventive concept, the quantum wire compiling method based on the quantum chip coupling topology structure provided in the embodiments of the present application further provides a corresponding quantum wire compiling device based on the quantum chip coupling topology structure, as shown in fig. 6.
Fig. 6 is a schematic structural diagram of a quantum wire compiling device based on a quantum chip coupling topology according to an embodiment of the present application, which specifically includes:
a determining module 601, configured to determine a coupling topology corresponding to each physical bit in the quantum chip;
a traversal module 602, configured to traverse all gate operations to be executed by the quantum wires according to the coupling topology, and determine a gate operation that needs to be adjusted on the coupling topology, as a gate operation to be adjusted;
an adjusting module 603, configured to adjust the coupling topology structure through SWAP gate operation according to the gate operation to be adjusted;
the recovery module 604 recovers the adjusted coupling topology through the SWAP gate operation, thereby completing the compilation of the quantum wires.
The embodiments in the present application are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A quantum wire compiling method based on a quantum chip coupling topological structure is characterized by comprising the following steps:
determining a coupling topological structure corresponding to each physical bit in the quantum chip;
traversing all gate operations to be executed of the quantum lines according to the coupling topological structure, and determining the gate operation needing to be adjusted of the coupling topological structure as the gate operation to be adjusted;
adjusting the coupling topological structure through SWAP gate operation according to the gate operation to be adjusted;
and restoring the adjusted coupling topological structure through SWAP gate operation to complete the compiling of the quantum circuit.
2. The method of claim 1, wherein determining, as the gate operation to be adjusted, a gate operation that requires adjustment of the coupling topology by traversing all gate operations to be performed by the quantum wires according to the coupling topology comprises:
determining whether the quantum bit corresponding to the gate operation has a coupling relation or not according to the coupling topological structure aiming at all gate operations to be executed by the quantum line;
and determining the gate operation corresponding to the quantum bit without the coupling relation as the gate operation to be adjusted.
3. The method of claim 1, wherein adjusting the coupling topology by a SWAP gate operation in accordance with the gate operation to be adjusted comprises:
determining a plurality of corresponding SWAP gate operations when the coupling topological structure is adjusted according to the quantum bit corresponding to the gate operation to be adjusted;
and adjusting each quantum bit in the coupling topological structure through the operation of the plurality of SWAP gates, and establishing a coupling relation between the quantum bits corresponding to the operation of the gate to be adjusted.
4. The method of claim 3, wherein determining a number of SWAP gate operations corresponding to adjusting the coupling topology according to the qubits corresponding to the gate operation to be adjusted comprises:
determining two quantum bits corresponding to the gate operation to be adjusted;
and determining a plurality of corresponding SWAP gate operations when the coupling topological structure is adjusted according to the distance between the two quantum bits in the coupling topological structure.
5. The method of claim 4, wherein determining a number of SWAP gate operations corresponding to the adjustment of the coupling topology based on the distance between the two qubits in the coupling topology comprises:
and determining the number of the SWAP gate operations required for adjusting the coupling topological structure and the execution sequence among the SWAP gate operations according to the distance between the two qubits in the coupling topological structure.
6. The method of claim 5, wherein the distance is positively correlated to the number of SWAP gate operations required.
7. The method of claim 5, wherein each SWAP gate operation is configured to gradually reduce a distance between two qubits corresponding to the gate operation to be adjusted.
8. The method of claim 3, wherein adjusting the qubits in the coupling topology through the SWAP gate operations to establish the coupling relationship between the qubits corresponding to the gate operations to be adjusted comprises:
and exchanging the sequence of the two corresponding qubits through each SWAP gate operation until a coupling relation exists between the two qubits corresponding to the gate operation to be adjusted.
9. The method of claim 5, wherein recovering the adjusted coupling topology through SWAP gate operations comprises:
and recovering the adjusted coupling topological structure according to the number of the needed SWAP gate operations and the reverse order of the execution order among the SWAP gate operations.
10. A quantum wire compiling apparatus based on a quantum chip coupling topology, comprising:
the determining module is used for determining a coupling topological structure corresponding to each physical bit in the quantum chip;
the traversal module traverses all gate operations to be executed of the quantum circuit according to the coupling topological structure, determines the gate operation needing to be adjusted on the coupling topological structure and takes the gate operation as the gate operation to be adjusted;
the adjusting module adjusts the coupling topological structure through SWAP gate operation according to the gate operation to be adjusted;
and the recovery module recovers the adjusted coupling topological structure through the SWAP gate operation to complete the compiling of the quantum circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010887028.7A CN112115655A (en) | 2020-08-28 | 2020-08-28 | Quantum line compiling method and device based on quantum chip coupling topological structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010887028.7A CN112115655A (en) | 2020-08-28 | 2020-08-28 | Quantum line compiling method and device based on quantum chip coupling topological structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112115655A true CN112115655A (en) | 2020-12-22 |
Family
ID=73804586
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010887028.7A Pending CN112115655A (en) | 2020-08-28 | 2020-08-28 | Quantum line compiling method and device based on quantum chip coupling topological structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112115655A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114548414A (en) * | 2022-02-22 | 2022-05-27 | 合肥本源量子计算科技有限责任公司 | Method, device, storage medium and compiling system for compiling quantum circuit |
| CN114912619A (en) * | 2021-02-08 | 2022-08-16 | 合肥本源量子计算科技有限责任公司 | Quantum computing task scheduling method and device and quantum computer operating system |
| CN115034169A (en) * | 2022-06-21 | 2022-09-09 | 中国人民解放军战略支援部队信息工程大学 | Superconducting quantum chip EDA framework based on quantum gate circuit model |
| CN115146782A (en) * | 2021-03-31 | 2022-10-04 | 合肥本源量子计算科技有限责任公司 | Quantum line compiling method, device, compiling framework and quantum operating system |
| CN115470924A (en) * | 2022-02-25 | 2022-12-13 | 合肥本源量子计算科技有限责任公司 | Quantum computer and execution method of quantum computing task |
-
2020
- 2020-08-28 CN CN202010887028.7A patent/CN112115655A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114912619A (en) * | 2021-02-08 | 2022-08-16 | 合肥本源量子计算科技有限责任公司 | Quantum computing task scheduling method and device and quantum computer operating system |
| CN115146782A (en) * | 2021-03-31 | 2022-10-04 | 合肥本源量子计算科技有限责任公司 | Quantum line compiling method, device, compiling framework and quantum operating system |
| WO2022206842A1 (en) * | 2021-03-31 | 2022-10-06 | 合肥本源量子计算科技有限责任公司 | Quantum circuit compilation method and device, compilation framework and quantum operating system |
| CN114548414A (en) * | 2022-02-22 | 2022-05-27 | 合肥本源量子计算科技有限责任公司 | Method, device, storage medium and compiling system for compiling quantum circuit |
| CN114548414B (en) * | 2022-02-22 | 2023-10-10 | 合肥本源量子计算科技有限责任公司 | Method, device, storage medium and compiling system for compiling quantum circuit |
| CN115470924A (en) * | 2022-02-25 | 2022-12-13 | 合肥本源量子计算科技有限责任公司 | Quantum computer and execution method of quantum computing task |
| CN115470924B (en) * | 2022-02-25 | 2024-04-05 | 本源量子计算科技（合肥）股份有限公司 | Quantum computer and execution method of quantum computing task |
| CN115034169A (en) * | 2022-06-21 | 2022-09-09 | 中国人民解放军战略支援部队信息工程大学 | Superconducting quantum chip EDA framework based on quantum gate circuit model |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112115655A (en) | Quantum line compiling method and device based on quantum chip coupling topological structure | |
| AU2021245164B2 (en) | Quantum entangled state processing method and apparatus, device, storage medium, and product | |
| Lawler | Matroid intersection algorithms | |
| KR102554578B1 (en) | XX coupler for flux qubits | |
| EP1264451B1 (en) | Method and system for controlling data traffic in a network | |
| Trodden et al. | Cooperative distributed MPC of linear systems with coupled constraints | |
| Sethi et al. | Optimal financing of a corporation subject to random returns | |
| DE112018003087B4 (en) | ON-CHIP NOISE REDUCTION OR REDUCTION OF THE SUPPLY VOLTAGE USING LOCAL DETECTION LOOPS IN A PROCESSOR CORE | |
| AU2001250382A1 (en) | Method and system for controlling data traffic in a network | |
| Ahn et al. | Intermittent iterative learning control | |
| US20210119900A1 (en) | Intelligent decision-making method and device for uav formation information interaction topologies in communication interference | |
| Jia | On solving event-based optimization with average reward over infinite stages | |
| Papadimitriou et al. | A new class of/spl epsi/-optimal learning automata | |
| Brown | Some Poisson approximations using compensators | |
| Glazebrook et al. | On single-machine scheduling with precedence relations and linear or discounted costs | |
| Grundke | Importance sampling for integrated market and credit portfolio models | |
| Liang et al. | Hybrid event-triggered impulsive flocking control for multi-agent systems via pinning mechanism | |
| Lin et al. | How to progress a database (and why) I. Logical foundations | |
| CN115629613B (en) | Formation fault-tolerant control method for multiple intelligent agents | |
| Bahadoran et al. | Strong hydrodynamic limit for attractive particle systems on Z | |
| Yang et al. | Stability and synchronization of directed complex dynamical networks with random packet loss: the continuous‐time case and the discrete‐time case | |
| CN112272141B (en) | Intra-domain route protection method based on key network state | |
| WO2023189886A1 (en) | Information processing device | |
| CN110986981B (en) | Path obstacle adding method for multi-robot path planning | |
| Chung et al. | Supervisory control with variable lookahead policies: Illustrative example |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |