CN1277181C - Single-output feedback-free sequential test response compression circuit - Google Patents
Single-output feedback-free sequential test response compression circuit Download PDFInfo
- Publication number
- CN1277181C CN1277181C CN 03149074 CN03149074A CN1277181C CN 1277181 C CN1277181 C CN 1277181C CN 03149074 CN03149074 CN 03149074 CN 03149074 A CN03149074 A CN 03149074A CN 1277181 C CN1277181 C CN 1277181C
- Authority
- CN
- China
- Prior art keywords
- merchant
- output
- chain
- compressor
- response
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Abstract
The present invention relates to a test response compressor in chip testability design. The present invention provides a single-output time sequence compression circuit which is a quotient-compressor. The compression circuit comprises a response diffusion network and a quotient-shifting register chain. The present invention can process the error cancellation and the indefinite position in scan output and can provide complete diagnosis capability. The design of a diffusion matrix of the response diffusion network accords with three rules: (1), any two rows in the diffusion matrix are in non-equivalence; (2), each row in the diffusion matrix contains odd number of 1; (3), the rank of the diffusion matrix transposition is equal to the input of the quotient-compressor. Because the quotient-compressor is the single-output compression circuit, the present invention has the characteristic of high compression rate. Using the full scan of the quotient-compressor can increase a scanning chain to three times, shorten the length of the scanning chain, and reduce the test time. In addition, a special designed aiming at a fault model easy to occur in the scan test ensures no erroneous judgement situation. The quotient-compressor can also process the indefinite position. If an operation for diagnosis is inserted, the quotient-compressor provides complete collection for the output information of the scanning chain.
Description
Technical field
The present invention relates to the measurability technical field of integrated circuit (IC) chip, the single output that particularly relates in a kind of chip full scan design does not have feedback timing sequence test response compressor circuit.
Background technology
Along with the development of technology, be accompanied by the development of system level chip especially, logical block (such as microprocessor, storer, DSPs, I/O controller) integrated on the single chip is more and more, and its function is also come complexity more, has brought a lot of new challenges to test.These challenges mainly comprise: 1) test frequency of testing apparatus does not catch up with the raising 2 of chip frequency) test duration is long, causes testing cost significantly to increase by 3) testing apparatus memory size less than 4) chip can be used as the test pin deficiency of full scan design.The scheme of a feasible solution test pin deficiency is that test response is compressed, and generally is to compress finishing this response by the test response compressor circuit that adopts a built-in chip type.
The main thought of test response compression is: at first design a built-in response compressor reducer, this compressor reducer can be compressed to one or several output with test response output as far as possible, and these outputs output to testing apparatus by pin.For general design for Measurability, can be used as the pin that scans input and output and limit.These qualifications may be the needs that come from layout design, also might be the actual test resource situations of the testing apparatus taken into account.Like this, if output be compressed tail off after, just can have the more pins to be used to design more test scan chain, thereby shorten the length of long scan chain, reduced be used to scan into/scan the vectorial time.And in the sweep test, main time consumption is exactly on the motion scan vector, and therefore compressing us by test response can significantly reduce the sweep test time.Simultaneously, owing to increased scan chain, the data volume on the single scan chain will correspondingly reduce, and therefore, the test response compression has also reduced the test capacity that each test channel needs.
For test response output several characteristic, these features being arranged is that we design the problem that different compressor circuits must be faced: 1) in the unit interval, the number that breaks down is fewer, generally can be above 4.2) may comprise a lot of uncertain positions in the response.Uncertain position is meant that its value is unascertainable in emulation.3) must be able to provide the method that simply can collect complete diagnostic message, and this diagnosis must there be assumed condition.The compressor circuit scheme that is suitable for solving above three problems can be divided into two big classes: combination compressor circuit and sequential compressor circuit.The combination compressor circuit is meant by simple combinational circuit realizes compressor circuit.This compressor circuit method for designing is fairly simple, and the simplest a kind of realization is exactly to utilize the XOR tree.Its theoretical foundation is based on parity checking.By the structure of rational design XOR tree and the number of planning compression output, can solve three problems proposed above targetedly.A weak point of combinational circuit is that compressibility is lower, and can not provide completely at scheme, and its diagnosis must be based on some hypothesis, and these hypothesis can't guarantee.The sequential compressor circuit is to realize compression by shift register.This compressor circuit ratio of compression is higher relatively, and False Rate is also lower.But the most direct sequential circuit ratio of compression such as M worker SR in the response compression, can not effectively handle uncertain position.Its usual way is to go to eliminate these nondeterministic statements by rational design for Measurability.And uncertain position can not be eliminated in large-scale SOC design fully.Therefore want to make that the sequential compressor circuit is still effective in the test response compression of SOC, just must be changed it.The sequential compressor circuit that creation makes new advances at above-mentioned three features.
Summary of the invention
The object of the present invention is to provide a kind of single output not have feedback timing sequence test response compressor circuit.
The present invention proposes a new merchant-compressor reducer.This circuit is to propose on the basis of fully studying three essential characteristics of above-mentioned test vector, also is the compressor circuit of a sequential.It has not only inherited advantages such as sequential compressor circuit ratio of compression height (have only an output, ratio of compression is the highest) and test vector be irrelevant, has also avoided few fault cancellation by rational design.Go out for the uncertain position that occurs in defeated and also can effectively handle.And can provide complete diagnosis capability.
The present invention has constructed a kind of new sequential compressor circuit: merchant-compressor reducer.This circuit comprises two ingredients: response proliferation network and merchant-shift register chain.Its hardware is realized with reference to figure 1.Fig. 1 has described the merchant-compressor circuit framework of one 5 input.As can be seen from Figure 1, the response proliferation network mainly is made of the XOR tree, by being connected in merchant-shift register chain with door; Merchant-shift register chain of alternately forming by XOR gate and register.Except the XOR tree, proliferation network has also comprised several and door, and these have formed a screened circuit with door.Can make merchant-shift register chain work in compact model and scan pattern.Merchant-shift register chain alternately is made up of several adjacent XOR gate and register.The output of the scan chain the when input of response proliferation network derives from the chip full scan, its output is corresponding to the input of merchant-shift register chain.Merchant-shift register chain also has an input qin and output qout except having the data-interface with the response proliferation network.Input qin be used to provide initialization seed and test vector, and this input end is optional; Qin is not necessary, can be used for scan chain of many designs by its setting value 0 is come simplified design.Single output qout is used to export compression result.Some XOR gate and the register that waits number are used for the response compression.
For a concrete merchant-compressor reducer, its basic configuration parameter has following two: input number N, the progression K of merchant-shift register chain.For reliable fault discovery ability and diagnosis capability are provided, for our merchant-compressor reducer of concrete application: N equals K.The progression that is to say merchant-shift register chain is corresponding with the output of scan chain always.
For complete diagnosable ability can be provided, need a kind of mechanism the output of scan chain can not to be added in the diagnosis buffer memory of collecting testing apparatus of compression.Utilize these information, the diagnostic routine that calls an aftertreatment just can carry out the location of mistake of gate leve to circuit.In merchant-compressor reducer, this mechanism is to realize by the mode of operation of controlling merchant-shift register chain.Following table has been listed corresponding mode of operation and control signal corresponding.
Table 1: the mode of operation of merchant-shift register chain
| ?Qmask ? | qin ? | qout ? | Mode of operation |
| ?0 ? | Initialization seed and test vector are provided | Serial scan chain output | Scan pattern |
| ? 1 ? | ? 0 ? | Merchant's output, for testing apparatus relatively | Compact model |
As can be seen, for merchant-shift register chain two kinds of mode of operations are arranged: scan pattern and compact model.Scan pattern is to be used for content with shift register chain to scan out and observe, and inserts new seed to chain of registers simultaneously.Compact model is to utilize the linear compression principle that chip output to be measured is compressed.
The scan pattern of merchant-shift register chain provides a kind of ability that can obtain the information of all scan chain outputs.A simple testing process has comprised following three steps:
1) initialization merchant-shift register chain is 0:qin=0; Qmask=0;
2) catch the outputing in the register in merchant-shift register chain of scan chain.Signal at that time: qin=0; Qmask=0
3) freeze the clock of all scan chains, utilize scan pattern will discuss-content in the shift register chain scans out, the merchant-shift register chain of initialization simultaneously is 0:qin=0, qmask=1;
Repeat the output that above three steps just can obtain scan chain by shooting.This process can be described a test protocol by adopting STIL, uses ATE (automatic test equipment) to realize automatically.After the data that are relevant to scan chain output by shooting of needs are collected into the debugging impact damper of testing apparatus, uses an expression respond proliferation network equation calculate the actual output of scan chain.These outputs can be used as the input of an ADP, and chip is carried out localization of fault.
Gordian technique of the present invention is to respond the method for designing of proliferation network.
If the response proliferation network in the invention adopts XOR gate to realize, can accurately characterize it with a diffusion matrix so.In this matrix, an output of proliferation network is shown in input of each line display, each tabulation.If i is capable, j classifies 1 as, represents that so i input of proliferation network is relevant with j output by the XOR tree.The relevant meaning is meant if there is an input to break down, and do not have other inputs to break down and uncertain position, and this fault will be reacted in the output relevant with it so.This definition has been arranged, and the response proliferation network can be represented with a following diffusion matrix in the accompanying drawing 1:
In this matrix, the 1st of proliferation network the input and the 2nd, 3 as can be seen, 5 outputs are relevant.So,, will be diffused into so on 2,3,5 registers if fault has taken place in the 1st output.This fault will be observed 3 times like this.
Because the one-to-one relationship of diffusion matrix and response proliferation network, in the later statement of the present invention, the object of design will all be a diffusion matrix, can realize the conversion that it and actual XOR are set with a very simple integration algorithm.A basic configuration above having mentioned merchant-compressor reducer is: K=N.For diffusion matrix, require matrix columns and line number equal fully exactly, in the design theorem below, this prerequisite is arranged all.
In the background of invention, mentioned the characteristics aspect three of structured testing response output,, hereinafter diffusion matrix has been proposed concrete design rule at these three characteristics.
These rules of description for convenience need at first be introduced one " equivalence " notion.
Two vectorial R1 that [definition] tieed up for two k-, R2, if of equal value following two conditions of R1 and R2 are set up:
1) comprising 1 number among R1 and the R2 equates
2) comprise among R1 and the R2 that 1 number equates and be 1
Perhaps i, j|P
R1(i)-P
R2(i) |=| P
R1(j)-P
R2(j) | (i, j＜=k) wherein, P
R1(i) and P
R1(j) refer to i in vectorial R1, j 1 residing position.P
R2(i) and P
R2(j)
Be illustrated in i among the vectorial R2, j 1 residing position
Providing two design theorems below guarantees not judge by accident for few mistake:
[theorem 1] if any two provisional capital non-equivalences in the diffusion matrix of a proliferation network correspondence, merchant-compressor reducer can be found any 1 or 2 faults so.These faults can occur on any scan chain, and the time of appearance can identical bat also can be to clap in difference.
[theorem 2] if 1 contained number of any two provisional capital non-equivalences and each row is an odd number in the diffusion matrix of a proliferation network correspondence, merchant-compressor reducer finally must be found 1 so, 2 or arbitrary odd number mistake.These mistakes can appear at any scan chain, and the time of appearance can be that identical bat also can be different the bat.
Because it is of equal value not having two row in the diffusion matrix, thus the situation that does not exist the related register of a mistake to offset fully mutually through displacement back and another wrong related register, so theorem 1 is set up.For theorem 2, if there is 1 mistake to be diffused in merchant-chain of registers, so infected the number of registers is an odd number.After the 2nd mistake was implanted, because wrong cancellation effect, at this moment, the infected the number of registers of staying in the chain of registers was an even number.Such as, if the related register of two mistakes has 1 position to cancel out each other, stay so that infected register number will subtract 2 in the chain of registers.It is similar to cancel out each other in 2 positions, so after the even number mistake was implanted, the register number that keeps error message was always even number, it is 0 situation that theorem 1 has guaranteed can not occur after 2 wrong implantation remaining error message register number.When the 3rd fault implanted, the number of registers that remain with error message this moment had become odd number again, may for: 1,3,5.......So all situations of counteracting also can not occur.When the 4th fault implanted, the number of registers that remains with error message had become even number again, and may be 0.Obviously, be that 0 expression will be judged by accident.So, theorem 2 can not guarantee for 4 and higher even number mistake do not judge by accident.And for greater than 3 odd number mistake, similar when its situation and 3 are wrong, the number of registers that keeps error message always is an odd number, just observed at least 1 time, so can not judge by accident.
The diffusion matrix П of analysis chart 1 proliferation network correspondence can find that it meets the condition that theorem 2 requires.Each provisional capital other row equivalents of getting along well.And each provisional capital comprises 3 1s.1 contained number of all row is relative and is 3 in the design of this example.The method for designing of odd numbers 1 such as use can simplified design, and good delay performance can be provided.Be that 3 design can be so that the area cost of compressor reducer be less during design particularly for odd number.
When estimating for the response compression performance, one very important index be exactly the processing power of this compressor reducer for uncertain position.Since the continuous increase of chip design scale, the method for the uncertain position of the elimination that has proposed, and such as increasing observation point, the way that increases may command point is difficult to prove effective fully.And because the existence of feedback circuit, make the problem of the uncertain position of common sequential compressor circuit intractable.The response compressor reducer that this paper proposes is owing to cancelled feedback circuit, so when having uncertain position to implant for input, this uncertain position will be diffused in merchant-chain of registers, to scanned out after the K bat at most, can not continued to shield the mistake that other are come by the proliferation network diffusion.Below theorem the processing power for uncertain position that merchant-compressor reducer has has been described:
[theorem 3] for the single fault that is accompanied by 1 uncertain position, will be found by merchant-compressor reducer so if two conditions in the theorem 2 all are satisfied.
Since be of equal value without any two row in the theorem 2 regulation diffusion matrix, therefore single uncertain position can not shield the register-bit that single error is spread after by the proliferation network diffusion fully.Have at least 1 register that has error message to be observed.Certainly, if having a plurality of uncertainly when implanting, situation is just different.A plurality of uncertain positions diffuse into a huge zone, and the register that makes mistake be diffused into might be completely contained in this zone, thereby is thoroughly shielded.
For a compressor reducer, can provide complete diagnostic message to be difficult to.Because response compression generally all is a lossy compression method, thus can't be complete collect output on the actual scanning chain.The front was described, and the merchant-chain of registers in the merchant-compressor reducer can be reconfigured as the scan chain of a serial, and cooperated by corresponding signal, can reach the purpose of collecting complete information.Certainly this is a kind of possibility, below a theorem will guarantee that this possibility comes true:
[theorem 4] merchant-compressor reducer can be collected complete scan chain output error message, and these mistakes can be to occur in synchronization also can occur in the different moment, when the diffusion matrix that designs satisfies:
Order (transposition of diffusion matrix)=N
If we suppose that proliferation network is input as the t moment: X
1=[x
1(t), x
2(t), x
3(t), Λ Λ, x
n(t)]
T, the state of each register of merchant-chain of registers is: S
t=[s
1(t), s
2(t), s
3(t), Λ Λ, s
m(t)]
TП is the diffusion matrix of proliferation network correspondence, has following equation to set up so:
П
T*X
tS
t-1＝S
t
S
T-1Be that merchant-chain of registers is at t-1 state constantly.If we insert seed with S by initialization
T-1Be initialized as 0, following formula can be reduced to so:
П
T*X
t＝S
t
In following formula, we can by will discuss-chain of registers controls to scan pattern and obtains S
tValue.Therefore in fact theorem 4 has become a problem that solves matrix equation: design matrix П how
TMake X in the following formula
tWell-determined separating arranged.Therefore can use Cramer's rule proof theorem 4.
Giving one example illustrates this diagnosis capability, for merchant-compressor reducer of Fig. 1, takes place if find to be carved with fault when t, and the diagnostic message of response is collected flow process and is inserted into testing process so, and the status information of collecting t merchant-chain of registers constantly is:
It is different from the output result of expectation:
We utilize S
t SValue can calculate the value of corresponding scan chain output:
Can utilize Gaussian elimination to separate the output valve that above-mentioned equation obtains scan chain:
Relatively
Can diagnose out the 2nd and the 3rd scan chain that mistake has taken place.
Top content has elaborated the ability of discovery of assurance response compressor reducer for few fault, and for the processing power of uncertain position, some of diagnosis capability design theorems entirely.Summarize theorem 1,2,3,4 can draw the recommendation design rule of a merchant-compressor reducer, meet these rules and can guarantee that compressor reducer can handle 1,2,3 or other odd number mistakes, can have the ability of handling uncertain position, and diagnosis capability completely can be provided:
[design rule]:
4) any two provisional capital non-equivalences in the diffusion matrix;
5) odd number 1 is contained in each provisional capital in the diffusion matrix;
6) order of diffusion matrix transposition equals to discuss-input of compressor reducer;
Description of drawings
Fig. 1 is that the gate leve of the merchant-compressor reducer of one 5 input is realized circuit diagram;
Fig. 2 is the chip full scan design for Measurability frame diagram that has merchant-compressor reducer;
Fig. 3 is a design for Measurability process flow diagram of using merchant-compressor reducer.
Among Fig. 1, comprised two parts, one of them part is by 10 XOR gate and 5 controlled XOR trees that constitute with door, is called as the response proliferation network.Another part is called as merchant-shift register chain by 5 XOR gate and 5 shift register chains that register is alternately formed.Represent XOR gate with the circle cross in the drawings, use and door symbolic representation and door.
Among Fig. 2, constitute by some scanning connection chains and a merchant-compressor reducer.The output of scan chain is by observing by pin output after the merchant-compressor compresses.
Embodiment
The present invention is applied to test response is compressed.Fig. 2 has described out the full scan design framework that has merchant-compressor reducer.As can be seen from the figure, the response compressor reducer is designed in the output of scan chain.The output of a plurality of scan chains is compressed into an output, outputs on the testing apparatus by a scanning output pin and compare.Therefore from whole design cycle, the design of response compressor reducer basically can be separate with the design of scan chain.Therefore the insertion that responds compressor reducer does not need to revise the design cycle of former chip, need not revise the design for Measurability flow process of former chip yet.
Fig. 3 has listed the design for Measurability flow process of using merchant-compressor reducer.As can be seen, can be divided into following steps for a design for Measurability flow process of using merchant-compressor reducer:
1) comprehensive, the scan chain design.Need plan the pin that can be used for the scan chain design in this step.Because merchant-compressor reducer is single output, be used for compressor circuit output so only need reserve an output pin, other pins may be used to input.In these inputs, only need reserve a pin is used for qmask, and other may be used to the input as scan chain.Therefore, for the available scanning pin M of regulation, we can design M-2 bar scan chain at most.The number of this step planning scan chain design inserts scan chain simultaneously in combined process;
2) merchant-compressor reducer is inserted in design.After scan chain designed, three design rules that propose according to the present invention generated a qualified diffusion matrix automatically.Use synthesis tool then, generate proliferation network automatically.Proliferation network just is connected with merchant-chain of registers can obtains complete merchant-compressor reducer.Again it is covered in the whole design as an independent design module.Then DRC is carried out in the design of integral body one time, check whether the excessive or deficiency of other electricity aspects of delay is arranged.
3) design produces test vector at scan chain to utilize atpg tool, and is translated into parallel structure, and the accent fault simulator obtains response results by shooting.And output in the software simulator of a merchant-compressor reducer.This software simulator can simulate compression output result fast according to concrete configuration.And record in the vector file.
4) the scan chain input that atpg tool is produced and the result of merchant-compressor reducer software simulation merge in the test vector, add the control signal of qmask simultaneously.Output is as final test vector.Promptly merge the result that vector sum compressor reducer simulator that atpg tool produces obtains, draw final test vector.
In this flow process, the diffusion matrix that generates merchant-compressor reducer automatically is a key issue.We will consider the influence of the XOR tree of design to time delay in the algorithm that generates diffusion matrix automatically.For the diffusion matrix that meets above-mentioned three design rules, because the difference of each row value, the delay of XOR tree on critical path that may cause being generated has very big difference.If the XOR of design tree is respectively imported the average change of XOR gate distribution on the path, then overall performance just can reach optimization.
The present invention is because merchant-compressor reducer is single output compressor circuit, so have the high characteristics of compressibility.The full scan design of using merchant-compressor reducer can increase by 2 times of scan chains, has shortened the length of scan chain, has also just reduced the test duration.Carry out special design at the fault model that occurs easily in the sweep test simultaneously, guarantee not judge by accident situation.Merchant-compressor reducer can also be handled the ability of uncertain position.If the operation of some diagnosis is inserted into, merchant-compressor reducer can provide the ability of collecting scan chain output information fully.
Claims (3)
1, a kind of merchant-compressor circuit comprises response proliferation network and two ingredients of merchant-shift register chain, it is characterized in that,
1) by some XOR gate and response proliferation network some and that door constitutes,
2) merchant-shift register chain of alternately forming by XOR gate and register;
Comprise N scan chain as test circuit, the response proliferation network comprises:
1) N input end is connected to the output of N above-mentioned test circuit scan chain;
2) 1 input end is used to control the mode of operation of merchant-shift register chain;
3) some XOR gate, the input of XOR gate is connected to the output of scan chain, and the output of XOR gate is connected to the input with door;
4) some and door is connected the output of XOR gate with the input of door, is connected the input in merchant-shift register chain with the output of door;
Comprise N scan chain as test circuit, merchant-shift register chain comprises:
1) 1 output terminal is connected in register, is used to export compression result;
2) 1 input end connects and register, is used to provide initialized seed and test vector, and this input end is optional;
3) N input end, a N XOR gate and N register, an above-mentioned N input end is connected to the input of an above-mentioned N XOR gate, and the output of an above-mentioned N XOR gate is connected to the input of an above-mentioned N register;
The design rule of the diffusion matrix of response proliferation network correspondence is:
1) any two provisional capital non-equivalences in the diffusion matrix;
2) odd number 1 is contained in each provisional capital in the diffusion matrix;
3) order of diffusion matrix transposition equals to discuss-the input number of compressor reducer.
According to the merchant-compressor circuit of claim 1, it is characterized in that 2, scan pattern is used for the content scanning of merchant-shift register chain is gone out to observe, and inserts new seed to chain of registers simultaneously; Compact model is to utilize the linear compression principle that chip output to be measured is compressed.
3, a kind of method that generates merchant-compressor reducer, step is as follows:
1. comprehensive, the scan chain design, the number of this step planning scan chain design inserts scan chain simultaneously in combined process;
2.) insert merchant-compressor reducer, the design rule generation response proliferation network circuit according to the diffusion matrix that responds the proliferation network correspondence carries out DRC then, and these design rules comprise:
I. any two provisional capital non-equivalences in the diffusion matrix;
II. odd number 1 is contained in each provisional capital in the diffusion matrix;
III. the order of diffusion matrix transposition equals to discuss-the input number of compressor reducer;
3.) utilize automatic test vector Core Generator to produce test vector at scan chain design, and carry out circuit simulation and draw the output response, the software simulator of merchant-compressor reducer will export the response conduct and import data, and emulation draws compression result;
4.) will discuss-compression result that the software simulator of compressor reducer draws, as final test response vector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03149074 CN1277181C (en) | 2003-06-25 | 2003-06-25 | Single-output feedback-free sequential test response compression circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03149074 CN1277181C (en) | 2003-06-25 | 2003-06-25 | Single-output feedback-free sequential test response compression circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1460923A CN1460923A (en) | 2003-12-10 |
| CN1277181C true CN1277181C (en) | 2006-09-27 |
Family
ID=29591448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 03149074 Expired - Lifetime CN1277181C (en) | 2003-06-25 | 2003-06-25 | Single-output feedback-free sequential test response compression circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1277181C (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100367676C (en) * | 2004-05-27 | 2008-02-06 | 中国科学院计算技术研究所 | Method and compressing circuits carried by high code rate convolutional codes |
| WO2007069098A1 (en) | 2005-11-04 | 2007-06-21 | Nxp B.V. | Integrated circuit test method and test apparatus |
| WO2007098167A2 (en) * | 2006-02-17 | 2007-08-30 | Mentor Graphics Corporation | Multi-stage test response compactors |
| CN102859457B (en) * | 2010-04-26 | 2015-11-25 | 株式会社日立制作所 | Time series data diagnosis compression method |
| CN102305912B (en) * | 2011-07-29 | 2014-06-04 | 清华大学 | Low power consumption integrated circuit testing device with compressible data and method using same |
| CN102967824B (en) * | 2011-08-31 | 2016-05-25 | 上海华虹集成电路有限责任公司 | A kind of scan chain control circuit and its implementation |
| CN111103531B (en) * | 2018-10-26 | 2022-11-01 | 瑞昱半导体股份有限公司 | Chip and method for manufacturing the same |
| CN113311319B (en) * | 2021-06-01 | 2024-02-13 | 成都海光集成电路设计有限公司 | Integrated circuit chip and configuration method, and test system and test method |
-
2003
- 2003-06-25 CN CN 03149074 patent/CN1277181C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CN1460923A (en) | 2003-12-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110618929B (en) | Verification platform and verification method of symmetric encryption algorithm based on UVM | |
| US6609229B1 (en) | Method for automatically generating checkers for finding functional defects in a description of a circuit | |
| CN1654973A (en) | Scan based self-testing structure and method adopting weighted scanning strobe signal | |
| CN1818912A (en) | Scalable reconfigurable prototyping system and method | |
| CN101499937A (en) | Software and hardware collaborative simulation verification system and method based on FPGA | |
| US8689070B2 (en) | Method and system for scan chain diagnosis | |
| US6886145B2 (en) | Reducing verification time for integrated circuit design including scan circuits | |
| CN1277181C (en) | Single-output feedback-free sequential test response compression circuit | |
| CN1267739C (en) | Scanning design with nano-scanning design test cost and test vector input method | |
| US20130024830A1 (en) | Fault Diagnosis Based On Design Partitioning | |
| US20160245866A1 (en) | Dynamic design partitioning for diagnosis | |
| CN104950241A (en) | Integrated circuit and method for establishing scanning test framework in integrated circuit | |
| US9015543B2 (en) | Diagnosis-aware scan chain stitching | |
| US20080313499A1 (en) | Debug circuit | |
| US20020120891A1 (en) | Method for diagnosing failures using invariant analysis | |
| CN201522707U (en) | Software and hardware cooperated simulation verification system based on FPGA | |
| Mitra et al. | X-tolerant test response compaction | |
| Huang et al. | Errortracer: Design error diagnosis based on fault simulation techniques | |
| Gaber et al. | Improved automatic correction for digital VLSI circuits | |
| CN101529388A (en) | Test method for non-boundary scan digital device | |
| CN104636509A (en) | Method for verifying timing problem in gate-level simulation | |
| CN1548974A (en) | Super large scale integrated circuit testing channel compression method and circuit | |
| CN1928578A (en) | Test circuit and test method thereof | |
| Tuerk et al. | Model checking PSL using HOL and SMV | |
| CN114328161A (en) | Java interface test method and device, storage medium and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20031210 Assignee: Zhongke Jianxin (Beijing) Technology Co.,Ltd. Assignor: Institute of Computing Technology, Chinese Academy of Sciences Contract record no.: X2022990000752 Denomination of invention: A Single Output Time Sequence Test Response Compression Circuit Without Feedback Granted publication date: 20060927 License type: Exclusive License Record date: 20221009 |
|
| EE01 | Entry into force of recordation of patent licensing contract | ||
| CX01 | Expiry of patent term |
Granted publication date: 20060927 |
|
| CX01 | Expiry of patent term |