CN102292715B - 存储器装置功率管理器及其方法 - Google Patents

存储器装置功率管理器及其方法 Download PDF

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Publication number
CN102292715B
CN102292715B CN201080005310.2A CN201080005310A CN102292715B CN 102292715 B CN102292715 B CN 102292715B CN 201080005310 A CN201080005310 A CN 201080005310A CN 102292715 B CN102292715 B CN 102292715B
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Prior art keywords
memory
power state
die
memory device
logic
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Chinese (zh)
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CN102292715A (zh
Inventor
乔·M·杰德罗
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Micron Technology Inc
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Micron Technology Inc
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Priority to CN201510124635.7A priority Critical patent/CN104699226B/zh
Publication of CN102292715A publication Critical patent/CN102292715A/zh
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/325Power saving in peripheral device
    • G06F1/3275Power saving in memory, e.g. RAM, cache
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215Monitoring of peripheral devices
    • G06F1/3225Monitoring of peripheral devices of memory devices
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4022Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/148Details of power up or power down circuits, standby circuits or recovery circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Power Sources (AREA)
  • Semiconductor Memories (AREA)
CN201080005310.2A 2009-01-23 2010-01-22 存储器装置功率管理器及其方法 Active CN102292715B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510124635.7A CN104699226B (zh) 2009-01-23 2010-01-22 存储器装置功率管理器及其方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/359,039 2009-01-23
US12/359,039 US9105323B2 (en) 2009-01-23 2009-01-23 Memory device power managers and methods
PCT/US2010/021820 WO2010085657A2 (en) 2009-01-23 2010-01-22 Memory device power managers and methods

Related Child Applications (1)

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CN201510124635.7A Division CN104699226B (zh) 2009-01-23 2010-01-22 存储器装置功率管理器及其方法

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CN102292715A CN102292715A (zh) 2011-12-21
CN102292715B true CN102292715B (zh) 2015-04-22

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CN201080005310.2A Active CN102292715B (zh) 2009-01-23 2010-01-22 存储器装置功率管理器及其方法
CN201510124635.7A Active CN104699226B (zh) 2009-01-23 2010-01-22 存储器装置功率管理器及其方法

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US (2) US9105323B2 (https=)
EP (2) EP2389633B1 (https=)
JP (2) JP5762312B2 (https=)
KR (1) KR101609311B1 (https=)
CN (2) CN102292715B (https=)
TW (3) TWI514409B (https=)
WO (1) WO2010085657A2 (https=)

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CN111052134B (zh) * 2017-08-31 2024-04-26 快图有限公司 外围处理设备
TWI659308B (zh) * 2017-12-08 2019-05-11 旺宏電子股份有限公司 記憶體裝置及其操作方法
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Also Published As

Publication number Publication date
TW201604887A (zh) 2016-02-01
EP2389633A4 (en) 2012-10-31
WO2010085657A2 (en) 2010-07-29
CN104699226A (zh) 2015-06-10
EP2389633A2 (en) 2011-11-30
TW201108241A (en) 2011-03-01
US9105323B2 (en) 2015-08-11
US20100191999A1 (en) 2010-07-29
JP2012515989A (ja) 2012-07-12
KR20110115587A (ko) 2011-10-21
EP3223281A2 (en) 2017-09-27
CN104699226B (zh) 2017-11-14
TWI514409B (zh) 2015-12-21
EP3223281B1 (en) 2019-07-31
KR101609311B1 (ko) 2016-04-05
CN102292715A (zh) 2011-12-21
EP3223281A3 (en) 2017-12-13
US20150357010A1 (en) 2015-12-10
TWI590255B (zh) 2017-07-01
WO2010085657A3 (en) 2010-10-21
TW201729185A (zh) 2017-08-16
JP2015158948A (ja) 2015-09-03
TWI628665B (zh) 2018-07-01
US9583157B2 (en) 2017-02-28
EP2389633B1 (en) 2017-04-05
JP6041928B2 (ja) 2016-12-14
JP5762312B2 (ja) 2015-08-12

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