CN102290329B - 形成具有lc滤波器和ipd滤波器的rf fem的半导体器件和方法 - Google Patents

形成具有lc滤波器和ipd滤波器的rf fem的半导体器件和方法 Download PDF

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CN102290329B
CN102290329B CN201110160586.4A CN201110160586A CN102290329B CN 102290329 B CN102290329 B CN 102290329B CN 201110160586 A CN201110160586 A CN 201110160586A CN 102290329 B CN102290329 B CN 102290329B
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conductive trace
pass filter
coupled
filter
substrate
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CN102290329A (zh
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金炫泰
李镕泽
金光
安秉勋
刘凯
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Changdian Integrated Circuit Shaoxing Co ltd
Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Abstract

本发明涉及形成具有LC滤波器和IPD滤波器的RF？FEM的半导体器件和方法。半导体器件具有基板和在基板上形成的RF？FEM。RF？FEM包括具有耦合用于接收发射信号的输入的LC低通滤波器。Tx/Rx开关具有耦合到LC滤波器的输出的第一端子。双工器具有耦合到Tx/Rx开关的第二端子的第一端子和用于提供RF信号的第二端子。IPD带通滤波器具有耦合到Tx/Rx开关的第三端子的输入和提供接收信号的输出。LC滤波器包括盘绕以展现电感和互感属性的导电迹线以及耦合到导电迹线的电容器。IPD滤波器包括盘绕以展现电感和互感属性的导电迹线和耦合到导电迹线的电容器。RF？FEM基板可以堆叠在包含RF收发器的半导体封装上。

Description

形成具有LC滤波器和IPD滤波器的RF FEM的半导体器件和方法
技术领域
本发明一般涉及半导体器件，且更具体而言，涉及一种使用IPD工艺在基板上形成具有LC滤波器和IPD滤波器的RFFEM的半导体器件和方法。
背景技术
常常在现代电子产品中发现半导体器件。半导体器件在电部件的数目和密度中变化。分立的半导体器件一般包含一种类型的电部件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器、功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件典型地包含几百个到数以百万的电部件。集成半导体器件的示例包括微控制器、微处理器、电荷耦合器件（CCD）、太阳能电池以及数字微镜器件（DMD）。
半导体器件执行各种的功能，诸如高速计算、发射和接收电磁信号、控制电子器件、将太阳光转变为电力以及产生用于电视显示的视觉投影。在娱乐、通信、功率转换、网络、计算机以及消费产品的领域中发现半导体器件。还在军事应用、航空、汽车、工业控制器和办公设备中发现半导体器件。
半导体器件利用半导体材料的电属性。半导体材料的原子结构允许通过施加电场或基础电流或通过掺杂工艺而操纵其导电性。掺杂向半导体材料引入杂质以操纵和控制半导体器件的导电性。
半导体器件包含有源和无源电结构。包括双极和场效应晶体管的有源结构控制电流的流动。通过改变掺杂水平和施加电场或基础电流，晶体管要么促进要么限制电流的流动。包括电阻器、电容器和电感器的无源结构创建为执行各种电功能所必须的电压和电流之间的关系。无源和有源结构电连接以形成电路，这使得半导体器件能够执行高速计算和其他有用功能。
半导体器件一般使用两个复杂的制造工艺来制造，即，前端制造和和后端制造，每一个可能涉及成百个步骤。前端制造涉及在半导体晶片的表面上形成多个管芯。每个管芯典型地相同且包含通过电连接有源和无源部件而形成的电路。后端制造涉及从完成的晶片分割（singulate）各个管芯且封装管芯以提供结构支撑和环境隔离。
半导体制造的一个目的是生产较小的半导体器件。较小的器件典型地消耗较少的功率、具有较高的性能且可以更高效地生产。另外，较小的半导体器件具有较小的占位面积，这对于较小的终端产品而言是希望的。较小的管芯尺寸可以通过前端工艺中的改进来获得，该前端工艺中的改进导致管芯具有较小、较高密度的有源和无源部件。后端工艺可以通过电互联和封装材料中的改进而导致具有较小占位面积的半导体器件封装。
半导体制造的另一目的是生产较高性能的半导体器件。器件性能中的增加可以通过形成能够以较高速度操作的有源部件来实现。在诸如射频（RF）无线通信的高频应用中，集成无源器件（IPD）通常被包含在半导体器件中。IPD的示例包括电阻器、电容器和电感器。典型的RF系统要求在一个或更多半导体封装中的多个IPD以执行必要的电功能。
在无线RF系统中，RF前端模块（FEM）耦合到用于发射和接收RF信号的天线。RFFEM分离且过滤发射RF信号和接收RF信号以避免RF信号之间的冲突和串扰（cross-over）。分离的发射RF信号和接收RF信号被路由到RF收发器或者从RF收发器接收以用于解调和转换为基带信号以用于进一步信号处理。RF系统可以是蜂窝电话、PDA或其他无线通信器件的一部分。
图1示出耦合到天线12的常规RFFEM10的框图。RFFEM10具有发射部和接收部。在发射部中，来自RF收发器的发射RF信号被路由到功率放大器14的输入以增加信号功率和放大。功率放大器14的输出耦合到检测发射信号功率级的RF耦合器15。发射RF信号通过LC滤波器16过滤且路由到TX/RX开关18，该开关18在发射RF信号和接收RF信号之间切换。当被TX/RX开关18选择时，发射RF信号被路由到双工器20，该双工器20执行从两个端口到一个端口的频率复用以通过天线12发射。
在接收部中，来自天线12的接收RF信号通过双工器20处理以用于从一个端口到两个端口的解复用。当被TX/RX开关18选择时，接收RF信号被路由到表面声波（SAW）滤波器22。SAW滤波器22使用压电晶体或陶瓷将电信号转换成机械波。机械波通过压电结构延迟以通过拒绝带外信号而提供窄带通响应。过滤的波被转换回电信号且作为接收RF信号路由到RF收发器。
图2示出用于实现RFFEM10的常规半导体封装23。基板24是具有多个内部电介质层26和诸如银或铜的导电层28的多层低温共烧陶瓷（LTCC）叠层。LTCC基板24包括在多层基板内的诸如电阻器30、电容器32和电感器34的内部无源部件以及嵌入式RF电路36。TX/RX开关管芯38和分立电阻器40安装到LTCC基板24的顶表面且电连接到导电层28。SAW滤波器管芯42安装到LTCC基板24且电连接到导电层28。SAW滤波器42由于其机械特征而相对较大，但是可以放置在LTCC基板24中形成的凹陷中以试图减小半导体封装23的高度。
作为具有SAW滤波器管芯42的实现的半导体封装23，RFFEM10代表相对笨重和复杂的结构且涉及高的制作成本。由于较小封装和较低成本的要求驱动着市场，需要附加的工作来改善RFFEM设计。
发明内容
对于没有笨重SAW滤波器的RFFEM存在需求。因此，在一个实施例中，本发明是一种制作半导体器件的方法，其包含以下步骤：提供基板，以及在基板上形成RFFEM。该RFFEM包括：形成LC低通滤波器，该LC低通滤波器具有耦合用于接收发射信号的输入；形成Tx/Rx开关，该Tx/Rx开关具有耦合到LC低通滤波器的输出的第一端子；形成双工器，该双工器具有耦合到Tx/Rx开关的第二端子的第一端子和用于提供RF信号的第二端子；以及形成IPD带通滤波器，该IPD带通滤波器具有耦合到Tx/Rx开关的第三端子以用于接收接收信号的输入和提供过滤的接收信号的输出。
在另一实施例中，本发明是一种制作半导体器件的方法，其包含以下步骤：提供基板，以及在基板上形成RFFEM。RFFEM包括：形成LC滤波器，该LC滤波器具有耦合用于接收发射信号的输入和提供过滤的发射信号的输出；以及形成IPD滤波器，该IPD滤波器具有耦合用于接收接收信号的输入和提供过滤的接收信号的输出。
在另一实施例中，本发明是一种制作半导体器件的方法，其包含以下步骤：提供基板，在基板上形成LC滤波器，以及在基板上形成IPD滤波器。该LC滤波器具有耦合用于接收发射信号的输入和提供过滤的发射信号的输出。该IPD滤波器具有耦合用于接收接收信号的输入和提供过滤的接收信号的输出。
在另一实施例中，本发明是一种半导体器件，其包含基板和在基板上形成的LC滤波器。该LC滤波器具有耦合用于接收发射信号的输入和提供过滤的发射信号的输出。IPD滤波器在基板上形成。该IPD滤波器具有耦合用于接收接收信号的输入和提供过滤的接收信号的输出。
附图说明
图1说明具有SAW滤波器的常规RFFEM的框图；
图2说明实现图1的具有SAW滤波器的RFFEM的常规LTCC基板；
图3说明具有安装到其表面的不同类型封装的PCB；
图4a-4c说明安装到PCB的代表性半导体封装的进一步细节；
图5说明用在无线通信器件中的RF系统；
图6说明图5的RF系统中的RFFEM的框图；
图7说明具有有源表面的半导体基板；
图8说明具有在半导体基板的有源表面上形成的IPD的半导体封装；
图9说明具有LC滤波器和IPD滤波器的RFFEM的物理电路布局；
图10说明LC滤波器的物理电路布局；
图11说明LC滤波器的示意图；
图12说明IPD滤波器的物理电路布局；
图13说明IPD滤波器的示意图；
图14说明安装到RF收发器管芯的RFFEM半导体封装；以及
图15说明在高电阻率基板上安装的RFFEM半导体封装。
具体实施方式
在下面的描述中，参考图以一个或更多实施例描述本发明，在这些图中相似的标号代表相同或类似的元件。尽管就用于实现本发明目的的最佳模式描述本发明，但是本领域技术人员应当理解，其旨在覆盖可以包括在如下面的公开和附图支持的所附权利要求及其等价物限定的本发明的精神和范围内的备选、修改和等价物。
半导体器件一般使用两个复杂制造工艺来制造：前端制造和后端制造。前端制造涉及在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包含有源和无源电部件，它们电连接以形成功能电电路。诸如晶体管和二极管的有源电部件具有控制电流流动的能力。诸如电容器、电感器、电阻器和变压器的无源电部件创建为执行电路功能所必须的电压和电流之间的关系。
通过包括掺杂、沉积、光刻、蚀刻和平整化的一系列工艺步骤在半导体晶片的表面上形成无源和有源部件。掺杂通过诸如离子注入或热扩散的技术将杂质引入到半导体材料中。掺杂工艺修改了有源器件中半导体材料的导电性，将半导体材料转变为绝缘体、导体，或者响应于电场或基础电流而动态地改变半导体材料的导电性。晶体管包含不同类型和掺杂程度的区域，其按照需要被布置为使得当施加电场或基本电流时晶体管能够促进或限制电流的流动。
通过具有不同电属性的材料层形成有源和无源部件。层可以通过部分由被沉积的材料类型确定的各种沉积技术来形成。例如，薄膜沉积可能涉及化学汽相沉积（CVD）、物理汽相沉积（PVD）、电解电镀和化学电镀工艺。每一层一般被图案化以形成有源部件、无源部件或部件之间的电连接的部分。
可以使用光刻对层进行图案化，光刻涉及例如光刻胶的光敏材料在待被图案化的层上的沉积。使用光，图案从光掩模转印到光刻胶。受光影响的光刻胶图案的部分使用溶剂来去除，露出待被图案化的底层的部分。光刻胶的剩余部分被去除，留下图案化层。备选地，一些类型的材料通过使用诸如化学电镀和电解电镀这样的技术来直接向原先沉积/蚀刻工艺形成的区域或通孔沉积材料而被图案化。
在现有图案上沉积材料的薄膜可以放大底层图案且形成不均匀的平坦表面。需要均匀的平坦表面来生产更小且更致密堆叠的有源和无源部件。平整化可以用于从晶片的表面去除材料且产生均匀的平坦表面。平整化涉及使用抛光垫对晶片的表面进行抛光。研磨材料和腐蚀化学物在抛光期间被添加到晶片的表面。化学物的研磨和腐蚀行为的组合机械行为去除任何不规则拓扑，导致均匀的平坦表面。
后端制造指将完成的晶片切割或分割为各个管芯且然后封装管芯以用于结构支撑和环境隔离。为了分割管芯，晶片沿着称为切割线或划线的晶片的非功能区域被划片且折断。使用激光切割工具或锯条来分割晶片。在分割之后，各个芯片被安装到封装基板，该封装基板包括引脚或接触焊盘以用于与其他系统部件互连。在半导体管芯上形成的接触焊盘然后连接到封装内的接触焊盘。电连接可以使用焊料凸点、柱形凸点、导电胶或引线接合来制成。密封剂或其他成型材料沉积在封装上以提供物理支撑和电隔离。完成的封装然后被插入到电系统中且使得半导体器件的功能性对于其他系统部件可用。
图3说明具有芯片载体基板或印刷电路板（PCB）52的电子器件50，该芯片载体基板或印刷电路板（PCB）52具有安装在其表面上的多个半导体封装。取决于应用，电子器件50可以具有一种类型的半导体封装或多种类型的半导体封装。用于说明性目的，在图3中示出了不同类型的半导体封装。
电子器件50可以是使用半导体封装以执行一个或更多电功能的独立系统。备选地，电子器件50可以是较大系统的子部件。例如，电子器件50可以是蜂窝电话、个人数字助理（PDA）、数码摄像机（DVC）或其他电子通信器件的一部分。备选地，电子器件50可以是图形卡、网络接口卡或可以被插入到计算机中的其他信号处理卡。半导体封装可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、RF电路、分立器件或其他半导体管芯或电部件。微型化和重量减小对于这些产品被市场接受是至关重要的。半导体器件之间的距离必须减小以实现更高的密度。
在图3中，PCB52提供用于安装到PCB上的半导体封装的结构支撑和电互连的一般性基板。使用蒸发、电解电镀、化学电镀、丝网印刷或者其他合适的金属沉积工艺，导电信号迹线54在PCB的表面上或其层内形成。信号迹线54提供半导体封装、安装的部件以及其他外部系统部件中的每一个之间的电通信。迹线54还向半导体封装中的每一个提供功率和接地连接。
在一些实施例中，半导体器件具有两个封装级别。第一级封装是用于机械和电附接半导体管芯到中间载体的技术。第二级封装涉及机械和电附接中间载体到PCB。在其他实施例中，半导体器件可以仅具有第一级封装，其中管芯被直接机械和电地安装到PCB。
用于说明目的，在PCB52上示出包括引线接合封装56和倒装芯片58的若干类型的第一级封装。另外，示出在PCB52上安装的若干类型的第二级封装，包括球栅阵列（BGA）60、凸点芯片载体（BCC）62、双列直插式封装（DIP）64、岸面栅格阵列（LGA）66、多芯片模块（MCM）68、四方扁平无引脚封装（QFN）70以及方形扁平封装72。取决于系统需求，使用第一和第二级封装类型的任何组合配置的半导体封装以及其他电子部件的任何组合可以连接到PCB52。在一些实施例中，电子器件50包括单一附接的半导体封装，而其他实施例需要多个互连封装。通过在单个基板上组合一个或更多半导体封装，制造商可以将预制部件结合到电子器件和系统中。因为半导体封装包括复杂的功能性，可以使用较廉价的部件和流水线制造工艺来制造电子器件。所得到的器件较不倾向于发生故障且对于制造而言较不昂贵，导致针对消费者的较少的成本。
图4a-4c示出示例性半导体封装。图4a说明安装在PCB52上的DIP64的进一步细节。半导体管芯74包括有源区域，该有源区域包含实现为根据管芯的电设计而在管芯内形成且电互连的有源器件、无源器件、导电层以及电介质层的模拟或数字电路。例如，电路可以包括一个或更多晶体管、二极管、电感器、电容器、电阻器以及在半导体管芯74的有源区域内形成的其他电路元件。接触焊盘76是诸如铝（Al）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）或银（Ag）的一层或多层导电材料，且电连接到半导体管芯74内形成的电路元件。在DIP64的组装期间，半导体管芯74使用金-硅共熔层或者诸如热环氧树脂或环氧树脂的粘合剂材料而安装到中间载体78。封装体包括诸如聚合物或陶瓷的绝缘封装材料。导线80和引线接合82提供半导体管芯74和PCB52之间的电互连。密封剂84沉积在封装上，以通过防止湿气和颗粒进入封装且污染管芯74或引线接合82而进行环境保护。
图4b说明安装在PCB52上的BCC62的进一步细节。半导体管芯88使用底层填料或者环氧树脂粘合剂材料92而安装在载体90上。引线接合94提供接触焊盘96和98之间的第一级封装互连。成型化合物或密封剂100沉积在半导体管芯88和引线接合94上，从而为器件提供物理支撑和电隔离。接触焊盘102使用诸如电解电镀或化学电镀之类的合适的金属沉积工艺而在PCB52的表面上形成以防止氧化。接触焊盘102电连接到PCB52中的一个或更多导电信号迹线54。凸点104在BCC62的接触焊盘98和PCB52的接触焊盘102之间形成。
在图4c中，使用倒装芯片类型第一级封装将半导体管芯58面朝下地安装到中间载体106。半导体管芯58的有源区域108包含实现为根据管芯的电设计而形成的有源器件、无源器件、导电层以及电介质层的模拟或数字电路。例如，电路可以包括一个或更多晶体管、二极管、电感器、电容器、电阻器以及有源区域108内的其他电路元件。半导体管芯58通过凸点110电和机械连接到载体106。
使用利用凸点112的BGA类型第二级封装，BGA60电且机械连接到PCB52。半导体管芯58通过凸点110、信号线114和凸点112电连接到PCB52中的导电迹线54。成型化合物或密封剂116被沉积在半导体管芯58和载体106上以为器件提供物理支撑和电隔离。倒装芯片半导体器件提供从半导体管芯58上的有源器件到PCB52上的导电迹线的短导电路径以便减小信号传播距离、降低电容且改善整体电路性能。在另一实施例中，半导体管芯58可以使用倒装芯片类型第一级封装来直接机械和电地连接到PCB52而不使用中间载体106。
图5说明包括耦合到用于发射和接收无线RF信号的天线124的RF前端模块（FEM）122的RF系统120。RFFEM122分离且过滤发射RF信号（Tx）和接收RF信号（Rx）以避免RF信号之间的冲突或串扰。Tx信号和Rx信号被路由到RF收发器126或者从RF收发器126接收以用于调制和转换为基带信号。基带信号处理块128对基带信号执行必要的电功能。RF系统120可以用在蜂窝电话、PDA或其他无线通信器件中。
图6说明RFFEM122的框图。RFFEM122具有发射部和接收部。在发射部中，来自RF收发器126的Tx信号被路由到功率放大器130的输入以增加信号功率和放大。功率放大器230的输出耦合到检测TX信号功率级的RF耦合器132。Tx信号被LC滤波器134低通过滤且路由到Tx/Rx开关136，该Tx/Rx开关136在Tx信号和Rx信号之间切换。当被Tx/Rx开关136选择时，Tx信号被路由到双工器138，该双工器138执行从两个端口到一个端口的频率复用以用于被天线124发射。
在接收部中，来自天线124的Rx信号通过双工器138处理以用于从一个端口到两个端口的频率解复用。当被Tx/Rx开关136选择时，Rx被路由到IPD滤波器140以用于带通过滤。过滤的Rx信号被路由到RF收发器126以转换到基带以用于块128的信号处理。
与图3和4a-4c相关，图7示出包含诸如硅、锗、砷化镓或其他用于结构支撑的体半导体材料的基底材料的半导体基板150。有源区域152在半导体基板150的表面上形成。有源区域152包含模拟或数字电路，该模拟或数字电路实现为根据其电设计和功能而在基板150内形成且电互连的有源器件、无源器件、导电层以及电介质层。例如，电路可以包括一个或更多晶体管、二极管以及在有源表面152内形成的其他电路元件以实现模拟电路或数字电路。有源区域152占用半导体管芯150的整体厚度或高度H的约5-10%。在一个实施例中，半导体基板150占用3.2毫米（mm）×2.2mm的面积。
图8示出在有源表面152上或上方形成的用于RF信号处理的多个IPD，诸如薄膜电感器、电容器和电阻器以及其他半导体管芯或部件。在该实施例中，功率放大器130和RF耦合器132在基板150的外部形成。IPD滤波器140在基板150的有源表面152上形成。IPD158是在有源表面152上形成的电阻器。IPD160是金属绝缘体金属（MIM）电容器，其具有位于金属层164和166之间且被钝化层168覆盖的电介质层162。IPD170是具有在钝化层174上形成的盘绕导电层172的电感器。来自图6的Tx/Rx开关136和双工器138在有源表面152上形成。使用膏印、压塑成型、转印成型、液封成型、真空压合、旋涂或其他合适的涂敷器，密封剂或成型化合物176沉积在部件136-170和有源表面152上。密封剂176可以是聚合物复合材料，诸如是具有填充剂的环氧树脂、具有填充剂的环氧丙烯酸脂或具有适当填充剂的聚合物。密封剂176是不导电的且环境保护半导体器件以免受外部元件和污染物的影响。
包含在公共基板150上形成的IPD140、158、160和170以及其他RF信号处理部件的半导体封装178可以用在高频应用中，诸如微波雷达、电信、无线通信、电子开关和执行RF电功能的其他器件。IPD为电路功能提供电特性，诸如平衡不平衡（平衡不平衡变换器）、谐振器、高通滤波器、低通滤波器、带通滤波器（BPF）、对称高Q谐振变压器、匹配网络、RF耦合器以及调谐电容器。例如，IPD可以用作可以位于天线和收发器之间的前端无线RF部件。无线应用可以是使用诸如宽带码分多址（WCDMA）带（PCS、IMT、低）和全球移动通信（GSM）带（低和高）的多带操作的蜂窝电话。
图9示出半导体封装178的公共基板150上的小形状因子的RFFEM122的一部分的顶视物理布局。在基板150的发射部中，LC滤波器134从功率放大器130和RF耦合器132接收Tx信号。根据图6，过滤的Tx信号被路由到Tx/Rx开关136和双工器138以用于发射。
图10示出包括用于Tx信号的平衡不平衡变换器或低通滤波器布置中的导电迹线或线圈179、180、181、182和183以及电容器184、185、186、187、188、189和191的LC滤波器134的物理布局的进一步细节。导电迹线179-183使用盘绕以呈现电感属性的条线导电迹线来实现。导电迹线可以是使用溅射、电解电镀、化学电镀或其他合适的金属沉积工艺形成的Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料的一层或多层。电容器184-191使用薄膜电介质来实现以增加电容密度。
图11示出具有电感器179-183和电容器184-191的低通滤波器134的电示意图。尤其是，电容器184耦合在导电迹线179的第一和第二终端端子之间。电容器185和186串联耦合在导电迹线180的第一和第二终端端子之间。导电迹线179和180交织以呈现互感属性。导电迹线179-183可以是圆形、椭圆形、多边形或者等角形状（conformalshape）以用于提高的Q因子和减小的管芯面积。
返回图9，在基板150的接收部中，Rx信号从双工器138和Tx/Rx开关136路由到IPD滤波器140。图12示出在用于Rx信号的带通滤波器布置中包括导电迹线或线圈192、193、194、195、196、197、198和199以及电容器200、201、202、204、206、207、208和210的IPD滤波器140的进一步细节。导电迹线192-199使用盘绕且交织以呈现电感和互感属性的条线导电迹线来实现。导电迹线可以是使用溅射、电解电镀、化学电镀或其他合适的金属沉积工艺形成的Al、Cu、Sn、Ni、Au、Ag或其他合适的导电材料的一层或多层。电容器200-210使用薄膜电介质来实现以增加电容密度。
导电迹线192具有耦合到端口212和端口214的第一和第二终端端子以用于差模操作。在一个实施例中，端口212是单端不平衡端口且端口214是接地端子。备选地，端口212是单端不平衡端口且端口214是接地端口。电容器200耦合在端口212和端口214之间。导电迹线193具有耦合到平衡端口216和218的第一和第二终端端子以用于差模操作。电容器201耦合在端口216和端口218之间。电容器202和204串联耦合在导电迹线194的终端端子之间。导电迹线194使用平面分离以非交叠布置而设置在导电迹线192和193的周界附近。导电迹线195在导电迹线194的周界附近形成且连接到低阻抗接地点以减小器件间干扰和辐射损失。导电迹线192相对于导电迹线193是不同的尺寸和/或形状。在一个实施例中，导电迹线192具有30-50微米（μm）的宽度和200-400μm的外径。导电迹线193具有30-50μm的宽度以及400-600μm的外径。导电迹线192与导电迹线193分离100μm；导电迹线192与导电迹线194分离100μm；导电迹线193与导电迹线194分离100μm。互感在导电迹线192和193之间、在导电迹线192和194以及导电迹线193和194之间形成。导电迹线192和193可以是圆形、椭圆形、多边形或等角形状以用于增强的Q因子和减小的管芯面积。不同大小的导电迹线192和193产生不同的端口阻抗。
导电迹线196具有耦合到端口220和端口222的第一和第二终端端子以用于差模操作。在一个实施例中，端口220是单端不平衡端口且端口222是接地端子。备选地，端口220是单端不平衡端口且端口222是接地端子。电容器206耦合在端口220和端口222之间。导电迹线197具有耦合到平衡端口224和226的第一和第二终端端子以用于差模操作。电容器207耦合在端口224和端口226之间。电容器208和210串联耦合在导电迹线198的终端端子之间。导电迹线198使用平面分离以非交叠布置而设置在导电迹线196和197的周界附近。导电迹线199在导电迹线198的周界附近形成且连接到低阻抗接地点以减小器件间干扰和辐射损失。导电迹线196相对于导电迹线197是不同的尺寸和/或形状。在一个实施例中，导电迹线196具有30-50微米的宽度和200-400μm的外径。导电迹线197具有30-50μm的宽度以及400-600μm的外径。导电迹线196与导电迹线197分离100μm；导电迹线196与导电迹线198分离100μm；导电迹线197与导电迹线198分离100μm。互感在导电迹线196和197之间、在导电迹线196和198以及导电迹线197和198之间形成。导电迹线196和197可以是圆形、椭圆形、多边形或等角形状以用于增强的Q因子和减小的管芯面积。不同大小的导电迹线196和197产生不同的端口阻抗。
图13示出具有电感器192、193和194以及电容器200、201、202和204的IPD带通滤波器140的电示意图。电感器192-194盘绕以在电感器之间形成相对小的磁耦合以用于阻止带中的高衰减。例如，电感器192、193和194的值分别被设置为1.89、4.91和2.15纳亨（nH）。电容器200、201、202和204的值分别被设置为1.97、3.9和3.9皮法（pF）。箭头说明电感器192、193和194之间的互感。电感器192和193之间的耦合系数是CC192-193=0.048，电感器193和194之间的耦合系数是CC193-194=-0.148，且电感器192和194之间的耦合系数是CC192-194=0.148。电感器192和194之间的耦合通过增加分离而减小，导致尤其在响应的高频边缘处的较窄的带通响应。电感器193和194之间的耦合通过减小分离而增加，且在带通的较低侧的衰减极点移动到高频，导致较窄的带宽、具有较高的阻止。电感器196、197和198以及电容器206、207、208和210具有类似的示意表达。
图14示出包含RFFEM122的半导体封装178，该RFFEM122安装到包含RF收发器126的半导体封装230。功率放大器130和RF耦合器132可以集成在半导体封装230内或者实现为单独的部件。半导体封装178使用凸点232电连接到半导体封装230。底层填料材料234在凸点232周围沉积在半导体封装178和230之间。堆叠的半导体封装178和230被安装到层叠基板236且使用凸点238电连接。半导体封装178使用接合引线240电连接到基板236。基板236包括用于半导体封装178和230以及外部部件之间的信号路由的多个导电迹线242。
如图6-13所示，RFFEM122可以在具有LC滤波器134和IPD滤波器140的低成本半导体封装178中实现，提供用于Tx信号和Rx信号的处理信道。与图1-2中描述的笨重体SAW滤波器和LTCC基板相比，半导体封装178更小且更成本有效。
图15示出具有高电阻率基板244的实施例。绝缘层246在基板244上形成。导电层248在绝缘层246上形成。诸如电感器、电容器和电阻器的IPD250和252可以在导电层248上形成。聚酰亚胺基板254在绝缘层246上形成。具有IPD滤波器140的RFFEM122在基板254上形成。包含诸如功率放大器130、RF耦合器132、Tx/Rx开关136、双工器138的RF部件的半导体封装256安装到基板254且使用接合引线258电连接。半导体封装256还使用接合引线260电连接到导电层248。
尽管已经详细说明了本发明的一个或更多实施例，但是本领域技术人员应当意识到，可以在不偏离如随后的权利要求提及的本发明的范围的情况下对这些实施例做出修改和适应。

Claims (14)

1.一种制作半导体器件的方法，包含：
通过以下步骤形成射频前端模块：
(a)提供第一基板；(b)在第一基板的表面上形成电感器电容器低通滤波器，该电感器电容器低通滤波器具有耦合的用于接收发射信号的输入；
(c)在第一基板的表面上形成发射/接收开关，该发射/接收开关具有耦合到电感器电容器低通滤波器的输出的第一端子；
(d)在第一基板的表面上形成双工器，该双工器具有耦合到发射/接收开关的第二端子的第一端子和用于提供射频信号的第二端子；以及
(e)在第一基板的表面上形成集成无源器件带通滤波器，该集成无源器件带通滤波器具有耦合到发射/接收开关的第三端子以用于接收接收信号的输入和提供过滤的接收信号的输出；
将所述射频前端模块安装在包含射频收发器的半导体封装上；以及
将所述半导体封装安装到第二基板。
2.根据权利要求1所述的方法，其中形成集成无源器件带通滤波器包括：
形成第一导电迹线，该第一导电迹线盘绕以展现电感属性且具有耦合到集成无源器件带通滤波器的输入的第一和第二端；
形成第二导电迹线，该第二导电迹线盘绕以展现电感属性且具有耦合到集成无源器件带通滤波器的输出的第一和第二端，该第一导电迹线布置在该第二导电迹线附近以展现互感属性；以及
形成第三导电迹线，该第三导电迹线盘绕以展现电感属性且具有第一和第二端，该第三导电迹线布置在第一和第二导电迹线附近以展现互感属性。
3.根据权利要求2所述的方法，其中形成该集成无源器件带通滤波器还包括：
在该第一导电迹线的第一和第二端之间形成第一电容器；
在该第二导电迹线的第一和第二端之间形成第二电容器；以及
在该第三导电迹线的第一和第二端之间形成第三电容器。
4.根据权利要求1所述的方法，其中形成该电感器电容器低通滤波器包括：
形成第一导电迹线，该第一导电迹线盘绕以展现电感属性且具有耦合到该电感器电容器低通滤波器的输出的第一和第二端；
形成第二导电迹线，该第二导电迹线盘绕以展现电感属性且具有耦合到该电感器电容器低通滤波器的输入的第一和第二端，该第一导电迹线布置在该第二导电迹线附近以展现互感属性。
5.根据权利要求4所述的方法，其中形成电感器电容器低通滤波器还包括：
在该第一导电迹线的第一和第二端之间形成第一电容器；以及
在该第二导电迹线的第一和第二端之间形成第二电容器。
6.一种制作半导体器件的方法，包含：
提供基板；
在基板的表面上形成电感器电容器低通滤波器，该电感器电容器低通滤波器具有耦合的用于接收发射信号的输入和提供过滤的发射信号的输出；
在基板的表面上形成发射/接收开关，该发射/接收开关具有耦合到电感器电容器低通滤波器的输出的第一端子；
在基板的表面上形成双工器，该双工器具有耦合到发射/接收开关的第二端子的第一端子和用于提供射频信号的第二端子；以及
在基板的表面上形成集成无源器件带通滤波器，该集成无源器件带通滤波器具有耦合的用于接收接收信号的输入和提供过滤的接收信号的输出。
7.根据权利要求6所述的方法，其中形成集成无源器件带通滤波器包括：
形成第一导电迹线，该第一导电迹线盘绕以展现电感属性且具有耦合到集成无源器件带通滤波器的输入的第一和第二端；
形成第二导电迹线，该第二导电迹线盘绕以展现电感属性且具有耦合到集成无源器件带通滤波器的输出的第一和第二端，该第一导电迹线布置在该第二导电迹线附近以展现互感属性；以及
形成第三导电迹线，该第三导电迹线盘绕以展现电感属性且具有第一和第二端，该第三导电迹线布置在第一和第二导电迹线附近以展现互感属性。
8.根据权利要求7所述的方法，其中形成该集成无源器件带通滤波器还包括：
在该第一导电迹线的第一和第二端之间形成第一电容器；
在该第二导电迹线的第一和第二端之间形成第二电容器；以及
在该第三导电迹线的第一和第二端之间形成第三电容器。
9.根据权利要求6所述的方法，其中形成该电感器电容器低通滤波器包括：
形成第一导电迹线，该第一导电迹线盘绕以展现电感属性且具有耦合到该电感器电容器低通滤波器的输出的第一和第二端；以及
形成第二导电迹线，该第二导电迹线盘绕以展现电感属性且具有耦合到该电感器电容器低通滤波器的输入的第一和第二端，该第一导电迹线布置在该第二导电迹线附近以展现互感属性。
10.一种半导体器件，包含：
基板；以及
形成在基板的表面上的射频前端模块，该射频前端模块包括：
(a)电感器电容器滤波器，该电感器电容器滤波器形成在基板的表面上并且被耦合用于接收发射信号并提供过滤的发射信号；以及
(b)集成无源器件滤波器，该集成无源器件滤波器形成在基板的表面上并且被耦合用于接收接收信号和提供过滤的接收信号。
11.根据权利要求10所述的半导体器件，其中该射频前端模块还包括：
发射/接收开关，该发射/接收开关包括耦合到电感器电容器滤波器的输出的第一端子和耦合到集成无源器件滤波器的输入的第二端子；以及
双工器，该双工器包括耦合到发射/接收开关的第三端子的第一端子和用于提供射频信号的第二端子。
12.根据权利要求10所述的半导体器件，其中该集成无源器件滤波器包括：
第一导电迹线，该第一导电迹线盘绕以展现电感属性且包括耦合到集成无源器件滤波器的输入的第一和第二端；
第二导电迹线，该第二导电迹线盘绕以展现电感属性且包括耦合到集成无源器件滤波器的输出的第一和第二端，该第二导电迹线布置在该第一导电迹线附近以展现互感属性；以及
第三导电迹线，该第三导电迹线盘绕以展现电感属性且该第三导电迹线布置在第一和第二导电迹线附近以展现互感属性。
13.根据权利要求12所述的半导体器件，其中该集成无源器件滤波器还包括：
耦合在该第一导电迹线的第一和第二端之间的第一电容器；
耦合在该第二导电迹线的第一和第二端之间的第二电容器；以及
耦合在该第三导电迹线的第一和第二端之间的第三电容器。
14.根据权利要求10所述的半导体器件，还包括半导体封装，半导体封装包括射频收发器，其中射频前端模块被安装到半导体封装上并电连接到射频收发器。
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